drivers/i2c/omap24xx_i2c.c

   1 /*
   2  * Basic I2C functions
   3  *
   4  * Copyright (c) 2004 Texas Instruments
   5  *
   6  * This package is free software;  you can redistribute it and/or
   7  * modify it under the terms of the license found in the file
   8  * named COPYING that should have accompanied this file.
   9  *
  10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13  *
  14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
  15  *
  16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
  17  * Rewritten to fit into the current U-Boot framework
  18  *
  19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
  20  *
  21  */
  22
  23 #include <common.h>
  24
  25 #include <asm/arch/i2c.h>
  26 #include <asm/io.h>
  27
  28 static void wait_for_bb (void);
  29 static u16 wait_for_pin (void);
  30 static void flush_fifo(void);
  31
  32 static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
  33
  34 static unsigned int bus_initialized[I2C_BUS_MAX];
  35 static unsigned int current_bus;
  36
  37 void i2c_init (int speed, int slaveadd)
  38 {
  39         int psc, fsscll, fssclh;
  40         int hsscll = 0, hssclh = 0;
  41         u32 scll, sclh;
  42
  43         /* Only handle standard, fast and high speeds */
  44         if ((speed != OMAP_I2C_STANDARD) &&
  45             (speed != OMAP_I2C_FAST_MODE) &&
  46             (speed != OMAP_I2C_HIGH_SPEED)) {
  47                 printf("Error : I2C unsupported speed %d\n", speed);
  48                 return;
  49         }
  50
  51         psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
  52         psc -= 1;
  53         if (psc < I2C_PSC_MIN) {
  54                 printf("Error : I2C unsupported prescalar %d\n", psc);
  55                 return;
  56         }
  57
  58         if (speed == OMAP_I2C_HIGH_SPEED) {
  59                 /* High speed */
  60
  61                 /* For first phase of HS mode */
  62                 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
  63                         (2 * OMAP_I2C_FAST_MODE);
  64
  65                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
  66                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
  67                 if (((fsscll < 0) || (fssclh < 0)) ||
  68                     ((fsscll > 255) || (fssclh > 255))) {
  69                         printf("Error : I2C initializing first phase clock\n");
  70                         return;
  71                 }
  72
  73                 /* For second phase of HS mode */
  74                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  75
  76                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
  77                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
  78                 if (((fsscll < 0) || (fssclh < 0)) ||
  79                     ((fsscll > 255) || (fssclh > 255))) {
  80                         printf("Error : I2C initializing second phase clock\n");
  81                         return;
  82                 }
  83
  84                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
  85                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
  86
  87         } else {
  88                 /* Standard and fast speed */
  89                 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  90
  91                 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
  92                 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
  93                 if (((fsscll < 0) || (fssclh < 0)) ||
  94                     ((fsscll > 255) || (fssclh > 255))) {
  95                         printf("Error : I2C initializing clock\n");
  96                         return;
  97                 }
  98
  99                 scll = (unsigned int)fsscll;
 100                 sclh = (unsigned int)fssclh;
 101         }
 102
 103         writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
 104         udelay(1000);
 105         writew(0x0, &i2c_base->sysc); /* will probably self clear but */
 106
 107         if (readw (&i2c_base->con) & I2C_CON_EN) {
 108                 writew (0, &i2c_base->con);
 109                 udelay (50000);
 110         }
 111
 112         writew(psc, &i2c_base->psc);
 113         writew(scll, &i2c_base->scll);
 114         writew(sclh, &i2c_base->sclh);
 115
 116         /* own address */
 117         writew (slaveadd, &i2c_base->oa);
 118         writew (I2C_CON_EN, &i2c_base->con);
 119
 120         /* have to enable intrrupts or OMAP i2c module doesn't work */
 121         writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
 122                 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
 123         udelay (1000);
 124         flush_fifo();
 125         writew (0xFFFF, &i2c_base->stat);
 126         writew (0, &i2c_base->cnt);
 127
 128         bus_initialized[current_bus] = 1;
 129 }
 130
 131 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 132 {
 133         int i2c_error = 0;
 134         u16 status;
 135
 136         /* wait until bus not busy */
 137         wait_for_bb ();
 138
 139         /* one byte only */
 140         writew (1, &i2c_base->cnt);
 141         /* set slave address */
 142         writew (devaddr, &i2c_base->sa);
 143         /* no stop bit needed here */
 144         writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
 145
 146         status = wait_for_pin ();
 147
 148         if (status & I2C_STAT_XRDY) {
 149                 /* Important: have to use byte access */
 150                 writeb (regoffset, &i2c_base->data);
 151                 udelay (20000);
 152                 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
 153                         i2c_error = 1;
 154                 }
 155         } else {
 156                 i2c_error = 1;
 157         }
 158
 159         if (!i2c_error) {
 160                 /* free bus, otherwise we can't use a combined transction */
 161                 writew (0, &i2c_base->con);
 162                 while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
 163                         udelay (10000);
 164                         /* Have to clear pending interrupt to clear I2C_STAT */
 165                         writew (0xFFFF, &i2c_base->stat);
 166                 }
 167
 168                 wait_for_bb ();
 169                 /* set slave address */
 170                 writew (devaddr, &i2c_base->sa);
 171                 /* read one byte from slave */
 172                 writew (1, &i2c_base->cnt);
 173                 /* need stop bit here */
 174                 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
 175                         &i2c_base->con);
 176
 177                 status = wait_for_pin ();
 178                 if (status & I2C_STAT_RRDY) {
 179 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 180                         *value = readb (&i2c_base->data);
 181 #else
 182                         *value = readw (&i2c_base->data);
 183 #endif
 184                         udelay (20000);
 185                 } else {
 186                         i2c_error = 1;
 187                 }
 188
 189                 if (!i2c_error) {
 190                         writew (I2C_CON_EN, &i2c_base->con);
 191                         while (readw (&i2c_base->stat)
 192                                || (readw (&i2c_base->con) & I2C_CON_MST)) {
 193                                 udelay (10000);
 194                                 writew (0xFFFF, &i2c_base->stat);
 195                         }
 196                 }
 197         }
 198         flush_fifo();
 199         writew (0xFFFF, &i2c_base->stat);
 200         writew (0, &i2c_base->cnt);
 201         return i2c_error;
 202 }
 203
 204 static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
 205 {
 206         int i2c_error = 0;
 207         u16 status, stat;
 208
 209         /* wait until bus not busy */
 210         wait_for_bb ();
 211
 212         /* two bytes */
 213         writew (2, &i2c_base->cnt);
 214         /* set slave address */
 215         writew (devaddr, &i2c_base->sa);
 216         /* stop bit needed here */
 217         writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 218                 I2C_CON_STP, &i2c_base->con);
 219
 220         /* wait until state change */
 221         status = wait_for_pin ();
 222
 223         if (status & I2C_STAT_XRDY) {
 224 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 225                 /* send out 1 byte */
 226                 writeb (regoffset, &i2c_base->data);
 227                 writew (I2C_STAT_XRDY, &i2c_base->stat);
 228
 229                 status = wait_for_pin ();
 230                 if ((status & I2C_STAT_XRDY)) {
 231                         /* send out next 1 byte */
 232                         writeb (value, &i2c_base->data);
 233                         writew (I2C_STAT_XRDY, &i2c_base->stat);
 234                 } else {
 235                         i2c_error = 1;
 236                 }
 237 #else
 238                 /* send out two bytes */
 239                 writew ((value << 8) + regoffset, &i2c_base->data);
 240 #endif
 241                 /* must have enough delay to allow BB bit to go low */
 242                 udelay (50000);
 243                 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
 244                         i2c_error = 1;
 245                 }
 246         } else {
 247                 i2c_error = 1;
 248         }
 249
 250         if (!i2c_error) {
 251                 int eout = 200;
 252
 253                 writew (I2C_CON_EN, &i2c_base->con);
 254                 while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
 255                         udelay (1000);
 256                         /* have to read to clear intrrupt */
 257                         writew (0xFFFF, &i2c_base->stat);
 258                         if(--eout == 0) /* better leave with error than hang */
 259                                 break;
 260                 }
 261         }
 262         flush_fifo();
 263         writew (0xFFFF, &i2c_base->stat);
 264         writew (0, &i2c_base->cnt);
 265         return i2c_error;
 266 }
 267
 268 static void flush_fifo(void)
 269 {       u16 stat;
 270
 271         /* note: if you try and read data when its not there or ready
 272          * you get a bus error
 273          */
 274         while(1){
 275                 stat = readw(&i2c_base->stat);
 276                 if(stat == I2C_STAT_RRDY){
 277 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 278                         readb(&i2c_base->data);
 279 #else
 280                         readw(&i2c_base->data);
 281 #endif
 282                         writew(I2C_STAT_RRDY,&i2c_base->stat);
 283                         udelay(1000);
 284                 }else
 285                         break;
 286         }
 287 }
 288
 289 int i2c_probe (uchar chip)
 290 {
 291         int res = 1; /* default = fail */
 292
 293         if (chip == readw (&i2c_base->oa)) {
 294                 return res;
 295         }
 296
 297         /* wait until bus not busy */
 298         wait_for_bb ();
 299
 300         /* try to read one byte */
 301         writew (1, &i2c_base->cnt);
 302         /* set slave address */
 303         writew (chip, &i2c_base->sa);
 304         /* stop bit needed here */
 305         writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
 306         /* enough delay for the NACK bit set */
 307         udelay (50000);
 308
 309         if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
 310                 res = 0;      /* success case */
 311                 flush_fifo();
 312                 writew(0xFFFF, &i2c_base->stat);
 313         } else {
 314                 writew(0xFFFF, &i2c_base->stat);         /* failue, clear sources*/
 315                 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
 316                 udelay(20000);
 317                 wait_for_bb ();
 318         }
 319         flush_fifo();
 320         writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
 321         writew(0xFFFF, &i2c_base->stat);
 322         return res;
 323 }
 324
 325 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 326 {
 327         int i;
 328
 329         if (alen > 1) {
 330                 printf ("I2C read: addr len %d not supported\n", alen);
 331                 return 1;
 332         }
 333
 334         if (addr + len > 256) {
 335                 printf ("I2C read: address out of range\n");
 336                 return 1;
 337         }
 338
 339         for (i = 0; i < len; i++) {
 340                 if (i2c_read_byte (chip, addr + i, &buffer[i])) {
 341                         printf ("I2C read: I/O error\n");
 342                         i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 343                         return 1;
 344                 }
 345         }
 346
 347         return 0;
 348 }
 349
 350 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
 351 {
 352         int i;
 353
 354         if (alen > 1) {
 355                 printf ("I2C read: addr len %d not supported\n", alen);
 356                 return 1;
 357         }
 358
 359         if (addr + len > 256) {
 360                 printf ("I2C read: address out of range\n");
 361                 return 1;
 362         }
 363
 364         for (i = 0; i < len; i++) {
 365                 if (i2c_write_byte (chip, addr + i, buffer[i])) {
 366                         printf ("I2C read: I/O error\n");
 367                         i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 368                         return 1;
 369                 }
 370         }
 371
 372         return 0;
 373 }
 374
 375 static void wait_for_bb (void)
 376 {
 377         int timeout = 10;
 378         u16 stat;
 379
 380         writew(0xFFFF, &i2c_base->stat);         /* clear current interruts...*/
 381         while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
 382                 writew (stat, &i2c_base->stat);
 383                 udelay (50000);
 384         }
 385
 386         if (timeout <= 0) {
 387                 printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
 388                         readw (&i2c_base->stat));
 389         }
 390         writew(0xFFFF, &i2c_base->stat);         /* clear delayed stuff*/
 391 }
 392
 393 static u16 wait_for_pin (void)
 394 {
 395         u16 status;
 396         int timeout = 10;
 397
 398         do {
 399                 udelay (1000);
 400                 status = readw (&i2c_base->stat);
 401         } while (  !(status &
 402                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
 403                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
 404                     I2C_STAT_AL)) && timeout--);
 405
 406         if (timeout <= 0) {
 407                 printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
 408                         readw (&i2c_base->stat));
 409                         writew(0xFFFF, &i2c_base->stat);
 410 }
 411         return status;
 412 }
 413
 414 int i2c_set_bus_num(unsigned int bus)
 415 {
 416         if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
 417                 printf("Bad bus: %d\n", bus);
 418                 return -1;
 419         }
 420
 421 #if I2C_BUS_MAX==3
 422         if (bus == 2)
 423                 i2c_base = (struct i2c *)I2C_BASE3;
 424         else
 425 #endif
 426         if (bus == 1)
 427                 i2c_base = (struct i2c *)I2C_BASE2;
 428         else
 429                 i2c_base = (struct i2c *)I2C_BASE1;
 430
 431         current_bus = bus;
 432
 433         if(!bus_initialized[current_bus])
 434                 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 435
 436         return 0;
 437 }