drivers/i2c/u8500_i2c.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Basic U-Boot I2C interface for STn8500/DB8500
   5  * Author: Michael Brandt <Michael.Brandt@stericsson.com> for ST-Ericsson
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 /*
  23  * Only 7-bit I2C device addresses are supported.
  24  */
  25
  26 #include <common.h>
  27 #include <i2c.h>
  28
  29 #include "u8500_i2c.h"
  30 #include <asm/io.h>
  31 #include <asm/arch/clock.h>
  32
  33 #define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100)     /* I2C bus timeout */
  34 #define U8500_I2C_FIFO_FLUSH_COUNTER    500000          /* flush "timeout" */
  35 #define U8500_I2C_SCL_FREQ              100000          /* I2C bus clock freq */
  36 #define U8500_I2C_INPUT_FREQ            48000000        /* Input clock freq */
  37 #define TX_FIFO_THRESHOLD       0x4
  38 #define RX_FIFO_THRESHOLD       0x4
  39 #define SLAVE_SETUP_TIME 14 /* Slave data setup time, 250ns for 48MHz i2c_clk */
  40
  41 #define WRITE_FIELD(var, mask, shift, value) \
  42                         (var = ((var & ~(mask)) | ((value) << (shift))))
  43
  44 static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX];
  45 static unsigned int i2c_bus_num;
  46 static unsigned int i2c_bus_speed[] = {
  47         CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED,
  48         CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED
  49 };
  50 static struct u8500_i2c_regs *i2c_dev[] = {
  51         (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE,
  52         (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE,
  53         (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE,
  54         (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE,
  55 };
  56
  57 static struct {
  58         int periph;
  59         int pcken;
  60         int kcken;
  61 } i2c_clock_bits[] = {
  62         {3, 3, 3}, /* I2C0 */
  63         {1, 2, 2}, /* I2C1 */
  64         {1, 6, 6}, /* I2C2 */
  65         {2, 0, 0}, /* I2C3 */
  66 };
  67
  68 static void i2c_set_bit(void *reg, u32 mask)
  69 {
  70         writel(readl(reg) | mask, reg);
  71 }
  72
  73 static void i2c_clr_bit(void *reg, u32 mask)
  74 {
  75         writel(readl(reg) & ~mask, reg);
  76 }
  77
  78 static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value)
  79 {
  80         writel((readl(reg) & ~mask) | (value << shift), reg);
  81 }
  82
  83 static int __i2c_set_bus_speed(unsigned int speed)
  84 {
  85         u32 value;
  86         struct u8500_i2c_regs *i2c_regs;
  87
  88         i2c_regs = i2c_dev[i2c_bus_num];
  89
  90         /* Select standard (100 kbps) speed mode */
  91         i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM,
  92                         U8500_I2C_CR_SHIFT_SM, 0x0);
  93
  94         /*
  95          * Set the Baud Rate Counter 2 value
  96          * Baud rate (standard) = fi2cclk / ( (BRCNT2 x 2) + Foncycle )
  97          * Foncycle = 0 (no digital filtering)
  98          */
  99         value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2));
 100         i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2,
 101                         U8500_I2C_BRCR_SHIFT_BRCNT2, value);
 102
 103         /* ensure that BRCNT value is zero */
 104         i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1,
 105                         U8500_I2C_BRCR_SHIFT_BRCNT1, 0);
 106
 107         return U8500_I2C_INPUT_FREQ/(value * 2);
 108 }
 109
 110 /*
 111  * i2c_init - initialize the i2c bus
 112  *
 113  *      speed: bus speed (in HZ)
 114  *      slaveaddr: address of device in slave mode
 115  *
 116  *      Slave mode is not implemented.
 117  */
 118 void i2c_init(int speed, int slaveaddr)
 119 {
 120         struct u8500_i2c_regs *i2c_regs;
 121
 122         debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
 123
 124         u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
 125                            i2c_clock_bits[i2c_bus_num].pcken,
 126                            i2c_clock_bits[i2c_bus_num].kcken);
 127
 128         i2c_regs = i2c_dev[i2c_bus_num];
 129
 130         /* Disable the controller */
 131         i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
 132
 133         /* Clear registers */
 134         writel(0, &i2c_regs->cr);
 135         writel(0, &i2c_regs->scr);
 136         writel(0, &i2c_regs->hsmcr);
 137         writel(0, &i2c_regs->tftr);
 138         writel(0, &i2c_regs->rftr);
 139         writel(0, &i2c_regs->dmar);
 140
 141         i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
 142
 143         /*
 144          * Set our own address.
 145          * Set slave address mode to 7 bit addressing mode
 146          */
 147         i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM);
 148         i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR,
 149                         U8500_I2C_SCR_SHIFT_ADDR, slaveaddr);
 150         /* Slave Data Set up Time */
 151         i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME,
 152                         U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
 153
 154         /* Disable the DMA sync logic */
 155         i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE,
 156                         U8500_I2C_CR_SHIFT_DMA_SLE, 0);
 157
 158         /* Disable interrupts */
 159         writel(0, &i2c_regs->imscr);
 160
 161         /* Configure bus master mode */
 162         i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM,
 163                         U8500_I2C_BUS_MASTER_MODE);
 164         /* Set FIFO threshold values */
 165         writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
 166         writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
 167
 168         /* Enable the I2C Controller */
 169         i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
 170
 171         bus_initialized[i2c_bus_num] = 1;
 172 }
 173
 174
 175 /*
 176  * loop_till_bit_clear - polls on a bit till it clears
 177  * ioreg: register where you want to check status
 178  * mask: bit mask for the bit you wish to check
 179  * timeout: timeout in ticks/s
 180  */
 181 static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout)
 182 {
 183         unsigned long timebase = get_timer(0);
 184
 185         do {
 186                 if ((readl(io_reg) & mask) == 0x0UL)
 187                         return 0;
 188         } while (get_timer(timebase) < timeout);
 189
 190         debug("loop_till_bit_clear timed out\n");
 191         return -1;
 192 }
 193
 194 /*
 195  * loop_till_bit_set - polls on a bit till it is set.
 196  * ioreg: register where you want to check status
 197  * mask: bit mask for the bit you wish to check
 198  * timeout: timeout in ticks/s
 199  */
 200 static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout)
 201 {
 202         unsigned long timebase = get_timer(0);
 203
 204         do {
 205                 if ((readl(io_reg) & mask) != 0x0UL)
 206                         return 0;
 207         } while (get_timer(timebase) < timeout);
 208
 209         debug("loop_till_bit_set timed out\n");
 210         return -1;
 211 }
 212
 213 /*
 214  * flush_fifo - flush the I2C TX and RX FIFOs
 215  */
 216 static void flush_fifo(struct u8500_i2c_regs *i2c_regs)
 217 {
 218         int counter = U8500_I2C_FIFO_FLUSH_COUNTER;
 219
 220         /* Flush Tx FIFO */
 221         i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX);
 222         /* Flush Rx FIFO */
 223         i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX);
 224         while (counter--) {
 225                 if (!(readl(&i2c_regs->cr) &
 226                                 (U8500_I2C_CR_FTX | U8500_I2C_CR_FRX)))
 227                         break;
 228         }
 229         return;
 230 }
 231
 232 #ifdef DEBUG
 233 static void print_abort_reason(struct u8500_i2c_regs *i2c_regs)
 234 {
 235         int cause;
 236
 237         printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr);
 238         cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >>
 239                                 U8500_I2C_SR_SHIFT_CAUSE;
 240         switch (cause) {
 241         case U8500_I2C_NACK_ADDR:
 242                 printf("No Ack received after Slave Address xmission\n");
 243                 break;
 244         case U8500_I2C_NACK_DATA:
 245                 printf("Valid for MASTER_WRITE: No Ack received "
 246                                 "during data phase\n");
 247                 break;
 248         case U8500_I2C_ACK_MCODE:
 249                 printf("Master recv ack after xmission of master code"
 250                                 "in hs mode\n");
 251                 break;
 252         case U8500_I2C_ARB_LOST:
 253                 printf("Master Lost arbitration\n");
 254                 break;
 255         case U8500_I2C_BERR_START:
 256                 printf("Slave restarts\n");
 257                 break;
 258         case U8500_I2C_BERR_STOP:
 259                 printf("Slave reset\n");
 260                 break;
 261         case U8500_I2C_OVFL:
 262                 printf("Overflow\n");
 263                 break;
 264         default:
 265                 printf("Unknown error type\n");
 266         }
 267 }
 268 #endif
 269
 270 /*
 271  * i2c_abort - called when a I2C transaction failed
 272  */
 273 static void i2c_abort(struct u8500_i2c_regs *i2c_regs)
 274 {
 275 #ifdef DEBUG
 276         print_abort_reason(i2c_regs);
 277 #endif
 278         /* flush RX and TX fifos */
 279         flush_fifo(i2c_regs);
 280
 281         /* Acknowledge the Master Transaction Done */
 282         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
 283
 284         /* Acknowledge the Master Transaction Done Without Stop */
 285         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
 286
 287         i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
 288 }
 289
 290 /*
 291  * write addr, alias index, to I2C bus.
 292  */
 293 static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen)
 294 {
 295         while (alen--) {
 296                 /* Wait until the Tx Fifo is not full */
 297                 if (loop_till_bit_clear((void *)&i2c_regs->risr,
 298                                         U8500_I2C_INT_TXFF,
 299                                         U8500_I2C_ENDAD_COUNTER)) {
 300                         i2c_abort(i2c_regs);
 301                         return -1;
 302                 }
 303
 304                 /* MSB first */
 305                 writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr);
 306         }
 307
 308         return 0;
 309 }
 310
 311 /*
 312  * Internal simplified read function:
 313  *   i2c_regs:  Pointer to I2C registers for current bus
 314  *   chip:      I2C chip address, range 0..127
 315  *   addr:      Memory (register) address within the chip
 316  *   alen:      Number of bytes to use for addr (typically 1, 2 for larger
 317  *              memories, 0 for register type devices with only one register)
 318  *   value:     Where to put the data
 319  *
 320  *   Returns:   0 on success, not 0 on failure
 321  */
 322 static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip,
 323                 uint addr, int alen, uchar *value)
 324 {
 325         u32   mcr = 0;
 326
 327         /* Set the address mode to 7 bit */
 328         WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
 329
 330         /* Store the slave address in the master control register */
 331         WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
 332
 333         if (alen != 0) {
 334                 /* Master write operation */
 335                 mcr &= ~(U8500_I2C_MCR_OP);
 336
 337                 /* Configure the Frame length to one byte */
 338                 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH,
 339                                 U8500_I2C_MCR_SHIFT_LENGTH, 1);
 340
 341                 /* Repeated start, no stop */
 342                 mcr &= ~(U8500_I2C_MCR_STOP);
 343
 344                 /* Write Master Control Register */
 345                 writel(mcr, &i2c_regs->mcr);
 346
 347                 /* send addr/index */
 348                 if (i2c_write_addr(i2c_regs, addr, alen) != 0)
 349                         return -1;
 350
 351                 /* Check for the Master Transaction Done Without Stop */
 352                 if (loop_till_bit_set((void *)&i2c_regs->risr,
 353                                         U8500_I2C_INT_MTDWS,
 354                                         U8500_I2C_ENDAD_COUNTER)) {
 355                         return -1;
 356                 }
 357
 358                 /* Acknowledge the Master Transaction Done Without Stop */
 359                 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
 360         }
 361
 362         /* Master control configuration for read operation  */
 363         mcr |= U8500_I2C_MCR_OP;
 364
 365         /* Configure the STOP condition, we read only one byte */
 366         mcr |= U8500_I2C_MCR_STOP;
 367
 368         /* Set the frame length to one byte, we support only 1 byte reads */
 369         WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
 370
 371         i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP,
 372                         U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
 373
 374         /*
 375          * receive_data_polling
 376          */
 377
 378         /* Wait until the Rx FIFO is not empty */
 379         if (loop_till_bit_clear((void *)&i2c_regs->risr,
 380                                         U8500_I2C_INT_RXFE,
 381                                         U8500_I2C_ENDAD_COUNTER))
 382                 return -1;
 383
 384         /* Read the data byte from Rx FIFO */
 385         *value = readb(&i2c_regs->rfr);
 386
 387         /* Wait until the work is done */
 388         if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD,
 389                                 U8500_I2C_ENDAD_COUNTER))
 390                 return -1;
 391
 392         /* Acknowledge the Master Transaction Done */
 393         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
 394
 395         /* If MTD is set, Master Transaction Done Without Stop is set too */
 396         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
 397
 398         return 0;
 399 }
 400
 401 /*
 402  * Internal simplified write function:
 403  *   i2c_regs:  Pointer to I2C registers for current bus
 404  *   chip:      I2C chip address, range 0..127
 405  *   addr:      Memory (register) address within the chip
 406  *   alen:      Number of bytes to use for addr (typically 1, 2 for larger
 407  *              memories, 0 for register type devices with only one register)
 408  *   data:      Where to read the data
 409  *   len:       How many bytes to write
 410  *
 411  *   Returns:   0 on success, not 0 on failure
 412  */
 413 static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr,
 414                 int alen, u8 *data, int len)
 415 {
 416         int i;
 417         u32 mcr = 0;
 418
 419         /* Set the address mode to 7 bit */
 420         WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
 421
 422         /* Store the slave address in the master control register */
 423         WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
 424
 425         /* Write operation */
 426         mcr &= ~(U8500_I2C_MCR_OP);
 427
 428         /* Current transaction is terminated by STOP condition */
 429         mcr |= U8500_I2C_MCR_STOP;
 430
 431         /* Frame length: addr byte + len */
 432         WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH,
 433                         (alen + len));
 434
 435         /* Write MCR register */
 436         writel(mcr, &i2c_regs->mcr);
 437
 438         if (i2c_write_addr(i2c_regs, addr, alen) != 0)
 439                 return -1;
 440
 441         for (i = 0; i < len; i++) {
 442                 /* Wait until the Tx FIFO is not full */
 443                 if (loop_till_bit_clear((void *)&i2c_regs->risr,
 444                                         U8500_I2C_INT_TXFF,
 445                                         U8500_I2C_ENDAD_COUNTER))
 446                         return -1;
 447
 448                 /* it is a 32 bit register with upper 24 reserved R/O */
 449                 writeb(data[i], &i2c_regs->tfr);
 450         }
 451
 452         /* Check for Master Transaction Done */
 453         if (loop_till_bit_set((void *)&i2c_regs->risr,
 454                                         U8500_I2C_INT_MTD,
 455                                         U8500_I2C_ENDAD_COUNTER)) {
 456                 printf("i2c_write_byte error2: risr %08x\n",
 457                                 i2c_regs->risr);
 458                 return -1;
 459         }
 460
 461         /* Acknowledge Master Transaction Done */
 462         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
 463
 464         /* Acknowledge Master Transaction Done Without Stop */
 465         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
 466
 467         return 0;
 468 }
 469
 470 /*
 471  * Probe the given I2C chip address. Returns 0 if a chip responded,
 472  * not 0 on failure.
 473  */
 474 int i2c_probe(uchar chip)
 475 {
 476         u32 mcr = 0;
 477         struct u8500_i2c_regs *i2c_regs;
 478
 479         if (chip == CONFIG_SYS_I2C_SLAVE)
 480                 return 1;
 481
 482         i2c_regs = i2c_dev[i2c_bus_num];
 483
 484         /* Set the address mode to 7 bit */
 485         WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
 486
 487         /* Store the slave address in the master control register */
 488         WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip);
 489
 490         /* Read operation */
 491         mcr |= U8500_I2C_MCR_OP;
 492
 493         /* Set the frame length to one byte */
 494         WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
 495
 496         /* Current transaction is terminated by STOP condition */
 497         mcr |= U8500_I2C_MCR_STOP;
 498
 499         /* Write MCR register */
 500         writel(mcr, &i2c_regs->mcr);
 501
 502         /* Wait until the Rx Fifo is not empty */
 503         if (loop_till_bit_clear((void *)&i2c_regs->risr,
 504                                         U8500_I2C_INT_RXFE,
 505                                         U8500_I2C_ENDAD_COUNTER)) {
 506                 i2c_abort(i2c_regs);
 507                 return -1;
 508         }
 509
 510         flush_fifo(i2c_regs);
 511
 512         /* Acknowledge the Master Transaction Done */
 513         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
 514
 515         /* Acknowledge the Master Transaction Done Without Stop */
 516         i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
 517
 518         return 0;
 519 }
 520
 521 /*
 522  * Read/Write interface:
 523  *   chip:    I2C chip address, range 0..127
 524  *   addr:    Memory (register) address within the chip
 525  *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
 526  *              memories, 0 for register type devices with only one
 527  *              register)
 528  *   buffer:  Where to read/write the data
 529  *   len:     How many bytes to read/write
 530  *
 531  *   Returns: 0 on success, not 0 on failure
 532  */
 533 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 534 {
 535         int i;
 536         int rc;
 537         struct u8500_i2c_regs *i2c_regs;
 538
 539         if (alen > 2) {
 540                 debug("I2C read: addr len %d not supported\n", alen);
 541                 return 1;
 542         }
 543
 544         i2c_regs = i2c_dev[i2c_bus_num];
 545
 546         for (i = 0; i < len; i++) {
 547                 rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]);
 548                 if (rc != 0) {
 549                         debug("I2C read: I/O error: %d\n", rc);
 550                         i2c_abort(i2c_regs);
 551                         return rc;
 552                 }
 553         }
 554
 555         return 0;
 556 }
 557
 558 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 559 {
 560         int rc;
 561         struct u8500_i2c_regs *i2c_regs;
 562         i2c_regs = i2c_dev[i2c_bus_num];
 563
 564         rc = __i2c_write(i2c_regs, chip, addr, alen, buffer,
 565                         len);
 566         if (rc != 0) {
 567                 debug("I2C write: I/O error\n");
 568                 i2c_abort(i2c_regs);
 569                 return rc;
 570         }
 571         return 0;
 572 }
 573
 574 int i2c_set_bus_num(unsigned int bus)
 575 {
 576         if (bus > ARRAY_SIZE(i2c_dev) - 1) {
 577                 debug("i2c_set_bus_num: only up to bus %d supported\n",
 578                                 ARRAY_SIZE(i2c_dev)-1);
 579                 return -1;
 580         }
 581
 582         i2c_bus_num = bus;
 583
 584         if (!bus_initialized[i2c_bus_num])
 585                 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 586
 587         return 0;
 588 }
 589
 590 int i2c_set_bus_speed(unsigned int speed)
 591 {
 592
 593         if (speed > U8500_I2C_MAX_STANDARD_SCL) {
 594                 debug("i2c_set_bus_speed: only up to %d supported\n",
 595                                 U8500_I2C_MAX_STANDARD_SCL);
 596                 return -1;
 597         }
 598
 599         /* sets as side effect i2c_bus_speed[i2c_bus_num] */
 600         i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
 601
 602         return 0;
 603 }
 604
 605 unsigned int i2c_get_bus_num(void)
 606 {
 607         return i2c_bus_num;
 608 }
 609
 610 unsigned int i2c_get_bus_speed(void)
 611 {
 612         return i2c_bus_speed[i2c_bus_num];
 613 }