drivers/mmc/sdhci.c

   1 /*
   2  * Copyright 2011, Marvell Semiconductor Inc.
   3  * Lei Wen <leiwen@marvell.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * Back ported to the 8xx platform (from the 8260 platform) by
   8  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <mmc.h>
  14 #include <sdhci.h>
  15
  16 void *aligned_buffer;
  17
  18 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  19 {
  20         unsigned long timeout;
  21
  22         /* Wait max 100 ms */
  23         timeout = 100;
  24         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  25         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  26                 if (timeout == 0) {
  27                         printf("Reset 0x%x never completed.\n", (int)mask);
  28                         return;
  29                 }
  30                 timeout--;
  31                 udelay(1000);
  32         }
  33 }
  34
  35 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  36 {
  37         int i;
  38         if (cmd->resp_type & MMC_RSP_136) {
  39                 /* CRC is stripped so we need to do some shifting. */
  40                 for (i = 0; i < 4; i++) {
  41                         cmd->response[i] = sdhci_readl(host,
  42                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  43                         if (i != 3)
  44                                 cmd->response[i] |= sdhci_readb(host,
  45                                                 SDHCI_RESPONSE + (3-i)*4-1);
  46                 }
  47         } else {
  48                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  49         }
  50 }
  51
  52 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  53 {
  54         int i;
  55         char *offs;
  56         for (i = 0; i < data->blocksize; i += 4) {
  57                 offs = data->dest + i;
  58                 if (data->flags == MMC_DATA_READ)
  59                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  60                 else
  61                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  62         }
  63 }
  64
  65 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  66                                 unsigned int start_addr)
  67 {
  68         unsigned int stat, rdy, mask, timeout, block = 0;
  69 #ifdef CONFIG_MMC_SDMA
  70         unsigned char ctrl;
  71         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  72         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  73         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  74 #endif
  75
  76         timeout = 1000000;
  77         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  78         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  79         do {
  80                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
  81                 if (stat & SDHCI_INT_ERROR) {
  82                         printf("Error detected in status(0x%X)!\n", stat);
  83                         return -1;
  84                 }
  85                 if (stat & rdy) {
  86                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  87                                 continue;
  88                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  89                         sdhci_transfer_pio(host, data);
  90                         data->dest += data->blocksize;
  91                         if (++block >= data->blocks)
  92                                 break;
  93                 }
  94 #ifdef CONFIG_MMC_SDMA
  95                 if (stat & SDHCI_INT_DMA_END) {
  96                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
  97                         start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
  98                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
  99                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 100                 }
 101 #endif
 102                 if (timeout-- > 0)
 103                         udelay(10);
 104                 else {
 105                         printf("Transfer data timeout\n");
 106                         return -1;
 107                 }
 108         } while (!(stat & SDHCI_INT_DATA_END));
 109         return 0;
 110 }
 111
 112 /*
 113  * No command will be sent by driver if card is busy, so driver must wait
 114  * for card ready state.
 115  * Every time when card is busy after timeout then (last) timeout value will be
 116  * increased twice but only if it doesn't exceed global defined maximum.
 117  * Each function call will use last timeout value. Max timeout can be redefined
 118  * in board config file.
 119  */
 120 #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
 121 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT            3200
 122 #endif
 123 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT        100
 124
 125 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 126                        struct mmc_data *data)
 127 {
 128         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 129         unsigned int stat = 0;
 130         int ret = 0;
 131         int trans_bytes = 0, is_aligned = 1;
 132         u32 mask, flags, mode;
 133         unsigned int time = 0, start_addr = 0;
 134         unsigned int retry = 10000;
 135         int mmc_dev = mmc->block_dev.dev;
 136
 137         /* Timeout unit - ms */
 138         static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
 139
 140         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 141         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 142
 143         /* We shouldn't wait for data inihibit for stop commands, even
 144            though they might use busy signaling */
 145         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 146                 mask &= ~SDHCI_DATA_INHIBIT;
 147
 148         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 149                 if (time >= cmd_timeout) {
 150                         printf("MMC: %d busy ", mmc_dev);
 151                         if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
 152                                 cmd_timeout += cmd_timeout;
 153                                 printf("timeout increasing to: %u ms.\n",
 154                                        cmd_timeout);
 155                         } else {
 156                                 puts("timeout.\n");
 157                                 return COMM_ERR;
 158                         }
 159                 }
 160                 time++;
 161                 udelay(1000);
 162         }
 163
 164         mask = SDHCI_INT_RESPONSE;
 165         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 166                 flags = SDHCI_CMD_RESP_NONE;
 167         else if (cmd->resp_type & MMC_RSP_136)
 168                 flags = SDHCI_CMD_RESP_LONG;
 169         else if (cmd->resp_type & MMC_RSP_BUSY) {
 170                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 171                 mask |= SDHCI_INT_DATA_END;
 172         } else
 173                 flags = SDHCI_CMD_RESP_SHORT;
 174
 175         if (cmd->resp_type & MMC_RSP_CRC)
 176                 flags |= SDHCI_CMD_CRC;
 177         if (cmd->resp_type & MMC_RSP_OPCODE)
 178                 flags |= SDHCI_CMD_INDEX;
 179         if (data)
 180                 flags |= SDHCI_CMD_DATA;
 181
 182         /*Set Transfer mode regarding to data flag*/
 183         if (data != 0) {
 184                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 185                 mode = SDHCI_TRNS_BLK_CNT_EN;
 186                 trans_bytes = data->blocks * data->blocksize;
 187                 if (data->blocks > 1)
 188                         mode |= SDHCI_TRNS_MULTI;
 189
 190                 if (data->flags == MMC_DATA_READ)
 191                         mode |= SDHCI_TRNS_READ;
 192
 193 #ifdef CONFIG_MMC_SDMA
 194                 if (data->flags == MMC_DATA_READ)
 195                         start_addr = (unsigned int)data->dest;
 196                 else
 197                         start_addr = (unsigned int)data->src;
 198                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 199                                 (start_addr & 0x7) != 0x0) {
 200                         is_aligned = 0;
 201                         start_addr = (unsigned int)aligned_buffer;
 202                         if (data->flags != MMC_DATA_READ)
 203                                 memcpy(aligned_buffer, data->src, trans_bytes);
 204                 }
 205
 206                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 207                 mode |= SDHCI_TRNS_DMA;
 208 #endif
 209                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 210                                 data->blocksize),
 211                                 SDHCI_BLOCK_SIZE);
 212                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 213                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 214         }
 215
 216         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 217 #ifdef CONFIG_MMC_SDMA
 218         flush_cache(start_addr, trans_bytes);
 219 #endif
 220         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 221         do {
 222                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 223                 if (stat & SDHCI_INT_ERROR)
 224                         break;
 225                 if (--retry == 0)
 226                         break;
 227         } while ((stat & mask) != mask);
 228
 229         if (retry == 0) {
 230                 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
 231                         return 0;
 232                 else {
 233                         printf("Timeout for status update!\n");
 234                         return TIMEOUT;
 235                 }
 236         }
 237
 238         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 239                 sdhci_cmd_done(host, cmd);
 240                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 241         } else
 242                 ret = -1;
 243
 244         if (!ret && data)
 245                 ret = sdhci_transfer_data(host, data, start_addr);
 246
 247         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 248                 udelay(1000);
 249
 250         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 251         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 252         if (!ret) {
 253                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 254                                 !is_aligned && (data->flags == MMC_DATA_READ))
 255                         memcpy(data->dest, aligned_buffer, trans_bytes);
 256                 return 0;
 257         }
 258
 259         sdhci_reset(host, SDHCI_RESET_CMD);
 260         sdhci_reset(host, SDHCI_RESET_DATA);
 261         if (stat & SDHCI_INT_TIMEOUT)
 262                 return TIMEOUT;
 263         else
 264                 return COMM_ERR;
 265 }
 266
 267 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 268 {
 269         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 270         unsigned int div, clk, timeout;
 271
 272         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 273
 274         if (clock == 0)
 275                 return 0;
 276
 277         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 278                 /* Version 3.00 divisors must be a multiple of 2. */
 279                 if (mmc->f_max <= clock)
 280                         div = 1;
 281                 else {
 282                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
 283                                 if ((mmc->f_max / div) <= clock)
 284                                         break;
 285                         }
 286                 }
 287         } else {
 288                 /* Version 2.00 divisors must be a power of 2. */
 289                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 290                         if ((mmc->f_max / div) <= clock)
 291                                 break;
 292                 }
 293         }
 294         div >>= 1;
 295
 296         if (host->set_clock)
 297                 host->set_clock(host->index, div);
 298
 299         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 300         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 301                 << SDHCI_DIVIDER_HI_SHIFT;
 302         clk |= SDHCI_CLOCK_INT_EN;
 303         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 304
 305         /* Wait max 20 ms */
 306         timeout = 20;
 307         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 308                 & SDHCI_CLOCK_INT_STABLE)) {
 309                 if (timeout == 0) {
 310                         printf("Internal clock never stabilised.\n");
 311                         return -1;
 312                 }
 313                 timeout--;
 314                 udelay(1000);
 315         }
 316
 317         clk |= SDHCI_CLOCK_CARD_EN;
 318         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 319         return 0;
 320 }
 321
 322 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 323 {
 324         u8 pwr = 0;
 325
 326         if (power != (unsigned short)-1) {
 327                 switch (1 << power) {
 328                 case MMC_VDD_165_195:
 329                         pwr = SDHCI_POWER_180;
 330                         break;
 331                 case MMC_VDD_29_30:
 332                 case MMC_VDD_30_31:
 333                         pwr = SDHCI_POWER_300;
 334                         break;
 335                 case MMC_VDD_32_33:
 336                 case MMC_VDD_33_34:
 337                         pwr = SDHCI_POWER_330;
 338                         break;
 339                 }
 340         }
 341
 342         if (pwr == 0) {
 343                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 344                 return;
 345         }
 346
 347         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
 348                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 349
 350         pwr |= SDHCI_POWER_ON;
 351
 352         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 353 }
 354
 355 void sdhci_set_ios(struct mmc *mmc)
 356 {
 357         u32 ctrl;
 358         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 359
 360         if (host->set_control_reg)
 361                 host->set_control_reg(host);
 362
 363         if (mmc->clock != host->clock)
 364                 sdhci_set_clock(mmc, mmc->clock);
 365
 366         /* Set bus width */
 367         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 368         if (mmc->bus_width == 8) {
 369                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 370                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 371                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 372                         ctrl |= SDHCI_CTRL_8BITBUS;
 373         } else {
 374                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 375                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 376                 if (mmc->bus_width == 4)
 377                         ctrl |= SDHCI_CTRL_4BITBUS;
 378                 else
 379                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 380         }
 381
 382         if (mmc->clock > 26000000)
 383                 ctrl |= SDHCI_CTRL_HISPD;
 384         else
 385                 ctrl &= ~SDHCI_CTRL_HISPD;
 386
 387         if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
 388                 ctrl &= ~SDHCI_CTRL_HISPD;
 389
 390         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 391 }
 392
 393 int sdhci_init(struct mmc *mmc)
 394 {
 395         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 396
 397         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 398                 aligned_buffer = memalign(8, 512*1024);
 399                 if (!aligned_buffer) {
 400                         printf("Aligned buffer alloc failed!!!");
 401                         return -1;
 402                 }
 403         }
 404
 405         sdhci_set_power(host, fls(mmc->voltages) - 1);
 406
 407         if (host->quirks & SDHCI_QUIRK_NO_CD) {
 408                 unsigned int status;
 409
 410                 sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
 411                         SDHCI_HOST_CONTROL);
 412
 413                 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
 414                 while ((!(status & SDHCI_CARD_PRESENT)) ||
 415                     (!(status & SDHCI_CARD_STATE_STABLE)) ||
 416                     (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
 417                         status = sdhci_readl(host, SDHCI_PRESENT_STATE);
 418         }
 419
 420         /* Enable only interrupts served by the SD controller */
 421         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK
 422                      , SDHCI_INT_ENABLE);
 423         /* Mask all sdhci interrupt sources */
 424         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 425
 426         return 0;
 427 }
 428
 429 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 430 {
 431         struct mmc *mmc;
 432         unsigned int caps;
 433
 434         mmc = malloc(sizeof(struct mmc));
 435         if (!mmc) {
 436                 printf("mmc malloc fail!\n");
 437                 return -1;
 438         }
 439
 440         mmc->priv = host;
 441         host->mmc = mmc;
 442
 443         sprintf(mmc->name, "%s", host->name);
 444         mmc->send_cmd = sdhci_send_command;
 445         mmc->set_ios = sdhci_set_ios;
 446         mmc->init = sdhci_init;
 447         mmc->getcd = NULL;
 448         mmc->getwp = NULL;
 449
 450         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 451 #ifdef CONFIG_MMC_SDMA
 452         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 453                 printf("Your controller don't support sdma!!\n");
 454                 return -1;
 455         }
 456 #endif
 457
 458         if (max_clk)
 459                 mmc->f_max = max_clk;
 460         else {
 461                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 462                         mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
 463                                 >> SDHCI_CLOCK_BASE_SHIFT;
 464                 else
 465                         mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
 466                                 >> SDHCI_CLOCK_BASE_SHIFT;
 467                 mmc->f_max *= 1000000;
 468         }
 469         if (mmc->f_max == 0) {
 470                 printf("Hardware doesn't specify base clock frequency\n");
 471                 return -1;
 472         }
 473         if (min_clk)
 474                 mmc->f_min = min_clk;
 475         else {
 476                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 477                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
 478                 else
 479                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
 480         }
 481
 482         mmc->voltages = 0;
 483         if (caps & SDHCI_CAN_VDD_330)
 484                 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 485         if (caps & SDHCI_CAN_VDD_300)
 486                 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 487         if (caps & SDHCI_CAN_VDD_180)
 488                 mmc->voltages |= MMC_VDD_165_195;
 489
 490         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 491                 mmc->voltages |= host->voltages;
 492
 493         mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 494         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 495                 if (caps & SDHCI_CAN_DO_8BIT)
 496                         mmc->host_caps |= MMC_MODE_8BIT;
 497         }
 498         if (host->host_caps)
 499                 mmc->host_caps |= host->host_caps;
 500
 501         sdhci_reset(host, SDHCI_RESET_ALL);
 502         mmc_register(mmc);
 503
 504         return 0;
 505 }