2 * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on ti81xx_nand.c
4 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
5 * Mansoor Ahamed <mansoor.ahamed@ti.com>
7 * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/mem.h>
33 #include <asm/arch/nand.h>
34 #include <linux/mtd/nand_ecc.h>
37 struct nand_bch_priv {
47 /* BCH nibbles for diff bch levels */
48 #define ECC_BCH4_NIBBLES 13
49 #define ECC_BCH8_NIBBLES 26
50 #define ECC_BCH16_NIBBLES 52
53 #ifndef CONFIG_SPL_BUILD
54 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT_KERNEL;
55 static struct nand_ecclayout hw_bch4_nand_oob = GPMC_NAND_HW_BCH4_ECC_LAYOUT;
56 static struct nand_ecclayout hw_bch16_nand_oob = GPMC_NAND_HW_BCH16_ECC_LAYOUT;
58 static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
60 static struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
62 static struct nand_bch_priv bch_priv = {
64 .nibbles = ECC_BCH8_NIBBLES,
67 #ifndef CONFIG_SYS_NAND_NO_OOB
68 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
69 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
71 static struct nand_bbt_descr bbt_main_descr = {
72 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
73 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
78 .pattern = bbt_pattern,
81 static struct nand_bbt_descr bbt_mirror_descr = {
82 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
83 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
88 .pattern = mirror_pattern,
93 * am33xx_read_bch8_result - Read BCH result for BCH8 level
95 * @mtd: MTD device structure
96 * @big_endian: When set read register 3 first
97 * @ecc_code: Read syndrome from BCH result registers
99 static void am33xx_read_bch8_result(struct mtd_info *mtd, int big_endian,
107 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
109 ecc_code[i++] = res & 0xFF;
110 for (j = 0; j < 3; j++) {
111 u32 res = readl(--ptr);
113 ecc_code[i++] = (res >> 24) & 0xFF;
114 ecc_code[i++] = (res >> 16) & 0xFF;
115 ecc_code[i++] = (res >> 8) & 0xFF;
116 ecc_code[i++] = res & 0xFF;
119 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
120 for (j = 0; j < 3; j++) {
121 u32 res = readl(ptr++);
123 ecc_code[i++] = res & 0xFF;
124 ecc_code[i++] = (res >> 8) & 0xFF;
125 ecc_code[i++] = (res >> 16) & 0xFF;
126 ecc_code[i++] = (res >> 24) & 0xFF;
128 ecc_code[i++] = readl(ptr) & 0xFF;
134 * am33xx_ecc_disable - Disable H/W ECC calculation
136 * @mtd: MTD device structure
139 static void am33xx_ecc_disable(struct mtd_info *mtd)
141 writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
142 &gpmc_cfg->ecc_config);
146 * am33xx_nand_hwcontrol - Set the address pointers correctly for the
147 * following address/data/command operation
149 static void am33xx_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
152 register struct nand_chip *this = mtd->priv;
154 debug("nand cmd %08x ctrl %08x\n", cmd, ctrl);
156 * Point the IO_ADDR to DATA and ADDRESS registers instead
160 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
161 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
163 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
164 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
166 case NAND_CTRL_CHANGE | NAND_NCE:
167 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
170 if (cmd != NAND_CMD_NONE)
171 writeb(cmd, this->IO_ADDR_W);
175 * am33xx_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
177 * @mtd: MTD device structure
178 * @mode: Read/Write mode
180 static void am33xx_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
182 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
183 uint32_t unused_length = 0;
184 struct nand_bch_priv *bch = chip->priv;
186 switch (bch->nibbles) {
187 case ECC_BCH4_NIBBLES:
190 case ECC_BCH8_NIBBLES:
193 case ECC_BCH16_NIBBLES:
197 /* Clear the ecc result registers, select ecc reg as 1 */
198 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
202 /* eccsize1 config */
203 val = ((unused_length + bch->nibbles) << 22);
208 /* by default eccsize0 selected for ecc1resultsize */
209 /* eccsize0 config */
210 val = (bch->nibbles << 12);
211 /* eccsize1 config */
212 val |= (unused_length << 22);
214 /* ecc size configuration */
215 writel(val, &gpmc_cfg->ecc_size_config);
216 /* by default 512bytes sector page is selected */
219 /* bch4 / bch8 / bch16 */
220 val |= (bch->type << 12);
221 /* set wrap mode to 1 */
223 val |= (dev_width << 7);
226 /* val |= (1); */ /* should not enable ECC just init i.e. config */
227 writel(val, &gpmc_cfg->ecc_config);
230 #ifndef CONFIG_SPL_BUILD
232 * am33xx_hwecc_init - Initialize the Hardware ECC for NAND flash in
234 * @mtd: MTD device structure
237 static void am33xx_hwecc_init(struct nand_chip *chip)
240 * Init ECC Control Register
241 * Clear all ECC | Enable Reg1
243 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
244 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
248 * gen_true_ecc - This function will generate true ECC value, which
249 * can be used when correcting data read from NAND flash memory core
251 * @ecc_buf: buffer to store ecc code
253 * @return: re-formatted ECC value
255 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
257 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
258 ((ecc_buf[2] & 0x0F) << 8);
263 * am33xx_rotate_ecc_bch - Rotate the syndrome bytes
265 * @mtd: MTD device structure
266 * @calc_ecc: ECC read from ECC registers
267 * @syndrome: Rotated syndrome will be retuned in this array
270 static inline void am33xx_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
273 struct nand_chip *chip = mtd->priv;
274 struct nand_bch_priv *bch = chip->priv;
292 for (i = 0, j = (n_bytes - 1); i < n_bytes; i++, j--)
293 syndrome[i] = calc_ecc[j];
299 * am33xx_fix_errors_bch - Correct bch error in the data
301 * @mtd: MTD device structure
302 * @data: Data read from flash
303 * @error_count:Number of errors in data
304 * @error_loc: Locations of errors in the data
307 static void am33xx_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
308 uint32_t error_count, uint32_t *error_loc)
310 struct nand_chip *chip = mtd->priv;
311 struct nand_bch_priv *bch = chip->priv;
313 uint32_t error_byte_pos;
314 uint32_t error_bit_mask;
315 uint32_t last_bit = (bch->nibbles * 4) - 1;
317 /* Flip all bits as specified by the error location array. */
318 /* FOR( each found error location flip the bit ) */
319 for (count = 0; count < error_count; count++) {
320 if (error_loc[count] > last_bit) {
321 /* Remove the ECC spare bits from correction. */
322 error_loc[count] -= (last_bit + 1);
323 /* Offset bit in data region */
324 error_byte_pos = ((512 * 8) - (error_loc[count]) - 1) / 8;
326 error_bit_mask = 0x1 << (error_loc[count] % 8);
327 /* Toggle the error bit to make the correction. */
328 data[error_byte_pos] ^= error_bit_mask;
334 * am33xx_correct_data_bch - Compares the ecc read from nand spare area
335 * with ECC registers values and corrects one bit error if it has occured
337 * @mtd: MTD device structure
339 * @read_ecc: ecc read from nand flash (ignored)
340 * @calc_ecc: ecc read from ECC registers
342 * @return 0 if data is OK or corrected, else returns -1
344 static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
345 uint8_t *buf, int page);
347 static int am33xx_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
348 uint8_t *read_ecc, uint8_t *calc_ecc)
350 struct nand_chip *chip = mtd->priv;
351 struct nand_bch_priv *bch = chip->priv;
352 uint8_t syndrome[28];
353 uint32_t error_count = 0;
354 uint32_t error_loc[8];
355 uint32_t i, ecc_flag;
358 for (i = 0; i < (chip->ecc.bytes - 1); i++)
359 if (read_ecc[i] != 0xff)
366 elm_config(bch->type);
368 /* while reading ECC result we read it in big endian.
369 * Hence while loading to ELM we have rotate to get the right endian.
371 am33xx_rotate_ecc_bch(mtd, calc_ecc, syndrome);
373 /* use elm module to check for errors */
374 if (elm_check_error(syndrome, bch->nibbles, &error_count, error_loc) != 0) {
375 printf("uncorrectable ECC error\n");
379 /* correct bch error */
380 if (error_count > 0) {
381 am33xx_fix_errors_bch(mtd, dat, error_count, error_loc);
387 #ifndef CONFIG_SPL_BUILD
389 * am33xx_correct_data - Compares the ecc read from nand spare area with ECC
390 * registers values and corrects one bit error if it has occured
391 * Further details can be had from Am33xx TRM and the following selected links:
392 * http://en.wikipedia.org/wiki/Hamming_code
393 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
395 * @mtd: MTD device structure
397 * @read_ecc: ecc read from nand flash
398 * @calc_ecc: ecc read from ECC registers
400 * @return 0 if data is OK or corrected, else returns -1
402 static int am33xx_correct_data(struct mtd_info *mtd, uint8_t *dat,
403 uint8_t *read_ecc, uint8_t *calc_ecc)
405 uint32_t orig_ecc, new_ecc, res, hm;
406 uint16_t parity_bits, byte;
409 /* Regenerate the orginal ECC */
410 orig_ecc = gen_true_ecc(read_ecc);
411 new_ecc = gen_true_ecc(calc_ecc);
412 /* Get the XOR of real ecc */
413 res = orig_ecc ^ new_ecc;
415 /* Get the hamming width */
417 /* Single bit errors can be corrected! */
419 /* Correctable data! */
420 parity_bits = res >> 16;
421 bit = (parity_bits & 0x7);
422 byte = (parity_bits >> 3) & 0x1FF;
423 /* Flip the bit to correct */
424 dat[byte] ^= (0x1 << bit);
425 } else if (hm == 1) {
426 printf("am33xx_nand: Error: Corrupted ECC\n");
427 /* ECC itself is corrupted */
431 * hm distance != parity pairs OR one, could mean 2 bit
432 * error OR potentially be on a blank page..
433 * orig_ecc: contains spare area data from nand flash.
434 * new_ecc: generated ecc while reading data area.
435 * Note: if the ecc = 0, all data bits from which it was
436 * generated are 0xFF.
437 * The 3 byte(24 bits) ecc is generated per 512byte
438 * chunk of a page. If orig_ecc(from spare area)
439 * is 0xFF && new_ecc(computed now from data area)=0x0,
440 * this means that data area is 0xFF and spare area is
441 * 0xFF. A sure sign of an erased page!
443 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
445 printf("am33xx_nand: Error: Multibit error detected; hm=%d\n",
447 /* detected 2 bit error */
456 * am33xx_calculate_ecc_bch - Read BCH ECC result
458 * @mtd: MTD structure
460 * @ecc_code: ecc_code buffer
462 static int am33xx_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
465 struct nand_chip *chip = mtd->priv;
466 struct nand_bch_priv *bch = chip->priv;
470 if (bch->type == ECC_BCH8)
471 am33xx_read_bch8_result(mtd, big_endian, ecc_code);
472 else /* BCH4 and BCH16 currently not supported */
476 * Stop reading anymore ECC vals and clear old results
477 * enable will be called if more reads are required
479 am33xx_ecc_disable(mtd);
484 #ifndef CONFIG_SPL_BUILD
486 * am33xx_calculate_ecc - Generate non-inverted ECC bytes.
488 * Using noninverted ECC can be considered ugly since writing a blank
489 * page ie. padding will clear the ECC bytes. This is no problem as
490 * long nobody is trying to write data on the seemingly unused page.
491 * Reading an erased page will produce an ECC mismatch between
492 * generated and read ECC bytes that has to be dealt with separately.
493 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
494 * is used, the result of read will be 0x0 while the ECC offsets of the
495 * spare area will be 0xFF which will result in an ECC mismatch.
496 * @mtd: MTD structure
498 * @ecc_code: ecc_code buffer
500 static int am33xx_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
505 /* Start Reading from HW ECC1_Result = 0x200 */
506 val = readl(&gpmc_cfg->ecc1_result);
508 ecc_code[0] = val & 0xFF;
509 ecc_code[1] = (val >> 16) & 0xFF;
510 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
513 * Stop reading anymore ECC vals and clear old results
514 * enable will be called if more reads are required
516 writel(0x000, &gpmc_cfg->ecc_config);
522 #ifdef CONFIG_SPL_BUILD
523 static void am33xx_spl_nand_command(struct mtd_info *mtd, unsigned int cmd,
526 struct nand_chip *chip = mtd->priv;
528 while (!chip->dev_ready(mtd))
531 /* Emulate NAND_CMD_READOOB */
532 if (cmd == NAND_CMD_READOOB) {
533 col += CONFIG_SYS_NAND_PAGE_SIZE;
534 cmd = NAND_CMD_READ0;
537 /* Shift the offset from byte addressing to word addressing. */
538 if (chip->options & NAND_BUSWIDTH_16)
541 /* Begin command latch cycle */
542 chip->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
543 /* Set ALE and clear CLE to start address cycle */
545 chip->cmd_ctrl(mtd, col & 0xff,
546 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
547 chip->cmd_ctrl(mtd, (col >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
549 chip->cmd_ctrl(mtd, page & 0xff, NAND_CTRL_ALE); /* A[19:12] */
550 chip->cmd_ctrl(mtd, (page >> 8) & 0xff,
551 NAND_CTRL_ALE); /* A[27:20] */
552 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
553 /* One more address cycle for devices > 128MiB */
554 chip->cmd_ctrl(mtd, (page >> 16) & 0x0f,
555 NAND_CTRL_ALE); /* A[31:28] */
557 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
559 /* Latch in address */
560 chip->cmd_ctrl(mtd, cmd == NAND_CMD_RNDOUT ?
561 NAND_CMD_RNDOUTSTART : NAND_CMD_READSTART,
562 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
563 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
566 * Wait a while for the data to be ready
568 while (!chip->dev_ready(mtd))
574 * am33xx_read_page_bch - hardware ecc based page read function
575 * @mtd: mtd info structure
576 * @chip: nand chip info structure
577 * @buf: buffer to store read data
578 * @page: page number to read
581 static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
582 uint8_t *buf, int page)
585 int i, eccsize = chip->ecc.size;
586 int eccbytes = chip->ecc.bytes;
587 int eccsteps = chip->ecc.steps;
589 uint8_t *ecc_calc = chip->buffers->ecccalc;
590 uint8_t *ecc_code = chip->buffers->ecccode;
591 uint32_t *eccpos = chip->ecc.layout->eccpos;
592 uint8_t *oob = chip->oob_poi;
593 uint32_t data_pos = 0;
594 uint32_t oob_pos = (eccsize * eccsteps) + eccpos[0];
596 chip->cmdfunc(mtd, NAND_CMD_READ0, data_pos, page);
598 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
600 chip->ecc.hwctl(mtd, NAND_ECC_READ);
602 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
603 chip->read_buf(mtd, p, eccsize);
604 /* read respective ecc from oob area */
605 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
606 chip->read_buf(mtd, oob, eccbytes);
608 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
614 for (i = 0; i < chip->ecc.total; i++) {
615 ecc_code[i] = chip->oob_poi[i];
618 eccsteps = chip->ecc.steps;
621 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
624 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
626 printf("am33xx_nand: uncorrectable ECC error in page %5d\n",
628 mtd->ecc_stats.failed++;
631 mtd->ecc_stats.corrected += stat;
632 printf("%s: corrected ECC errors: %d\n", __func__, stat);
640 * am33xx_enable_ecc_bch- This function enables the bch h/w ecc functionality
641 * @mtd: MTD device structure
642 * @mode: Read/Write mode
645 static void am33xx_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
647 struct nand_chip *chip = mtd->priv;
649 am33xx_hwecc_init_bch(chip, mode);
651 writel(readl(&gpmc_cfg->ecc_config) | 0x1, &gpmc_cfg->ecc_config);
654 #ifndef CONFIG_SPL_BUILD
656 * am33xx_enable_ecc - This function enables the hardware ecc functionality
657 * @mtd: MTD device structure
658 * @mode: Read/Write mode
660 static void am33xx_enable_ecc(struct mtd_info *mtd, int32_t mode)
662 struct nand_chip *chip = mtd->priv;
663 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
668 /* Clear the ecc result registers, select ecc reg as 1 */
669 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
672 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
673 * tell all regs to generate size0 sized regs
674 * we just have a single ECC engine for all CS
676 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
677 &gpmc_cfg->ecc_size_config);
678 val = (dev_width << 7) | (cs << 1) | (1 << 0);
679 writel(val, &gpmc_cfg->ecc_config);
682 printf("Error: Unrecognized Mode[%d]!\n", mode);
687 * __am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
688 * (i.e. hamming / bch) and s/w ecc.
689 * The default is to come up on s/w ecc
691 * @nand: NAND chip datastructure
692 * @hardware: NAND_ECC_HW -switch to h/w ecc
693 * NAND_ECC_SOFT -switch to s/w ecc
695 * @mode: 0 - hamming code
700 static void __am33xx_nand_switch_ecc(struct nand_chip *nand,
701 nand_ecc_modes_t hardware, int32_t mode)
703 struct nand_bch_priv *bch;
707 /* Reset ecc interface */
708 nand->ecc.read_page = NULL;
709 nand->ecc.write_page = NULL;
710 nand->ecc.read_oob = NULL;
711 nand->ecc.write_oob = NULL;
712 nand->ecc.hwctl = NULL;
713 nand->ecc.correct = NULL;
714 nand->ecc.calculate = NULL;
716 nand->ecc.mode = hardware;
717 /* Setup the ecc configurations again */
718 if (hardware == NAND_ECC_HW) {
720 /* -1 for converting mode to bch type */
721 bch->type = mode - 1;
726 nand->ecc.layout = &hw_bch4_nand_oob;
727 bch->nibbles = ECC_BCH4_NIBBLES;
728 debug("4 not supported\n");
732 nand->ecc.bytes = 26;
733 nand->ecc.layout = &hw_bch16_nand_oob;
734 bch->nibbles = ECC_BCH16_NIBBLES;
735 debug("16 not supported\n");
740 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
741 nand->ecc.layout = &hw_bch8_nand_oob;
742 bch->nibbles = ECC_BCH8_NIBBLES;
743 debug("8 Selected\n");
745 nand->ecc.mode = NAND_ECC_HW;
746 nand->ecc.size = 512;
747 nand->ecc.read_page = am33xx_read_page_bch;
748 nand->ecc.hwctl = am33xx_enable_ecc_bch;
749 nand->ecc.correct = am33xx_correct_data_bch;
750 nand->ecc.calculate = am33xx_calculate_ecc_bch;
751 am33xx_hwecc_init_bch(nand, NAND_ECC_READ);
753 nand->ecc.layout = &hw_nand_oob;
754 nand->ecc.size = 512;
756 nand->ecc.hwctl = am33xx_enable_ecc;
757 nand->ecc.correct = am33xx_correct_data;
758 nand->ecc.calculate = am33xx_calculate_ecc;
759 am33xx_hwecc_init(nand);
760 debug("HW ECC Hamming Code selected\n");
762 } else if (hardware == NAND_ECC_SOFT) {
763 /* Use mtd default settings */
764 nand->ecc.layout = NULL;
765 debug("SW ECC selected\n");
767 debug("ECC Disabled\n");
772 * am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
773 * (i.e. hamming / bch) and s/w ecc.
774 * The default is to come up on s/w ecc
776 * @hardware - NAND_ECC_HW -switch to h/w ecc
777 * NAND_ECC_SOFT -switch to s/w ecc
779 * @mode - 0 - hamming code
784 void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode)
786 struct nand_chip *nand;
787 struct mtd_info *mtd;
789 if (nand_curr_device < 0 ||
790 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
791 printf("Error: Can't switch ecc, no devices available\n");
795 mtd = &nand_info[nand_curr_device];
798 __am33xx_nand_switch_ecc(nand, hardware, mode);
800 nand->options |= NAND_OWN_BUFFERS;
801 /* Update NAND handling after ECC mode switch */
803 nand->options &= ~NAND_OWN_BUFFERS;
806 #else /* CONFIG_SPL_BUILD */
807 /* Check wait pin as dev ready indicator */
808 static int am33xx_spl_dev_ready(struct mtd_info *mtd)
812 // printf("dev status: ");
813 ret = readl(&gpmc_cfg->status) & (1 << 8);
814 // printf("%d %08x\n", ret, gpmc_cfg->status);
820 * Board-specific NAND initialization. The following members of the
821 * argument are board-specific:
822 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
823 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
824 * - cmd_ctrl: hardwarespecific function for accesing control-lines
825 * - waitfunc: hardwarespecific function for accesing device ready/busy line
826 * - ecc.hwctl: function to enable (reset) hardware ecc generator
827 * - ecc.mode: mode of ecc, see defines
828 * - chip_delay: chip dependent delay for transfering data from array to
830 * - options: various chip options. They can partly be set to inform
831 * nand_scan about special functionality. See the defines for further
834 int board_nand_init(struct nand_chip *nand)
836 /* int32_t gpmc_config = 0; */
840 * xloader/Uboot's gpmc configuration would have configured GPMC for
841 * nand type of memory. The following logic scans and latches on to the
842 * first CS with NAND type memory.
843 * TBD: need to make this logic generic to handle multiple CS NAND
846 while (cs < GPMC_MAX_CS) {
847 /* Check if NAND type is set */
848 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
850 debug("Searching for NAND device @ GPMC CS:%d\n", cs);
855 if (cs >= GPMC_MAX_CS) {
856 printf("NAND: Unable to find NAND settings in "
857 "GPMC Configuration - quitting\n");
861 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
862 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
864 nand->cmd_ctrl = am33xx_nand_hwcontrol;
865 nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
866 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
867 #ifdef CONFIG_SYS_NAND_NO_OOB
868 nand->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB;
870 nand->options |= NAND_USE_FLASH_BBT;
871 nand->bbt_td = &bbt_main_descr;
872 nand->bbt_md = &bbt_mirror_descr;
873 #endif /* CONFIG_SYS_NAND_NO_OOB */
874 #endif /* CONFIG_SYS_NAND_USE_FLASH_BBT */
876 /* If we are 16 bit dev, our gpmc config tells us that */
877 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) {
878 nand->options |= NAND_BUSWIDTH_16;
881 nand->chip_delay = 100;
883 /* required in case of BCH */
886 /* BCH info that will be correct for SPL or overridden otherwise. */
887 nand->priv = &bch_priv;
889 bch_priv.nibbles = ECC_BCH8_NIBBLES;
890 bch_priv.type = ECC_BCH8;
891 nand->ecc.mode = NAND_ECC_HW;
892 nand->ecc.layout = &hw_bch8_nand_oob;
893 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
894 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
895 nand->ecc.hwctl = am33xx_enable_ecc_bch;
896 nand->ecc.read_page = am33xx_read_page_bch;
897 nand->ecc.correct = am33xx_correct_data_bch;
898 nand->ecc.calculate = am33xx_calculate_ecc_bch;
900 #ifndef CONFIG_SPL_BUILD
901 nand_curr_device = 0;
903 nand->cmdfunc = am33xx_spl_nand_command;
905 nand->ecc.steps = CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE;
906 nand->ecc.total = CONFIG_SYS_NAND_ECCBYTES * nand->ecc.steps;
908 if (nand->options & NAND_BUSWIDTH_16)
909 nand->read_buf = nand_read_buf16;
911 nand->read_buf = nand_read_buf;
913 nand->dev_ready = am33xx_spl_dev_ready;
914 #endif /* CONFIG_SPL_BUILD */
915 am33xx_hwecc_init_bch(nand, NAND_ECC_READ);