drivers/mtd/nand/atmel_nand.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   7  *
   8  * Add Programmable Multibit ECC support for various AT91 SoC
   9  *     (C) Copyright 2012 ATMEL, Hong Xu
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/gpio.h>
  17
  18 #include <malloc.h>
  19 #include <nand.h>
  20 #include <watchdog.h>
  21 #include <linux/mtd/nand_ecc.h>
  22
  23 #ifdef CONFIG_ATMEL_NAND_HWECC
  24
  25 /* Register access macros */
  26 #define ecc_readl(add, reg)                             \
  27         readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  28 #define ecc_writel(add, reg, value)                     \
  29         writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  30
  31 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  32
  33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  34
  35 #ifdef CONFIG_SPL_BUILD
  36 #undef CONFIG_SYS_NAND_ONFI_DETECTION
  37 #endif
  38
  39 struct atmel_nand_host {
  40         struct pmecc_regs __iomem *pmecc;
  41         struct pmecc_errloc_regs __iomem *pmerrloc;
  42         void __iomem            *pmecc_rom_base;
  43
  44         u8              pmecc_corr_cap;
  45         u16             pmecc_sector_size;
  46         u32             pmecc_index_table_offset;
  47
  48         int             pmecc_bytes_per_sector;
  49         int             pmecc_sector_number;
  50         int             pmecc_degree;   /* Degree of remainders */
  51         int             pmecc_cw_len;   /* Length of codeword */
  52
  53         /* lookup table for alpha_to and index_of */
  54         void __iomem    *pmecc_alpha_to;
  55         void __iomem    *pmecc_index_of;
  56
  57         /* data for pmecc computation */
  58         int16_t *pmecc_smu;
  59         int16_t *pmecc_partial_syn;
  60         int16_t *pmecc_si;
  61         int16_t *pmecc_lmu; /* polynomal order */
  62         int     *pmecc_mu;
  63         int     *pmecc_dmu;
  64         int     *pmecc_delta;
  65 };
  66
  67 static struct atmel_nand_host pmecc_host;
  68 static struct nand_ecclayout atmel_pmecc_oobinfo;
  69
  70 /*
  71  * Return number of ecc bytes per sector according to sector size and
  72  * correction capability
  73  *
  74  * Following table shows what at91 PMECC supported:
  75  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  76  * =====================        ================        =================
  77  *                2-bits                 4-bytes                  4-bytes
  78  *                4-bits                 7-bytes                  7-bytes
  79  *                8-bits                13-bytes                 14-bytes
  80  *               12-bits                20-bytes                 21-bytes
  81  *               24-bits                39-bytes                 42-bytes
  82  */
  83 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  84 {
  85         int m = 12 + sector_size / 512;
  86         return (m * cap + 7) / 8;
  87 }
  88
  89 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  90         int oobsize, int ecc_len)
  91 {
  92         int i;
  93
  94         layout->eccbytes = ecc_len;
  95
  96         /* ECC will occupy the last ecc_len bytes continuously */
  97         for (i = 0; i < ecc_len; i++)
  98                 layout->eccpos[i] = oobsize - ecc_len + i;
  99
 100         layout->oobfree[0].offset = 2;
 101         layout->oobfree[0].length =
 102                 oobsize - ecc_len - layout->oobfree[0].offset;
 103 }
 104
 105 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 106 {
 107         int table_size;
 108
 109         table_size = host->pmecc_sector_size == 512 ?
 110                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 111
 112         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 113         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 114                         table_size * sizeof(int16_t);
 115 }
 116
 117 static void pmecc_data_free(struct atmel_nand_host *host)
 118 {
 119         free(host->pmecc_partial_syn);
 120         free(host->pmecc_si);
 121         free(host->pmecc_lmu);
 122         free(host->pmecc_smu);
 123         free(host->pmecc_mu);
 124         free(host->pmecc_dmu);
 125         free(host->pmecc_delta);
 126 }
 127
 128 static int pmecc_data_alloc(struct atmel_nand_host *host)
 129 {
 130         const int cap = host->pmecc_corr_cap;
 131         int size;
 132
 133         size = (2 * cap + 1) * sizeof(int16_t);
 134         host->pmecc_partial_syn = malloc(size);
 135         host->pmecc_si = malloc(size);
 136         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 137         host->pmecc_smu = malloc((cap + 2) * size);
 138
 139         size = (cap + 1) * sizeof(int);
 140         host->pmecc_mu = malloc(size);
 141         host->pmecc_dmu = malloc(size);
 142         host->pmecc_delta = malloc(size);
 143
 144         if (host->pmecc_partial_syn &&
 145                         host->pmecc_si &&
 146                         host->pmecc_lmu &&
 147                         host->pmecc_smu &&
 148                         host->pmecc_mu &&
 149                         host->pmecc_dmu &&
 150                         host->pmecc_delta)
 151                 return 0;
 152
 153         /* error happened */
 154         pmecc_data_free(host);
 155         return -ENOMEM;
 156
 157 }
 158
 159 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 160 {
 161         struct nand_chip *nand_chip = mtd->priv;
 162         struct atmel_nand_host *host = nand_chip->priv;
 163         int i;
 164         uint32_t value;
 165
 166         /* Fill odd syndromes */
 167         for (i = 0; i < host->pmecc_corr_cap; i++) {
 168                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 169                 if (i & 1)
 170                         value >>= 16;
 171                 value &= 0xffff;
 172                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 173         }
 174 }
 175
 176 static void pmecc_substitute(struct mtd_info *mtd)
 177 {
 178         struct nand_chip *nand_chip = mtd->priv;
 179         struct atmel_nand_host *host = nand_chip->priv;
 180         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 181         int16_t __iomem *index_of = host->pmecc_index_of;
 182         int16_t *partial_syn = host->pmecc_partial_syn;
 183         const int cap = host->pmecc_corr_cap;
 184         int16_t *si;
 185         int i, j;
 186
 187         /* si[] is a table that holds the current syndrome value,
 188          * an element of that table belongs to the field
 189          */
 190         si = host->pmecc_si;
 191
 192         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 193
 194         /* Computation 2t syndromes based on S(x) */
 195         /* Odd syndromes */
 196         for (i = 1; i < 2 * cap; i += 2) {
 197                 for (j = 0; j < host->pmecc_degree; j++) {
 198                         if (partial_syn[i] & (0x1 << j))
 199                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 200                 }
 201         }
 202         /* Even syndrome = (Odd syndrome) ** 2 */
 203         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 204                 if (si[j] == 0) {
 205                         si[i] = 0;
 206                 } else {
 207                         int16_t tmp;
 208
 209                         tmp = readw(index_of + si[j]);
 210                         tmp = (tmp * 2) % host->pmecc_cw_len;
 211                         si[i] = readw(alpha_to + tmp);
 212                 }
 213         }
 214 }
 215
 216 /*
 217  * This function defines a Berlekamp iterative procedure for
 218  * finding the value of the error location polynomial.
 219  * The input is si[], initialize by pmecc_substitute().
 220  * The output is smu[][].
 221  *
 222  * This function is written according to chip datasheet Chapter:
 223  * Find the Error Location Polynomial Sigma(x) of Section:
 224  * Programmable Multibit ECC Control (PMECC).
 225  */
 226 static void pmecc_get_sigma(struct mtd_info *mtd)
 227 {
 228         struct nand_chip *nand_chip = mtd->priv;
 229         struct atmel_nand_host *host = nand_chip->priv;
 230
 231         int16_t *lmu = host->pmecc_lmu;
 232         int16_t *si = host->pmecc_si;
 233         int *mu = host->pmecc_mu;
 234         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 235         int *delta = host->pmecc_delta; /* Delta order */
 236         int cw_len = host->pmecc_cw_len;
 237         const int16_t cap = host->pmecc_corr_cap;
 238         const int num = 2 * cap + 1;
 239         int16_t __iomem *index_of = host->pmecc_index_of;
 240         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 241         int i, j, k;
 242         uint32_t dmu_0_count, tmp;
 243         int16_t *smu = host->pmecc_smu;
 244
 245         /* index of largest delta */
 246         int ro;
 247         int largest;
 248         int diff;
 249
 250         /* Init the Sigma(x) */
 251         memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
 252
 253         dmu_0_count = 0;
 254
 255         /* First Row */
 256
 257         /* Mu */
 258         mu[0] = -1;
 259
 260         smu[0] = 1;
 261
 262         /* discrepancy set to 1 */
 263         dmu[0] = 1;
 264         /* polynom order set to 0 */
 265         lmu[0] = 0;
 266         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 267         delta[0] = -1;
 268
 269         /* Second Row */
 270
 271         /* Mu */
 272         mu[1] = 0;
 273         /* Sigma(x) set to 1 */
 274         smu[num] = 1;
 275
 276         /* discrepancy set to S1 */
 277         dmu[1] = si[1];
 278
 279         /* polynom order set to 0 */
 280         lmu[1] = 0;
 281
 282         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 283         delta[1] = 0;
 284
 285         for (i = 1; i <= cap; i++) {
 286                 mu[i + 1] = i << 1;
 287                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 288                 /* check if discrepancy is set to 0 */
 289                 if (dmu[i] == 0) {
 290                         dmu_0_count++;
 291
 292                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 293                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 294                                 tmp += 2;
 295                         else
 296                                 tmp += 1;
 297
 298                         if (dmu_0_count == tmp) {
 299                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 300                                         smu[(cap + 1) * num + j] =
 301                                                         smu[i * num + j];
 302
 303                                 lmu[cap + 1] = lmu[i];
 304                                 return;
 305                         }
 306
 307                         /* copy polynom */
 308                         for (j = 0; j <= lmu[i] >> 1; j++)
 309                                 smu[(i + 1) * num + j] = smu[i * num + j];
 310
 311                         /* copy previous polynom order to the next */
 312                         lmu[i + 1] = lmu[i];
 313                 } else {
 314                         ro = 0;
 315                         largest = -1;
 316                         /* find largest delta with dmu != 0 */
 317                         for (j = 0; j < i; j++) {
 318                                 if ((dmu[j]) && (delta[j] > largest)) {
 319                                         largest = delta[j];
 320                                         ro = j;
 321                                 }
 322                         }
 323
 324                         /* compute difference */
 325                         diff = (mu[i] - mu[ro]);
 326
 327                         /* Compute degree of the new smu polynomial */
 328                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 329                                 lmu[i + 1] = lmu[i];
 330                         else
 331                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 332
 333                         /* Init smu[i+1] with 0 */
 334                         for (k = 0; k < num; k++)
 335                                 smu[(i + 1) * num + k] = 0;
 336
 337                         /* Compute smu[i+1] */
 338                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 339                                 int16_t a, b, c;
 340
 341                                 if (!(smu[ro * num + k] && dmu[i]))
 342                                         continue;
 343                                 a = readw(index_of + dmu[i]);
 344                                 b = readw(index_of + dmu[ro]);
 345                                 c = readw(index_of + smu[ro * num + k]);
 346                                 tmp = a + (cw_len - b) + c;
 347                                 a = readw(alpha_to + tmp % cw_len);
 348                                 smu[(i + 1) * num + (k + diff)] = a;
 349                         }
 350
 351                         for (k = 0; k <= lmu[i] >> 1; k++)
 352                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 353                 }
 354
 355                 /* End Computing Sigma (Mu+1) and L(mu) */
 356                 /* In either case compute delta */
 357                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 358
 359                 /* Do not compute discrepancy for the last iteration */
 360                 if (i >= cap)
 361                         continue;
 362
 363                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 364                         tmp = 2 * (i - 1);
 365                         if (k == 0) {
 366                                 dmu[i + 1] = si[tmp + 3];
 367                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 368                                 int16_t a, b, c;
 369                                 a = readw(index_of +
 370                                                 smu[(i + 1) * num + k]);
 371                                 b = si[2 * (i - 1) + 3 - k];
 372                                 c = readw(index_of + b);
 373                                 tmp = a + c;
 374                                 tmp %= cw_len;
 375                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 376                                         dmu[i + 1];
 377                         }
 378                 }
 379         }
 380 }
 381
 382 static int pmecc_err_location(struct mtd_info *mtd)
 383 {
 384         struct nand_chip *nand_chip = mtd->priv;
 385         struct atmel_nand_host *host = nand_chip->priv;
 386         const int cap = host->pmecc_corr_cap;
 387         const int num = 2 * cap + 1;
 388         int sector_size = host->pmecc_sector_size;
 389         int err_nbr = 0;        /* number of error */
 390         int roots_nbr;          /* number of roots */
 391         int i;
 392         uint32_t val;
 393         int16_t *smu = host->pmecc_smu;
 394         int timeout = PMECC_MAX_TIMEOUT_US;
 395
 396         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 397
 398         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 399                 pmecc_writel(host->pmerrloc, sigma[i],
 400                              smu[(cap + 1) * num + i]);
 401                 err_nbr++;
 402         }
 403
 404         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 405         if (sector_size == 1024)
 406                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 407
 408         pmecc_writel(host->pmerrloc, elcfg, val);
 409         pmecc_writel(host->pmerrloc, elen,
 410                      sector_size * 8 + host->pmecc_degree * cap);
 411
 412         while (--timeout) {
 413                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 414                         break;
 415                 WATCHDOG_RESET();
 416                 udelay(1);
 417         }
 418
 419         if (!timeout) {
 420                 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
 421                 return -1;
 422         }
 423
 424         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 425                         >> 8;
 426         /* Number of roots == degree of smu hence <= cap */
 427         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 428                 return err_nbr - 1;
 429
 430         /* Number of roots does not match the degree of smu
 431          * unable to correct error */
 432         return -1;
 433 }
 434
 435 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 436                 int sector_num, int extra_bytes, int err_nbr)
 437 {
 438         struct nand_chip *nand_chip = mtd->priv;
 439         struct atmel_nand_host *host = nand_chip->priv;
 440         int i = 0;
 441         int byte_pos, bit_pos, sector_size, pos;
 442         uint32_t tmp;
 443         uint8_t err_byte;
 444
 445         sector_size = host->pmecc_sector_size;
 446
 447         while (err_nbr) {
 448                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 449                 byte_pos = tmp / 8;
 450                 bit_pos  = tmp % 8;
 451
 452                 if (byte_pos >= (sector_size + extra_bytes))
 453                         BUG();  /* should never happen */
 454
 455                 if (byte_pos < sector_size) {
 456                         err_byte = *(buf + byte_pos);
 457                         *(buf + byte_pos) ^= (1 << bit_pos);
 458
 459                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 460                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 461                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 462                 } else {
 463                         /* Bit flip in OOB area */
 464                         tmp = sector_num * host->pmecc_bytes_per_sector
 465                                         + (byte_pos - sector_size);
 466                         err_byte = ecc[tmp];
 467                         ecc[tmp] ^= (1 << bit_pos);
 468
 469                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 470                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 471                                 pos, bit_pos, err_byte, ecc[tmp]);
 472                 }
 473
 474                 i++;
 475                 err_nbr--;
 476         }
 477
 478         return;
 479 }
 480
 481 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 482         u8 *ecc)
 483 {
 484         struct nand_chip *nand_chip = mtd->priv;
 485         struct atmel_nand_host *host = nand_chip->priv;
 486         int i, err_nbr, eccbytes;
 487         uint8_t *buf_pos;
 488
 489         eccbytes = nand_chip->ecc.bytes;
 490         for (i = 0; i < eccbytes; i++)
 491                 if (ecc[i] != 0xff)
 492                         goto normal_check;
 493         /* Erased page, return OK */
 494         return 0;
 495
 496 normal_check:
 497         for (i = 0; i < host->pmecc_sector_number; i++) {
 498                 err_nbr = 0;
 499                 if (pmecc_stat & 0x1) {
 500                         buf_pos = buf + i * host->pmecc_sector_size;
 501
 502                         pmecc_gen_syndrome(mtd, i);
 503                         pmecc_substitute(mtd);
 504                         pmecc_get_sigma(mtd);
 505
 506                         err_nbr = pmecc_err_location(mtd);
 507                         if (err_nbr == -1) {
 508                                 dev_err(host->dev, "PMECC: Too many errors\n");
 509                                 mtd->ecc_stats.failed++;
 510                                 return -EIO;
 511                         } else {
 512                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 513                                         host->pmecc_bytes_per_sector, err_nbr);
 514                                 mtd->ecc_stats.corrected += err_nbr;
 515                         }
 516                 }
 517                 pmecc_stat >>= 1;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 524         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 525 {
 526         struct atmel_nand_host *host = chip->priv;
 527         int eccsize = chip->ecc.size;
 528         uint8_t *oob = chip->oob_poi;
 529         uint32_t *eccpos = chip->ecc.layout->eccpos;
 530         uint32_t stat;
 531         int timeout = PMECC_MAX_TIMEOUT_US;
 532
 533         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 534         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 535         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 536                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 537
 538         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 539         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 540
 541         chip->read_buf(mtd, buf, eccsize);
 542         chip->read_buf(mtd, oob, mtd->oobsize);
 543
 544         while (--timeout) {
 545                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 546                         break;
 547                 WATCHDOG_RESET();
 548                 udelay(1);
 549         }
 550
 551         if (!timeout) {
 552                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
 553                 return -1;
 554         }
 555
 556         stat = pmecc_readl(host->pmecc, isr);
 557         if (stat != 0)
 558                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 559                         return -EIO;
 560
 561         return 0;
 562 }
 563
 564 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 565                 struct nand_chip *chip, const uint8_t *buf,
 566                 int oob_required)
 567 {
 568         struct atmel_nand_host *host = chip->priv;
 569         uint32_t *eccpos = chip->ecc.layout->eccpos;
 570         int i, j;
 571         int timeout = PMECC_MAX_TIMEOUT_US;
 572
 573         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 574         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 575
 576         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 577                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 578
 579         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 580         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 581
 582         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 583
 584         while (--timeout) {
 585                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 586                         break;
 587                 WATCHDOG_RESET();
 588                 udelay(1);
 589         }
 590
 591         if (!timeout) {
 592                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 593                 goto out;
 594         }
 595
 596         for (i = 0; i < host->pmecc_sector_number; i++) {
 597                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 598                         int pos;
 599
 600                         pos = i * host->pmecc_bytes_per_sector + j;
 601                         chip->oob_poi[eccpos[pos]] =
 602                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 603                 }
 604         }
 605         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 606 out:
 607         return 0;
 608 }
 609
 610 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 611 {
 612         struct nand_chip *nand_chip = mtd->priv;
 613         struct atmel_nand_host *host = nand_chip->priv;
 614         uint32_t val = 0;
 615         struct nand_ecclayout *ecc_layout;
 616
 617         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 618         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 619
 620         switch (host->pmecc_corr_cap) {
 621         case 2:
 622                 val = PMECC_CFG_BCH_ERR2;
 623                 break;
 624         case 4:
 625                 val = PMECC_CFG_BCH_ERR4;
 626                 break;
 627         case 8:
 628                 val = PMECC_CFG_BCH_ERR8;
 629                 break;
 630         case 12:
 631                 val = PMECC_CFG_BCH_ERR12;
 632                 break;
 633         case 24:
 634                 val = PMECC_CFG_BCH_ERR24;
 635                 break;
 636         }
 637
 638         if (host->pmecc_sector_size == 512)
 639                 val |= PMECC_CFG_SECTOR512;
 640         else if (host->pmecc_sector_size == 1024)
 641                 val |= PMECC_CFG_SECTOR1024;
 642
 643         switch (host->pmecc_sector_number) {
 644         case 1:
 645                 val |= PMECC_CFG_PAGE_1SECTOR;
 646                 break;
 647         case 2:
 648                 val |= PMECC_CFG_PAGE_2SECTORS;
 649                 break;
 650         case 4:
 651                 val |= PMECC_CFG_PAGE_4SECTORS;
 652                 break;
 653         case 8:
 654                 val |= PMECC_CFG_PAGE_8SECTORS;
 655                 break;
 656         }
 657
 658         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 659                 | PMECC_CFG_AUTO_DISABLE);
 660         pmecc_writel(host->pmecc, cfg, val);
 661
 662         ecc_layout = nand_chip->ecc.layout;
 663         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 664         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 665         pmecc_writel(host->pmecc, eaddr,
 666                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 667         /* See datasheet about PMECC Clock Control Register */
 668         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 669         pmecc_writel(host->pmecc, idr, 0xff);
 670         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 671 }
 672
 673 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 674 /*
 675  * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
 676  * @ecc_bits: store the ONFI ECC correct bits capbility
 677  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 678  *
 679  * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
 680  * @sector_size are initialize to 0.
 681  * Return 0 if success to get the ECC requirement.
 682  */
 683 static int get_onfi_ecc_param(struct nand_chip *chip,
 684                 int *ecc_bits, int *sector_size)
 685 {
 686         *ecc_bits = *sector_size = 0;
 687
 688         if (chip->onfi_params.ecc_bits == 0xff)
 689                 /* TODO: the sector_size and ecc_bits need to be find in
 690                  * extended ecc parameter, currently we don't support it.
 691                  */
 692                 return -1;
 693
 694         *ecc_bits = chip->onfi_params.ecc_bits;
 695
 696         /* The default sector size (ecc codeword size) is 512 */
 697         *sector_size = 512;
 698
 699         return 0;
 700 }
 701
 702 /*
 703  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
 704  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
 705  *                    ONFI ECC parameters.
 706  * @host: point to an atmel_nand_host structure.
 707  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
 708  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
 709  * @chip: point to an nand_chip structure.
 710  * @cap: store the ONFI ECC correct bits capbility
 711  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
 712  *
 713  * Return 0 if success. otherwise return the error code.
 714  */
 715 static int pmecc_choose_ecc(struct atmel_nand_host *host,
 716                 struct nand_chip *chip,
 717                 int *cap, int *sector_size)
 718 {
 719         /* Get ECC requirement from ONFI parameters */
 720         *cap = *sector_size = 0;
 721         if (chip->onfi_version) {
 722                 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
 723                         MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
 724                                 *cap, *sector_size);
 725                 } else {
 726                         dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
 727                 }
 728         } else {
 729                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
 730         }
 731         if (*cap == 0 && *sector_size == 0) {
 732                 /* Non-ONFI compliant or use extended ONFI parameters */
 733                 *cap = 2;
 734                 *sector_size = 512;
 735         }
 736
 737         /* If head file doesn't specify then use the one in ONFI parameters */
 738         if (host->pmecc_corr_cap == 0) {
 739                 /* use the most fitable ecc bits (the near bigger one ) */
 740                 if (*cap <= 2)
 741                         host->pmecc_corr_cap = 2;
 742                 else if (*cap <= 4)
 743                         host->pmecc_corr_cap = 4;
 744                 else if (*cap <= 8)
 745                         host->pmecc_corr_cap = 8;
 746                 else if (*cap <= 12)
 747                         host->pmecc_corr_cap = 12;
 748                 else if (*cap <= 24)
 749                         host->pmecc_corr_cap = 24;
 750                 else
 751                         return -EINVAL;
 752         }
 753         if (host->pmecc_sector_size == 0) {
 754                 /* use the most fitable sector size (the near smaller one ) */
 755                 if (*sector_size >= 1024)
 756                         host->pmecc_sector_size = 1024;
 757                 else if (*sector_size >= 512)
 758                         host->pmecc_sector_size = 512;
 759                 else
 760                         return -EINVAL;
 761         }
 762         return 0;
 763 }
 764 #endif
 765
 766 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 767                 struct mtd_info *mtd)
 768 {
 769         struct atmel_nand_host *host;
 770         int cap, sector_size;
 771
 772         host = nand->priv = &pmecc_host;
 773
 774         nand->ecc.mode = NAND_ECC_HW;
 775         nand->ecc.calculate = NULL;
 776         nand->ecc.correct = NULL;
 777         nand->ecc.hwctl = NULL;
 778
 779 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 780         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
 781
 782 #ifdef CONFIG_PMECC_CAP
 783         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 784 #endif
 785 #ifdef CONFIG_PMECC_SECTOR_SIZE
 786         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 787 #endif
 788         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
 789          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
 790          * from ONFI.
 791          */
 792         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
 793                 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
 794                                 cap, sector_size);
 795                 return -EINVAL;
 796         }
 797
 798         if (cap > host->pmecc_corr_cap)
 799                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
 800                                 host->pmecc_corr_cap, cap);
 801         if (sector_size < host->pmecc_sector_size)
 802                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
 803                                 host->pmecc_sector_size, sector_size);
 804 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
 805         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 806         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 807 #endif
 808
 809         cap = host->pmecc_corr_cap;
 810         sector_size = host->pmecc_sector_size;
 811
 812         /* TODO: need check whether cap & sector_size is validate */
 813
 814         if (host->pmecc_sector_size == 512)
 815                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 816         else
 817                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 818
 819         MTDDEBUG(MTD_DEBUG_LEVEL1,
 820                 "Initialize PMECC params, cap: %d, sector: %d\n",
 821                 cap, sector_size);
 822
 823         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 824         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 825                         ATMEL_BASE_PMERRLOC;
 826         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 827
 828         /* ECC is calculated for the whole page (1 step) */
 829         nand->ecc.size = mtd->writesize;
 830
 831         /* set ECC page size and oob layout */
 832         switch (mtd->writesize) {
 833         case 2048:
 834         case 4096:
 835         case 8192:
 836                 host->pmecc_degree = (sector_size == 512) ?
 837                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 838                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 839                 host->pmecc_sector_number = mtd->writesize / sector_size;
 840                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 841                         cap, sector_size);
 842                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 843                 host->pmecc_index_of = host->pmecc_rom_base +
 844                         host->pmecc_index_table_offset;
 845
 846                 nand->ecc.steps = 1;
 847                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 848                                        host->pmecc_sector_number;
 849
 850                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
 851                         dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
 852                                         MTD_MAX_ECCPOS_ENTRIES_LARGE);
 853                         return -EINVAL;
 854                 }
 855
 856                 if (nand->ecc.bytes > mtd->oobsize - 2) {
 857                         dev_err(host->dev, "No room for ECC bytes\n");
 858                         return -EINVAL;
 859                 }
 860                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 861                                         mtd->oobsize,
 862                                         nand->ecc.bytes);
 863                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 864                 break;
 865         case 512:
 866         case 1024:
 867                 /* TODO */
 868                 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
 869         default:
 870                 /* page size not handled by HW ECC */
 871                 /* switching back to soft ECC */
 872                 nand->ecc.mode = NAND_ECC_SOFT;
 873                 nand->ecc.read_page = NULL;
 874                 nand->ecc.postpad = 0;
 875                 nand->ecc.prepad = 0;
 876                 nand->ecc.bytes = 0;
 877                 return 0;
 878         }
 879
 880         /* Allocate data for PMECC computation */
 881         if (pmecc_data_alloc(host)) {
 882                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
 883                 return -ENOMEM;
 884         }
 885
 886         nand->options |= NAND_NO_SUBPAGE_WRITE;
 887         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 888         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 889         nand->ecc.strength = cap;
 890
 891         atmel_pmecc_core_init(mtd);
 892
 893         return 0;
 894 }
 895
 896 #else
 897
 898 /* oob layout for large page size
 899  * bad block info is on bytes 0 and 1
 900  * the bytes have to be consecutives to avoid
 901  * several NAND_CMD_RNDOUT during read
 902  */
 903 static struct nand_ecclayout atmel_oobinfo_large = {
 904         .eccbytes = 4,
 905         .eccpos = {60, 61, 62, 63},
 906         .oobfree = {
 907                 {2, 58}
 908         },
 909 };
 910
 911 /* oob layout for small page size
 912  * bad block info is on bytes 4 and 5
 913  * the bytes have to be consecutives to avoid
 914  * several NAND_CMD_RNDOUT during read
 915  */
 916 static struct nand_ecclayout atmel_oobinfo_small = {
 917         .eccbytes = 4,
 918         .eccpos = {0, 1, 2, 3},
 919         .oobfree = {
 920                 {6, 10}
 921         },
 922 };
 923
 924 /*
 925  * Calculate HW ECC
 926  *
 927  * function called after a write
 928  *
 929  * mtd:        MTD block structure
 930  * dat:        raw data (unused)
 931  * ecc_code:   buffer for ECC
 932  */
 933 static int atmel_nand_calculate(struct mtd_info *mtd,
 934                 const u_char *dat, unsigned char *ecc_code)
 935 {
 936         unsigned int ecc_value;
 937
 938         /* get the first 2 ECC bytes */
 939         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
 940
 941         ecc_code[0] = ecc_value & 0xFF;
 942         ecc_code[1] = (ecc_value >> 8) & 0xFF;
 943
 944         /* get the last 2 ECC bytes */
 945         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
 946
 947         ecc_code[2] = ecc_value & 0xFF;
 948         ecc_code[3] = (ecc_value >> 8) & 0xFF;
 949
 950         return 0;
 951 }
 952
 953 /*
 954  * HW ECC read page function
 955  *
 956  * mtd:        mtd info structure
 957  * chip:       nand chip info structure
 958  * buf:        buffer to store read data
 959  * oob_required:    caller expects OOB data read to chip->oob_poi
 960  */
 961 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 962                                 uint8_t *buf, int oob_required, int page)
 963 {
 964         int eccsize = chip->ecc.size;
 965         int eccbytes = chip->ecc.bytes;
 966         uint32_t *eccpos = chip->ecc.layout->eccpos;
 967         uint8_t *p = buf;
 968         uint8_t *oob = chip->oob_poi;
 969         uint8_t *ecc_pos;
 970         int stat;
 971
 972         /* read the page */
 973         chip->read_buf(mtd, p, eccsize);
 974
 975         /* move to ECC position if needed */
 976         if (eccpos[0] != 0) {
 977                 /* This only works on large pages
 978                  * because the ECC controller waits for
 979                  * NAND_CMD_RNDOUTSTART after the
 980                  * NAND_CMD_RNDOUT.
 981                  * anyway, for small pages, the eccpos[0] == 0
 982                  */
 983                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
 984                                 mtd->writesize + eccpos[0], -1);
 985         }
 986
 987         /* the ECC controller needs to read the ECC just after the data */
 988         ecc_pos = oob + eccpos[0];
 989         chip->read_buf(mtd, ecc_pos, eccbytes);
 990
 991         /* check if there's an error */
 992         stat = chip->ecc.correct(mtd, p, oob, NULL);
 993
 994         if (stat < 0)
 995                 mtd->ecc_stats.failed++;
 996         else
 997                 mtd->ecc_stats.corrected += stat;
 998
 999         /* get back to oob start (end of page) */
1000         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1001
1002         /* read the oob */
1003         chip->read_buf(mtd, oob, mtd->oobsize);
1004
1005         return 0;
1006 }
1007
1008 /*
1009  * HW ECC Correction
1010  *
1011  * function called after a read
1012  *
1013  * mtd:        MTD block structure
1014  * dat:        raw data read from the chip
1015  * read_ecc:   ECC from the chip (unused)
1016  * isnull:     unused
1017  *
1018  * Detect and correct a 1 bit error for a page
1019  */
1020 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1021                 u_char *read_ecc, u_char *isnull)
1022 {
1023         struct nand_chip *nand_chip = mtd->priv;
1024         unsigned int ecc_status;
1025         unsigned int ecc_word, ecc_bit;
1026
1027         /* get the status from the Status Register */
1028         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1029
1030         /* if there's no error */
1031         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1032                 return 0;
1033
1034         /* get error bit offset (4 bits) */
1035         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1036         /* get word address (12 bits) */
1037         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1038         ecc_word >>= 4;
1039
1040         /* if there are multiple errors */
1041         if (ecc_status & ATMEL_ECC_MULERR) {
1042                 /* check if it is a freshly erased block
1043                  * (filled with 0xff) */
1044                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1045                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1046                         /* the block has just been erased, return OK */
1047                         return 0;
1048                 }
1049                 /* it doesn't seems to be a freshly
1050                  * erased block.
1051                  * We can't correct so many errors */
1052                 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1053                                 " Unable to correct.\n");
1054                 return -EIO;
1055         }
1056
1057         /* if there's a single bit error : we can correct it */
1058         if (ecc_status & ATMEL_ECC_ECCERR) {
1059                 /* there's nothing much to do here.
1060                  * the bit error is on the ECC itself.
1061                  */
1062                 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1063                                 " Nothing to correct\n");
1064                 return 0;
1065         }
1066
1067         dev_warn(host->dev, "atmel_nand : one bit error on data."
1068                         " (word offset in the page :"
1069                         " 0x%x bit offset : 0x%x)\n",
1070                         ecc_word, ecc_bit);
1071         /* correct the error */
1072         if (nand_chip->options & NAND_BUSWIDTH_16) {
1073                 /* 16 bits words */
1074                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1075         } else {
1076                 /* 8 bits words */
1077                 dat[ecc_word] ^= (1 << ecc_bit);
1078         }
1079         dev_warn(host->dev, "atmel_nand : error corrected\n");
1080         return 1;
1081 }
1082
1083 /*
1084  * Enable HW ECC : unused on most chips
1085  */
1086 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1087 {
1088 }
1089
1090 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1091 {
1092         nand->ecc.mode = NAND_ECC_HW;
1093         nand->ecc.calculate = atmel_nand_calculate;
1094         nand->ecc.correct = atmel_nand_correct;
1095         nand->ecc.hwctl = atmel_nand_hwctl;
1096         nand->ecc.read_page = atmel_nand_read_page;
1097         nand->ecc.bytes = 4;
1098
1099         if (nand->ecc.mode == NAND_ECC_HW) {
1100                 /* ECC is calculated for the whole page (1 step) */
1101                 nand->ecc.size = mtd->writesize;
1102
1103                 /* set ECC page size and oob layout */
1104                 switch (mtd->writesize) {
1105                 case 512:
1106                         nand->ecc.layout = &atmel_oobinfo_small;
1107                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1108                                         ATMEL_ECC_PAGESIZE_528);
1109                         break;
1110                 case 1024:
1111                         nand->ecc.layout = &atmel_oobinfo_large;
1112                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1113                                         ATMEL_ECC_PAGESIZE_1056);
1114                         break;
1115                 case 2048:
1116                         nand->ecc.layout = &atmel_oobinfo_large;
1117                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1118                                         ATMEL_ECC_PAGESIZE_2112);
1119                         break;
1120                 case 4096:
1121                         nand->ecc.layout = &atmel_oobinfo_large;
1122                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1123                                         ATMEL_ECC_PAGESIZE_4224);
1124                         break;
1125                 default:
1126                         /* page size not handled by HW ECC */
1127                         /* switching back to soft ECC */
1128                         nand->ecc.mode = NAND_ECC_SOFT;
1129                         nand->ecc.calculate = NULL;
1130                         nand->ecc.correct = NULL;
1131                         nand->ecc.hwctl = NULL;
1132                         nand->ecc.read_page = NULL;
1133                         nand->ecc.postpad = 0;
1134                         nand->ecc.prepad = 0;
1135                         nand->ecc.bytes = 0;
1136                         break;
1137                 }
1138         }
1139
1140         return 0;
1141 }
1142
1143 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1144
1145 #endif /* CONFIG_ATMEL_NAND_HWECC */
1146
1147 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1148                                          int cmd, unsigned int ctrl)
1149 {
1150         struct nand_chip *this = mtd->priv;
1151
1152         if (ctrl & NAND_CTRL_CHANGE) {
1153                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1154                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1155                              | CONFIG_SYS_NAND_MASK_CLE);
1156
1157                 if (ctrl & NAND_CLE)
1158                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1159                 if (ctrl & NAND_ALE)
1160                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1161
1162 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1163                 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1164 #endif
1165                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1166         }
1167
1168         if (cmd != NAND_CMD_NONE)
1169                 writeb(cmd, this->IO_ADDR_W);
1170 }
1171
1172 #ifdef CONFIG_SYS_NAND_READY_PIN
1173 static int at91_nand_ready(struct mtd_info *mtd)
1174 {
1175         return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1176 }
1177 #endif
1178
1179 #ifdef CONFIG_SPL_BUILD
1180 /* The following code is for SPL */
1181 static nand_info_t mtd;
1182 static struct nand_chip nand_chip;
1183
1184 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1185 {
1186         struct nand_chip *this = mtd.priv;
1187         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1188         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1189                         unsigned int ctrl) = this->cmd_ctrl;
1190
1191         while (this->dev_ready(&mtd))
1192                 ;
1193
1194         if (cmd == NAND_CMD_READOOB) {
1195                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1196                 cmd = NAND_CMD_READ0;
1197         }
1198
1199         hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1200
1201         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1202                 offs >>= 1;
1203
1204         hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1205         hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1206         hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1207         hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1208 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1209         hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1210 #endif
1211         hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1212
1213         hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1214         hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1215
1216         while (this->dev_ready(&mtd))
1217                 ;
1218
1219         return 0;
1220 }
1221
1222 static int nand_is_bad_block(int block)
1223 {
1224         struct nand_chip *this = mtd.priv;
1225
1226         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1227
1228         if (this->options & NAND_BUSWIDTH_16) {
1229                 if (readw(this->IO_ADDR_R) != 0xffff)
1230                         return 1;
1231         } else {
1232                 if (readb(this->IO_ADDR_R) != 0xff)
1233                         return 1;
1234         }
1235
1236         return 0;
1237 }
1238
1239 #ifdef CONFIG_SPL_NAND_ECC
1240 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1241 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1242                   CONFIG_SYS_NAND_ECCSIZE)
1243 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1244
1245 static int nand_read_page(int block, int page, void *dst)
1246 {
1247         struct nand_chip *this = mtd.priv;
1248         u_char ecc_calc[ECCTOTAL];
1249         u_char ecc_code[ECCTOTAL];
1250         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1251         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1252         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1253         int eccsteps = ECCSTEPS;
1254         int i;
1255         uint8_t *p = dst;
1256         nand_command(block, page, 0, NAND_CMD_READ0);
1257
1258         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1259                 if (this->ecc.mode != NAND_ECC_SOFT)
1260                         this->ecc.hwctl(&mtd, NAND_ECC_READ);
1261                 this->read_buf(&mtd, p, eccsize);
1262                 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
1263         }
1264         this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1265
1266         for (i = 0; i < ECCTOTAL; i++)
1267                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1268
1269         eccsteps = ECCSTEPS;
1270         p = dst;
1271
1272         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1273                 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
1274
1275         return 0;
1276 }
1277 #else
1278 static int nand_read_page(int block, int page, void *dst)
1279 {
1280         struct nand_chip *this = mtd.priv;
1281
1282         nand_command(block, page, 0, NAND_CMD_READ0);
1283         atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
1284
1285         return 0;
1286 }
1287 #endif /* CONFIG_SPL_NAND_ECC */
1288
1289 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1290 {
1291         unsigned int block, lastblock;
1292         unsigned int page;
1293
1294         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
1295         lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
1296         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
1297
1298         while (block <= lastblock) {
1299                 if (!nand_is_bad_block(block)) {
1300                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
1301                                 nand_read_page(block, page, dst);
1302                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
1303                                 page++;
1304                         }
1305
1306                         page = 0;
1307                 } else {
1308                         lastblock++;
1309                 }
1310
1311                 block++;
1312         }
1313
1314         return 0;
1315 }
1316
1317 int at91_nand_wait_ready(struct mtd_info *mtd)
1318 {
1319         struct nand_chip *this = mtd->priv;
1320
1321         udelay(this->chip_delay);
1322
1323         return 0;
1324 }
1325
1326 int board_nand_init(struct nand_chip *nand)
1327 {
1328         int ret = 0;
1329
1330         nand->ecc.mode = NAND_ECC_SOFT;
1331 #ifdef CONFIG_SYS_NAND_DBW_16
1332         nand->options = NAND_BUSWIDTH_16;
1333         nand->read_buf = nand_read_buf16;
1334 #else
1335         nand->read_buf = nand_read_buf;
1336 #endif
1337         nand->cmd_ctrl = at91_nand_hwcontrol;
1338 #ifdef CONFIG_SYS_NAND_READY_PIN
1339         nand->dev_ready = at91_nand_ready;
1340 #else
1341         nand->dev_ready = at91_nand_wait_ready;
1342 #endif
1343         nand->chip_delay = 20;
1344
1345 #ifdef CONFIG_ATMEL_NAND_HWECC
1346 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1347         ret = atmel_pmecc_nand_init_params(nand, &mtd);
1348 #endif
1349 #endif
1350
1351         return ret;
1352 }
1353
1354 void nand_init(void)
1355 {
1356         mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1357         mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
1358         mtd.priv = &nand_chip;
1359         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1360         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1361         board_nand_init(&nand_chip);
1362
1363 #ifdef CONFIG_SPL_NAND_ECC
1364         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1365                 nand_chip.ecc.calculate = nand_calculate_ecc;
1366                 nand_chip.ecc.correct = nand_correct_data;
1367         }
1368 #endif
1369
1370         if (nand_chip.select_chip)
1371                 nand_chip.select_chip(&mtd, 0);
1372 }
1373
1374 void nand_deselect(void)
1375 {
1376         if (nand_chip.select_chip)
1377                 nand_chip.select_chip(&mtd, -1);
1378 }
1379
1380 #else
1381
1382 #ifndef CONFIG_SYS_NAND_BASE_LIST
1383 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1384 #endif
1385 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1386 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1387
1388 int atmel_nand_chip_init(int devnum, ulong base_addr)
1389 {
1390         int ret;
1391         struct mtd_info *mtd = &nand_info[devnum];
1392         struct nand_chip *nand = &nand_chip[devnum];
1393
1394         mtd->priv = nand;
1395         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1396
1397 #ifdef CONFIG_NAND_ECC_BCH
1398         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1399 #else
1400         nand->ecc.mode = NAND_ECC_SOFT;
1401 #endif
1402 #ifdef CONFIG_SYS_NAND_DBW_16
1403         nand->options = NAND_BUSWIDTH_16;
1404 #endif
1405         nand->cmd_ctrl = at91_nand_hwcontrol;
1406 #ifdef CONFIG_SYS_NAND_READY_PIN
1407         nand->dev_ready = at91_nand_ready;
1408 #endif
1409         nand->chip_delay = 75;
1410
1411         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1412         if (ret)
1413                 return ret;
1414
1415 #ifdef CONFIG_ATMEL_NAND_HWECC
1416 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1417         ret = atmel_pmecc_nand_init_params(nand, mtd);
1418 #else
1419         ret = atmel_hwecc_nand_init_param(nand, mtd);
1420 #endif
1421         if (ret)
1422                 return ret;
1423 #endif
1424
1425         ret = nand_scan_tail(mtd);
1426         if (!ret)
1427                 nand_register(devnum);
1428
1429         return ret;
1430 }
1431
1432 void board_nand_init(void)
1433 {
1434         int i;
1435         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1436                 if (atmel_nand_chip_init(i, base_addr[i]))
1437                         dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1438                                 i);
1439 }
1440 #endif /* CONFIG_SPL_BUILD */