drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
   2  *
   3  * Copyright (c) 2006-2008 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <common.h>
  24 #include <malloc.h>
  25
  26 #include <linux/mtd/mtd.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/nand_ecc.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/errno.h>
  32
  33 #ifdef VERBOSE_DEBUG
  34 #define DEBUG_ELBC
  35 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  36 #else
  37 #define vdbg(format, arg...) do {} while (0)
  38 #endif
  39
  40 /* Can't use plain old DEBUG because the linux mtd
  41  * headers define it as a macro.
  42  */
  43 #ifdef DEBUG_ELBC
  44 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  45 #else
  46 #define dbg(format, arg...) do {} while (0)
  47 #endif
  48
  49 #define MAX_BANKS 8
  50 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  51 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
  52
  53 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  54
  55 struct fsl_elbc_ctrl;
  56
  57 /* mtd information per set */
  58
  59 struct fsl_elbc_mtd {
  60         struct mtd_info mtd;
  61         struct nand_chip chip;
  62         struct fsl_elbc_ctrl *ctrl;
  63
  64         struct device *dev;
  65         int bank;               /* Chip select bank number           */
  66         u8 __iomem *vbase;      /* Chip select base virtual address  */
  67         int page_size;          /* NAND page size (0=512, 1=2048)    */
  68         unsigned int fmr;       /* FCM Flash Mode Register value     */
  69 };
  70
  71 /* overview of the fsl elbc controller */
  72
  73 struct fsl_elbc_ctrl {
  74         struct nand_hw_control controller;
  75         struct fsl_elbc_mtd *chips[MAX_BANKS];
  76
  77         /* device info */
  78         lbus83xx_t *regs;
  79         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  80         unsigned int page;       /* Last page written to / read from      */
  81         unsigned int read_bytes; /* Number of bytes read during command   */
  82         unsigned int column;     /* Saved column from SEQIN               */
  83         unsigned int index;      /* Pointer to next byte to 'read'        */
  84         unsigned int status;     /* status read from LTESR after last op  */
  85         unsigned int mdr;        /* UPM/FCM Data Register value           */
  86         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  87         unsigned int oob;        /* Non zero if operating on OOB data     */
  88         uint8_t *oob_poi;        /* Place to write ECC after read back    */
  89 };
  90
  91 /* These map to the positions used by the FCM hardware ECC generator */
  92
  93 /* Small Page FLASH with FMR[ECCM] = 0 */
  94 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  95         .eccbytes = 3,
  96         .eccpos = {6, 7, 8},
  97         .oobfree = { {0, 5}, {9, 7} },
  98         .oobavail = 12,
  99 };
 100
 101 /* Small Page FLASH with FMR[ECCM] = 1 */
 102 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
 103         .eccbytes = 3,
 104         .eccpos = {8, 9, 10},
 105         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 106         .oobavail = 12,
 107 };
 108
 109 /* Large Page FLASH with FMR[ECCM] = 0 */
 110 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 111         .eccbytes = 12,
 112         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 113         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 114         .oobavail = 48,
 115 };
 116
 117 /* Large Page FLASH with FMR[ECCM] = 1 */
 118 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 119         .eccbytes = 12,
 120         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 121         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 122         .oobavail = 48,
 123 };
 124
 125 /*=================================*/
 126
 127 /*
 128  * Set up the FCM hardware block and page address fields, and the fcm
 129  * structure addr field to point to the correct FCM buffer in memory
 130  */
 131 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 132 {
 133         struct nand_chip *chip = mtd->priv;
 134         struct fsl_elbc_mtd *priv = chip->priv;
 135         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 136         lbus83xx_t *lbc = ctrl->regs;
 137         int buf_num;
 138
 139         ctrl->page = page_addr;
 140
 141         if (priv->page_size) {
 142                 out_be32(&lbc->fbar, page_addr >> 6);
 143                 out_be32(&lbc->fpar,
 144                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 145                          (oob ? FPAR_LP_MS : 0) | column);
 146                 buf_num = (page_addr & 1) << 2;
 147         } else {
 148                 out_be32(&lbc->fbar, page_addr >> 5);
 149                 out_be32(&lbc->fpar,
 150                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 151                          (oob ? FPAR_SP_MS : 0) | column);
 152                 buf_num = page_addr & 7;
 153         }
 154
 155         ctrl->addr = priv->vbase + buf_num * 1024;
 156         ctrl->index = column;
 157
 158         /* for OOB data point to the second half of the buffer */
 159         if (oob)
 160                 ctrl->index += priv->page_size ? 2048 : 512;
 161
 162         vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 163              "index %x, pes %d ps %d\n",
 164              buf_num, ctrl->addr, priv->vbase, ctrl->index,
 165              chip->phys_erase_shift, chip->page_shift);
 166 }
 167
 168 /*
 169  * execute FCM command and wait for it to complete
 170  */
 171 static int fsl_elbc_run_command(struct mtd_info *mtd)
 172 {
 173         struct nand_chip *chip = mtd->priv;
 174         struct fsl_elbc_mtd *priv = chip->priv;
 175         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 176         lbus83xx_t *lbc = ctrl->regs;
 177         long long end_tick;
 178         u32 ltesr;
 179
 180         /* Setup the FMR[OP] to execute without write protection */
 181         out_be32(&lbc->fmr, priv->fmr | 3);
 182         if (ctrl->use_mdr)
 183                 out_be32(&lbc->mdr, ctrl->mdr);
 184
 185         vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 186              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 187         vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
 188              "fbcr=%08x bank=%d\n",
 189              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 190              in_be32(&lbc->fbcr), priv->bank);
 191
 192         /* execute special operation */
 193         out_be32(&lbc->lsor, priv->bank);
 194
 195         /* wait for FCM complete flag or timeout */
 196         end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
 197
 198         ltesr = 0;
 199         while (end_tick > get_ticks()) {
 200                 ltesr = in_be32(&lbc->ltesr);
 201                 if (ltesr & LTESR_CC)
 202                         break;
 203         }
 204
 205         ctrl->status = ltesr & LTESR_NAND_MASK;
 206         out_be32(&lbc->ltesr, ctrl->status);
 207         out_be32(&lbc->lteatr, 0);
 208
 209         /* store mdr value in case it was needed */
 210         if (ctrl->use_mdr)
 211                 ctrl->mdr = in_be32(&lbc->mdr);
 212
 213         ctrl->use_mdr = 0;
 214
 215         vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 216              ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 217
 218         /* returns 0 on success otherwise non-zero) */
 219         return ctrl->status == LTESR_CC ? 0 : -EIO;
 220 }
 221
 222 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 223 {
 224         struct fsl_elbc_mtd *priv = chip->priv;
 225         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 226         lbus83xx_t *lbc = ctrl->regs;
 227
 228         if (priv->page_size) {
 229                 out_be32(&lbc->fir,
 230                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 231                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 232                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 233                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 234                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 235
 236                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 237                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 238         } else {
 239                 out_be32(&lbc->fir,
 240                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 241                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 242                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 243                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 244
 245                 if (oob)
 246                         out_be32(&lbc->fcr,
 247                                  NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 248                 else
 249                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 250         }
 251 }
 252
 253 /* cmdfunc send commands to the FCM */
 254 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 255                              int column, int page_addr)
 256 {
 257         struct nand_chip *chip = mtd->priv;
 258         struct fsl_elbc_mtd *priv = chip->priv;
 259         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 260         lbus83xx_t *lbc = ctrl->regs;
 261
 262         ctrl->use_mdr = 0;
 263
 264         /* clear the read buffer */
 265         ctrl->read_bytes = 0;
 266         if (command != NAND_CMD_PAGEPROG)
 267                 ctrl->index = 0;
 268
 269         switch (command) {
 270         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 271         case NAND_CMD_READ1:
 272                 column += 256;
 273
 274         /* fall-through */
 275         case NAND_CMD_READ0:
 276                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 277                      " 0x%x, column: 0x%x.\n", page_addr, column);
 278
 279                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 280                 set_addr(mtd, 0, page_addr, 0);
 281
 282                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 283                 ctrl->index += column;
 284
 285                 fsl_elbc_do_read(chip, 0);
 286                 fsl_elbc_run_command(mtd);
 287                 return;
 288
 289         /* READOOB reads only the OOB because no ECC is performed. */
 290         case NAND_CMD_READOOB:
 291                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 292                      " 0x%x, column: 0x%x.\n", page_addr, column);
 293
 294                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 295                 set_addr(mtd, column, page_addr, 1);
 296
 297                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 298
 299                 fsl_elbc_do_read(chip, 1);
 300                 fsl_elbc_run_command(mtd);
 301
 302                 return;
 303
 304         /* READID must read all 5 possible bytes while CEB is active */
 305         case NAND_CMD_READID:
 306                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 307
 308                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 309                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 310                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 311                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 312                 /* 5 bytes for manuf, device and exts */
 313                 out_be32(&lbc->fbcr, 5);
 314                 ctrl->read_bytes = 5;
 315                 ctrl->use_mdr = 1;
 316                 ctrl->mdr = 0;
 317
 318                 set_addr(mtd, 0, 0, 0);
 319                 fsl_elbc_run_command(mtd);
 320                 return;
 321
 322         /* ERASE1 stores the block and page address */
 323         case NAND_CMD_ERASE1:
 324                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 325                      "page_addr: 0x%x.\n", page_addr);
 326                 set_addr(mtd, 0, page_addr, 0);
 327                 return;
 328
 329         /* ERASE2 uses the block and page address from ERASE1 */
 330         case NAND_CMD_ERASE2:
 331                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 332
 333                 out_be32(&lbc->fir,
 334                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 335                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 336                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 337
 338                 out_be32(&lbc->fcr,
 339                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 340                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 341
 342                 out_be32(&lbc->fbcr, 0);
 343                 ctrl->read_bytes = 0;
 344
 345                 fsl_elbc_run_command(mtd);
 346                 return;
 347
 348         /* SEQIN sets up the addr buffer and all registers except the length */
 349         case NAND_CMD_SEQIN: {
 350                 u32 fcr;
 351                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 352                      "page_addr: 0x%x, column: 0x%x.\n",
 353                      page_addr, column);
 354
 355                 ctrl->column = column;
 356                 ctrl->oob = 0;
 357
 358                 if (priv->page_size) {
 359                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 360                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 361
 362                         out_be32(&lbc->fir,
 363                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 364                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 365                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 366                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 367                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 368                 } else {
 369                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 370                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 371
 372                         out_be32(&lbc->fir,
 373                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 374                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 375                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 376                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 377                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 378                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 379
 380                         if (column >= mtd->writesize) {
 381                                 /* OOB area --> READOOB */
 382                                 column -= mtd->writesize;
 383                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 384                                 ctrl->oob = 1;
 385                         } else if (column < 256) {
 386                                 /* First 256 bytes --> READ0 */
 387                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 388                         } else {
 389                                 /* Second 256 bytes --> READ1 */
 390                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 391                         }
 392                 }
 393
 394                 out_be32(&lbc->fcr, fcr);
 395                 set_addr(mtd, column, page_addr, ctrl->oob);
 396                 return;
 397         }
 398
 399         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 400         case NAND_CMD_PAGEPROG: {
 401                 int full_page;
 402                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 403                      "writing %d bytes.\n", ctrl->index);
 404
 405                 /* if the write did not start at 0 or is not a full page
 406                  * then set the exact length, otherwise use a full page
 407                  * write so the HW generates the ECC.
 408                  */
 409                 if (ctrl->oob || ctrl->column != 0 ||
 410                     ctrl->index != mtd->writesize + mtd->oobsize) {
 411                         out_be32(&lbc->fbcr, ctrl->index);
 412                         full_page = 0;
 413                 } else {
 414                         out_be32(&lbc->fbcr, 0);
 415                         full_page = 1;
 416                 }
 417
 418                 fsl_elbc_run_command(mtd);
 419
 420                 /* Read back the page in order to fill in the ECC for the
 421                  * caller.  Is this really needed?
 422                  */
 423                 if (full_page && ctrl->oob_poi) {
 424                         out_be32(&lbc->fbcr, 3);
 425                         set_addr(mtd, 6, page_addr, 1);
 426
 427                         ctrl->read_bytes = mtd->writesize + 9;
 428
 429                         fsl_elbc_do_read(chip, 1);
 430                         fsl_elbc_run_command(mtd);
 431
 432                         memcpy_fromio(ctrl->oob_poi + 6,
 433                                       &ctrl->addr[ctrl->index], 3);
 434                         ctrl->index += 3;
 435                 }
 436
 437                 ctrl->oob_poi = NULL;
 438                 return;
 439         }
 440
 441         /* CMD_STATUS must read the status byte while CEB is active */
 442         /* Note - it does not wait for the ready line */
 443         case NAND_CMD_STATUS:
 444                 out_be32(&lbc->fir,
 445                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 446                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 447                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 448                 out_be32(&lbc->fbcr, 1);
 449                 set_addr(mtd, 0, 0, 0);
 450                 ctrl->read_bytes = 1;
 451
 452                 fsl_elbc_run_command(mtd);
 453
 454                 /* The chip always seems to report that it is
 455                  * write-protected, even when it is not.
 456                  */
 457                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 458                 return;
 459
 460         /* RESET without waiting for the ready line */
 461         case NAND_CMD_RESET:
 462                 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 463                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 464                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 465                 fsl_elbc_run_command(mtd);
 466                 return;
 467
 468         default:
 469                 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 470                         command);
 471         }
 472 }
 473
 474 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 475 {
 476         /* The hardware does not seem to support multiple
 477          * chips per bank.
 478          */
 479 }
 480
 481 /*
 482  * Write buf to the FCM Controller Data Buffer
 483  */
 484 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 485 {
 486         struct nand_chip *chip = mtd->priv;
 487         struct fsl_elbc_mtd *priv = chip->priv;
 488         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 489         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 490
 491         if (len <= 0) {
 492                 printf("write_buf of %d bytes", len);
 493                 ctrl->status = 0;
 494                 return;
 495         }
 496
 497         if ((unsigned int)len > bufsize - ctrl->index) {
 498                 printf("write_buf beyond end of buffer "
 499                        "(%d requested, %u available)\n",
 500                        len, bufsize - ctrl->index);
 501                 len = bufsize - ctrl->index;
 502         }
 503
 504         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 505         /*
 506          * This is workaround for the weird elbc hangs during nand write,
 507          * Scott Wood says: "...perhaps difference in how long it takes a
 508          * write to make it through the localbus compared to a write to IMMR
 509          * is causing problems, and sync isn't helping for some reason."
 510          * Reading back the last byte helps though.
 511          */
 512         in_8(&ctrl->addr[ctrl->index] + len - 1);
 513
 514         ctrl->index += len;
 515 }
 516
 517 /*
 518  * read a byte from either the FCM hardware buffer if it has any data left
 519  * otherwise issue a command to read a single byte.
 520  */
 521 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 522 {
 523         struct nand_chip *chip = mtd->priv;
 524         struct fsl_elbc_mtd *priv = chip->priv;
 525         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 526
 527         /* If there are still bytes in the FCM, then use the next byte. */
 528         if (ctrl->index < ctrl->read_bytes)
 529                 return in_8(&ctrl->addr[ctrl->index++]);
 530
 531         printf("read_byte beyond end of buffer\n");
 532         return ERR_BYTE;
 533 }
 534
 535 /*
 536  * Read from the FCM Controller Data Buffer
 537  */
 538 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 539 {
 540         struct nand_chip *chip = mtd->priv;
 541         struct fsl_elbc_mtd *priv = chip->priv;
 542         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 543         int avail;
 544
 545         if (len < 0)
 546                 return;
 547
 548         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 549         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 550         ctrl->index += avail;
 551
 552         if (len > avail)
 553                 printf("read_buf beyond end of buffer "
 554                        "(%d requested, %d available)\n",
 555                        len, avail);
 556 }
 557
 558 /*
 559  * Verify buffer against the FCM Controller Data Buffer
 560  */
 561 static int fsl_elbc_verify_buf(struct mtd_info *mtd,
 562                                const u_char *buf, int len)
 563 {
 564         struct nand_chip *chip = mtd->priv;
 565         struct fsl_elbc_mtd *priv = chip->priv;
 566         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 567         int i;
 568
 569         if (len < 0) {
 570                 printf("write_buf of %d bytes", len);
 571                 return -EINVAL;
 572         }
 573
 574         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 575                 printf("verify_buf beyond end of buffer "
 576                        "(%d requested, %u available)\n",
 577                        len, ctrl->read_bytes - ctrl->index);
 578
 579                 ctrl->index = ctrl->read_bytes;
 580                 return -EINVAL;
 581         }
 582
 583         for (i = 0; i < len; i++)
 584                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 585                         break;
 586
 587         ctrl->index += len;
 588         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 589 }
 590
 591 /* This function is called after Program and Erase Operations to
 592  * check for success or failure.
 593  */
 594 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 595 {
 596         struct fsl_elbc_mtd *priv = chip->priv;
 597         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 598         lbus83xx_t *lbc = ctrl->regs;
 599
 600         if (ctrl->status != LTESR_CC)
 601                 return NAND_STATUS_FAIL;
 602
 603         /* Use READ_STATUS command, but wait for the device to be ready */
 604         ctrl->use_mdr = 0;
 605         out_be32(&lbc->fir,
 606                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 607                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 608         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 609         out_be32(&lbc->fbcr, 1);
 610         set_addr(mtd, 0, 0, 0);
 611         ctrl->read_bytes = 1;
 612
 613         fsl_elbc_run_command(mtd);
 614
 615         if (ctrl->status != LTESR_CC)
 616                 return NAND_STATUS_FAIL;
 617
 618         /* The chip always seems to report that it is
 619          * write-protected, even when it is not.
 620          */
 621         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 622         return fsl_elbc_read_byte(mtd);
 623 }
 624
 625 static int fsl_elbc_read_page(struct mtd_info *mtd,
 626                               struct nand_chip *chip,
 627                               uint8_t *buf)
 628 {
 629         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 630         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 631
 632         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 633                 mtd->ecc_stats.failed++;
 634
 635         return 0;
 636 }
 637
 638 /* ECC will be calculated automatically, and errors will be detected in
 639  * waitfunc.
 640  */
 641 static void fsl_elbc_write_page(struct mtd_info *mtd,
 642                                 struct nand_chip *chip,
 643                                 const uint8_t *buf)
 644 {
 645         struct fsl_elbc_mtd *priv = chip->priv;
 646         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 647
 648         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 649         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 650
 651         ctrl->oob_poi = chip->oob_poi;
 652 }
 653
 654 static struct fsl_elbc_ctrl *elbc_ctrl;
 655
 656 static void fsl_elbc_ctrl_init(void)
 657 {
 658         immap_t *im = (immap_t *)CFG_IMMR;
 659
 660         elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 661         if (!elbc_ctrl)
 662                 return;
 663
 664         elbc_ctrl->regs = &im->lbus;
 665
 666         /* clear event registers */
 667         out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
 668         out_be32(&elbc_ctrl->regs->lteatr, 0);
 669
 670         /* Enable interrupts for any detected events */
 671         out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
 672
 673         elbc_ctrl->read_bytes = 0;
 674         elbc_ctrl->index = 0;
 675         elbc_ctrl->addr = NULL;
 676 }
 677
 678 int board_nand_init(struct nand_chip *nand)
 679 {
 680         struct fsl_elbc_mtd *priv;
 681         uint32_t br, or;
 682
 683         if (!elbc_ctrl) {
 684                 fsl_elbc_ctrl_init();
 685                 if (!elbc_ctrl)
 686                         return -1;
 687         }
 688
 689         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 690         if (!priv)
 691                 return -ENOMEM;
 692
 693         priv->ctrl = elbc_ctrl;
 694         priv->vbase = nand->IO_ADDR_R;
 695
 696         /* Find which chip select it is connected to.  It'd be nice
 697          * if we could pass more than one datum to the NAND driver...
 698          */
 699         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 700                 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
 701                 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 702
 703                 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
 704                     (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R)
 705                         break;
 706         }
 707
 708         if (priv->bank >= MAX_BANKS) {
 709                 printf("fsl_elbc_nand: address did not match any "
 710                        "chip selects\n");
 711                 return -ENODEV;
 712         }
 713
 714         elbc_ctrl->chips[priv->bank] = priv;
 715
 716         /* fill in nand_chip structure */
 717         /* set up function call table */
 718         nand->read_byte = fsl_elbc_read_byte;
 719         nand->write_buf = fsl_elbc_write_buf;
 720         nand->read_buf = fsl_elbc_read_buf;
 721         nand->verify_buf = fsl_elbc_verify_buf;
 722         nand->select_chip = fsl_elbc_select_chip;
 723         nand->cmdfunc = fsl_elbc_cmdfunc;
 724         nand->waitfunc = fsl_elbc_wait;
 725
 726         /* set up nand options */
 727         nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
 728
 729         nand->controller = &elbc_ctrl->controller;
 730         nand->priv = priv;
 731
 732         nand->ecc.read_page = fsl_elbc_read_page;
 733         nand->ecc.write_page = fsl_elbc_write_page;
 734
 735         /* If CS Base Register selects full hardware ECC then use it */
 736         if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 737                 nand->ecc.mode = NAND_ECC_HW;
 738
 739                 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 740                                    &fsl_elbc_oob_sp_eccm1 :
 741                                    &fsl_elbc_oob_sp_eccm0;
 742
 743                 nand->ecc.size = 512;
 744                 nand->ecc.bytes = 3;
 745                 nand->ecc.steps = 1;
 746         } else {
 747                 /* otherwise fall back to default software ECC */
 748                 nand->ecc.mode = NAND_ECC_SOFT;
 749         }
 750
 751         priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 752
 753         /* adjust Option Register and ECC to match Flash page size */
 754         if (or & OR_FCM_PGS) {
 755                 priv->page_size = 1;
 756
 757                 /* adjust ecc setup if needed */
 758                 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 759                         nand->ecc.steps = 4;
 760                         nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 761                                            &fsl_elbc_oob_lp_eccm1 :
 762                                            &fsl_elbc_oob_lp_eccm0;
 763                 }
 764         }
 765
 766         return 0;
 767 }