drivers/mtd/nand/fsl_ifc_spl.c

   1 /*
   2  * NAND boot for Freescale Integrated Flash Controller, NAND FCM
   3  *
   4  * Copyright 2011 Freescale Semiconductor, Inc.
   5  * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <fsl_ifc.h>
  13 #include <linux/mtd/nand.h>
  14
  15 static inline int is_blank(uchar *addr, int page_size)
  16 {
  17         int i;
  18
  19         for (i = 0; i < page_size; i++) {
  20                 if (__raw_readb(&addr[i]) != 0xff)
  21                         return 0;
  22         }
  23
  24         /*
  25          * For the SPL, don't worry about uncorrectable errors
  26          * where the main area is all FFs but shouldn't be.
  27          */
  28         return 1;
  29 }
  30
  31 /* returns nonzero if entire page is blank */
  32 static inline int check_read_ecc(uchar *buf, u32 *eccstat,
  33                                  unsigned int bufnum, int page_size)
  34 {
  35         u32 reg = eccstat[bufnum / 4];
  36         int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
  37
  38         if (errors == 0xf) { /* uncorrectable */
  39                 /* Blank pages fail hw ECC checks */
  40                 if (is_blank(buf, page_size))
  41                         return 1;
  42
  43                 puts("ecc error\n");
  44                 for (;;)
  45                         ;
  46         }
  47
  48         return 0;
  49 }
  50
  51 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
  52 {
  53         struct fsl_ifc *ifc = IFC_BASE_ADDR;
  54         u32 status;
  55         u32 eccstat[4];
  56         int bufperpage = page_size / 512;
  57         int bufnum_end, i;
  58
  59         bufnum *= bufperpage;
  60         bufnum_end = bufnum + bufperpage - 1;
  61
  62         do {
  63                 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  64         } while (!(status & IFC_NAND_EVTER_STAT_OPC));
  65
  66         if (status & IFC_NAND_EVTER_STAT_FTOER) {
  67                 puts("flash time out error\n");
  68                 for (;;)
  69                         ;
  70         }
  71
  72         for (i = bufnum / 4; i <= bufnum_end / 4; i++)
  73                 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  74
  75         for (i = bufnum; i <= bufnum_end; i++) {
  76                 if (check_read_ecc(buf, eccstat, i, page_size))
  77                         break;
  78         }
  79
  80         ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
  81 }
  82
  83 static inline int bad_block(uchar *marker, int port_size)
  84 {
  85         if (port_size == 8)
  86                 return __raw_readb(marker) != 0xff;
  87         else
  88                 return __raw_readw((u16 *)marker) != 0xffff;
  89 }
  90
  91 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  92 {
  93         struct fsl_ifc *ifc = IFC_BASE_ADDR;
  94         uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  95         int page_size;
  96         int port_size;
  97         int pages_per_blk;
  98         int blk_size;
  99         int bad_marker = 0;
 100         int bufnum_mask, bufnum;
 101
 102         int csor, cspr;
 103         int pos = 0;
 104         int j = 0;
 105
 106         int sram_addr;
 107         int pg_no;
 108         uchar *dst = vdst;
 109
 110         /* Get NAND Flash configuration */
 111         csor = CONFIG_SYS_NAND_CSOR;
 112         cspr = CONFIG_SYS_NAND_CSPR;
 113
 114         port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
 115
 116         if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
 117                 page_size = 8192;
 118                 bufnum_mask = 0x0;
 119         } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
 120                 page_size = 4096;
 121                 bufnum_mask = 0x1;
 122         } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
 123                 page_size = 2048;
 124                 bufnum_mask = 0x3;
 125         } else {
 126                 page_size = 512;
 127                 bufnum_mask = 0xf;
 128
 129                 if (port_size == 8)
 130                         bad_marker = 5;
 131         }
 132
 133         pages_per_blk =
 134                 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
 135
 136         blk_size = pages_per_blk * page_size;
 137
 138         /* Open Full SRAM mapping for spare are access */
 139         ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
 140
 141         /* Clear Boot events */
 142         ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
 143
 144         /* Program FIR/FCR for Large/Small page */
 145         if (page_size > 512) {
 146                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 147                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 148                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 149                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 150                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 151                           (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
 152                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 153
 154                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 155                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 156                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 157         } else {
 158                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 159                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 160                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 161                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 162                           (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
 163                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 164
 165                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 166                           NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 167         }
 168
 169         /* Program FBCR = 0 for full page read */
 170         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 171
 172         /* Read and copy u-boot on SDRAM from NAND device, In parallel
 173          * check for Bad block if found skip it and read continue to
 174          * next Block
 175          */
 176         while (pos < uboot_size) {
 177                 int i = 0;
 178                 do {
 179                         pg_no = offs / page_size;
 180                         bufnum = pg_no & bufnum_mask;
 181                         sram_addr = bufnum * page_size * 2;
 182
 183                         ifc_out32(&ifc->ifc_nand.row0, pg_no);
 184                         ifc_out32(&ifc->ifc_nand.col0, 0);
 185                         /* start read */
 186                         ifc_out32(&ifc->ifc_nand.nandseq_strt,
 187                                   IFC_NAND_SEQ_STRT_FIR_STRT);
 188
 189                         /* wait for read to complete */
 190                         nand_wait(&buf[sram_addr], bufnum, page_size);
 191
 192                         /*
 193                          * If either of the first two pages are marked bad,
 194                          * continue to the next block.
 195                          */
 196                         if (i++ < 2 &&
 197                             bad_block(&buf[sram_addr + page_size + bad_marker],
 198                                       port_size)) {
 199                                 puts("skipping\n");
 200                                 offs = (offs + blk_size) & ~(blk_size - 1);
 201                                 pos &= ~(blk_size - 1);
 202                                 break;
 203                         }
 204
 205                         for (j = 0; j < page_size; j++)
 206                                 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
 207
 208                         pos += page_size;
 209                         offs += page_size;
 210                 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
 211         }
 212
 213         return 0;
 214 }
 215
 216 /*
 217  * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
 218  * configured and available since this code loads the main U-boot image
 219  * from NAND into SDRAM and starts from there.
 220  */
 221 void nand_boot(void)
 222 {
 223         __attribute__((noreturn)) void (*uboot)(void);
 224         /*
 225          * Load U-Boot image from NAND into RAM
 226          */
 227         nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
 228                             CONFIG_SYS_NAND_U_BOOT_SIZE,
 229                             (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 230
 231 #ifdef CONFIG_NAND_ENV_DST
 232         nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 233                             (uchar *)CONFIG_NAND_ENV_DST);
 234
 235 #ifdef CONFIG_ENV_OFFSET_REDUND
 236         nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 237                             (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 238 #endif
 239 #endif
 240         /*
 241          * Jump to U-Boot image
 242          */
 243 #ifdef CONFIG_SPL_FLUSH_IMAGE
 244         /*
 245          * Clean d-cache and invalidate i-cache, to
 246          * make sure that no stale data is executed.
 247          */
 248         flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
 249 #endif
 250         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 251         uboot();
 252 }