drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  18  * MA 02110-1301, USA.
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <linux/err.h>
  24 #include <asm/io.h>
  25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
  26 #include <asm/arch/imx-regs.h>
  27 #endif
  28 #include <fsl_nfc.h>
  29
  30 #define DRIVER_NAME "mxc_nand"
  31
  32 typedef enum {false, true} bool;
  33
  34 struct mxc_nand_host {
  35         struct mtd_info                 mtd;
  36         struct nand_chip                *nand;
  37
  38         struct fsl_nfc_regs __iomem     *regs;
  39         int                             spare_only;
  40         int                             status_request;
  41         int                             pagesize_2k;
  42         int                             clk_act;
  43         uint16_t                        col_addr;
  44         unsigned int                    page_addr;
  45 };
  46
  47 static struct mxc_nand_host mxc_host;
  48 static struct mxc_nand_host *host = &mxc_host;
  49
  50 /* Define delays in microsec for NAND device operations */
  51 #define TROP_US_DELAY   2000
  52 /* Macros to get byte and bit positions of ECC */
  53 #define COLPOS(x)  ((x) >> 3)
  54 #define BITPOS(x) ((x) & 0xf)
  55
  56 /* Define single bit Error positions in Main & Spare area */
  57 #define MAIN_SINGLEBIT_ERROR 0x4
  58 #define SPARE_SINGLEBIT_ERROR 0x1
  59
  60 /* OOB placement block for use with hardware ecc generation */
  61 #if defined(MXC_NFC_V1)
  62 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  63 static struct nand_ecclayout nand_hw_eccoob = {
  64         .eccbytes = 5,
  65         .eccpos = {6, 7, 8, 9, 10},
  66         .oobfree = { {0, 5}, {11, 5}, }
  67 };
  68 #else
  69 static struct nand_ecclayout nand_hw_eccoob2k = {
  70         .eccbytes = 20,
  71         .eccpos = {
  72                 6, 7, 8, 9, 10,
  73                 22, 23, 24, 25, 26,
  74                 38, 39, 40, 41, 42,
  75                 54, 55, 56, 57, 58,
  76         },
  77         .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  78 };
  79 #endif
  80 #elif defined(MXC_NFC_V2_1)
  81 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  82 static struct nand_ecclayout nand_hw_eccoob = {
  83         .eccbytes = 9,
  84         .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  85         .oobfree = { {2, 5} }
  86 };
  87 #else
  88 static struct nand_ecclayout nand_hw_eccoob2k = {
  89         .eccbytes = 36,
  90         .eccpos = {
  91                 7, 8, 9, 10, 11, 12, 13, 14, 15,
  92                 23, 24, 25, 26, 27, 28, 29, 30, 31,
  93                 39, 40, 41, 42, 43, 44, 45, 46, 47,
  94                 55, 56, 57, 58, 59, 60, 61, 62, 63,
  95         },
  96         .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  97 };
  98 #endif
  99 #endif
 100
 101 static int is_16bit_nand(void)
 102 {
 103 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
 104         return 1;
 105 #else
 106         return 0;
 107 #endif
 108 }
 109
 110 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
 111 {
 112         uint32_t *d = dest;
 113
 114         size >>= 2;
 115         while (size--)
 116                 __raw_writel(__raw_readl(source++), d++);
 117         return dest;
 118 }
 119
 120 /*
 121  * This function polls the NANDFC to wait for the basic operation to
 122  * complete by checking the INT bit of config2 register.
 123  */
 124 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 125                                 uint16_t param)
 126 {
 127         uint32_t tmp;
 128
 129         while (max_retries-- > 0) {
 130                 if (readw(&host->regs->config2) & NFC_INT) {
 131                         tmp = readw(&host->regs->config2);
 132                         tmp  &= ~NFC_INT;
 133                         writew(tmp, &host->regs->config2);
 134                         break;
 135                 }
 136                 udelay(1);
 137         }
 138         if (max_retries < 0) {
 139                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 140                                 __func__, param);
 141         }
 142 }
 143
 144 /*
 145  * This function issues the specified command to the NAND device and
 146  * waits for completion.
 147  */
 148 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 149 {
 150         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
 151
 152         writew(cmd, &host->regs->flash_cmd);
 153         writew(NFC_CMD, &host->regs->config2);
 154
 155         /* Wait for operation to complete */
 156         wait_op_done(host, TROP_US_DELAY, cmd);
 157 }
 158
 159 /*
 160  * This function sends an address (or partial address) to the
 161  * NAND device. The address is used to select the source/destination for
 162  * a NAND command.
 163  */
 164 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 165 {
 166         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
 167
 168         writew(addr, &host->regs->flash_addr);
 169         writew(NFC_ADDR, &host->regs->config2);
 170
 171         /* Wait for operation to complete */
 172         wait_op_done(host, TROP_US_DELAY, addr);
 173 }
 174
 175 /*
 176  * This function requests the NANDFC to initiate the transfer
 177  * of data currently in the NANDFC RAM buffer to the NAND device.
 178  */
 179 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 180                         int spare_only)
 181 {
 182         if (spare_only)
 183                 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
 184
 185         if (is_mxc_nfc_21()) {
 186                 int i;
 187                 /*
 188                  *  The controller copies the 64 bytes of spare data from
 189                  *  the first 16 bytes of each of the 4 64 byte spare buffers.
 190                  *  Copy the contiguous data starting in spare_area[0] to
 191                  *  the four spare area buffers.
 192                  */
 193                 for (i = 1; i < 4; i++) {
 194                         void __iomem *src = &host->regs->spare_area[0][i * 16];
 195                         void __iomem *dst = &host->regs->spare_area[i][0];
 196
 197                         mxc_nand_memcpy32(dst, src, 16);
 198                 }
 199         }
 200
 201         writew(buf_id, &host->regs->buf_addr);
 202
 203         /* Configure spare or page+spare access */
 204         if (!host->pagesize_2k) {
 205                 uint16_t config1 = readw(&host->regs->config1);
 206                 if (spare_only)
 207                         config1 |= NFC_SP_EN;
 208                 else
 209                         config1 &= ~NFC_SP_EN;
 210                 writew(config1, &host->regs->config1);
 211         }
 212
 213         writew(NFC_INPUT, &host->regs->config2);
 214
 215         /* Wait for operation to complete */
 216         wait_op_done(host, TROP_US_DELAY, spare_only);
 217 }
 218
 219 /*
 220  * Requests NANDFC to initiate the transfer of data from the
 221  * NAND device into in the NANDFC ram buffer.
 222  */
 223 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 224                 int spare_only)
 225 {
 226         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 227
 228         writew(buf_id, &host->regs->buf_addr);
 229
 230         /* Configure spare or page+spare access */
 231         if (!host->pagesize_2k) {
 232                 uint32_t config1 = readw(&host->regs->config1);
 233                 if (spare_only)
 234                         config1 |= NFC_SP_EN;
 235                 else
 236                         config1 &= ~NFC_SP_EN;
 237                 writew(config1, &host->regs->config1);
 238         }
 239
 240         writew(NFC_OUTPUT, &host->regs->config2);
 241
 242         /* Wait for operation to complete */
 243         wait_op_done(host, TROP_US_DELAY, spare_only);
 244
 245         if (is_mxc_nfc_21()) {
 246                 int i;
 247
 248                 /*
 249                  *  The controller copies the 64 bytes of spare data to
 250                  *  the first 16 bytes of each of the 4 spare buffers.
 251                  *  Make the data contiguous starting in spare_area[0].
 252                  */
 253                 for (i = 1; i < 4; i++) {
 254                         void __iomem *src = &host->regs->spare_area[i][0];
 255                         void __iomem *dst = &host->regs->spare_area[0][i * 16];
 256
 257                         mxc_nand_memcpy32(dst, src, 16);
 258                 }
 259         }
 260 }
 261
 262 /* Request the NANDFC to perform a read of the NAND device ID. */
 263 static void send_read_id(struct mxc_nand_host *host)
 264 {
 265         uint16_t tmp;
 266
 267         /* NANDFC buffer 0 is used for device ID output */
 268         writew(0x0, &host->regs->buf_addr);
 269
 270         /* Read ID into main buffer */
 271         tmp = readw(&host->regs->config1);
 272         tmp &= ~NFC_SP_EN;
 273         writew(tmp, &host->regs->config1);
 274
 275         writew(NFC_ID, &host->regs->config2);
 276
 277         /* Wait for operation to complete */
 278         wait_op_done(host, TROP_US_DELAY, 0);
 279 }
 280
 281 /*
 282  * This function requests the NANDFC to perform a read of the
 283  * NAND device status and returns the current status.
 284  */
 285 static uint16_t get_dev_status(struct mxc_nand_host *host)
 286 {
 287         void __iomem *main_buf = host->regs->main_area[1];
 288         uint32_t store;
 289         uint16_t ret, tmp;
 290         /* Issue status request to NAND device */
 291
 292         /* store the main area1 first word, later do recovery */
 293         store = readl(main_buf);
 294         /* NANDFC buffer 1 is used for device status */
 295         writew(1, &host->regs->buf_addr);
 296
 297         /* Read status into main buffer */
 298         tmp = readw(&host->regs->config1);
 299         tmp &= ~NFC_SP_EN;
 300         writew(tmp, &host->regs->config1);
 301
 302         writew(NFC_STATUS, &host->regs->config2);
 303
 304         /* Wait for operation to complete */
 305         wait_op_done(host, TROP_US_DELAY, 0);
 306
 307         /*
 308          *  Status is placed in first word of main buffer
 309          * get status, then recovery area 1 data
 310          */
 311         ret = readw(main_buf);
 312         writel(store, main_buf);
 313
 314         return ret;
 315 }
 316
 317 /* This function is used by upper layer to checks if device is ready */
 318 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 319 {
 320         /*
 321          * NFC handles R/B internally. Therefore, this function
 322          * always returns status as ready.
 323          */
 324         return 1;
 325 }
 326
 327 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 328 {
 329         struct nand_chip *nand_chip = mtd->priv;
 330         struct mxc_nand_host *host = nand_chip->priv;
 331         uint16_t tmp = readw(&host->regs->config1);
 332
 333         if (on)
 334                 tmp |= NFC_ECC_EN;
 335         else
 336                 tmp &= ~NFC_ECC_EN;
 337         writew(tmp, &host->regs->config1);
 338 }
 339
 340 #ifdef CONFIG_MXC_NAND_HWECC
 341 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 342 {
 343         /*
 344          * If HW ECC is enabled, we turn it on during init. There is
 345          * no need to enable again here.
 346          */
 347 }
 348
 349 #ifdef MXC_NFC_V2_1
 350 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 351                                       struct nand_chip *chip,
 352                                       int page, int sndcmd)
 353 {
 354         struct mxc_nand_host *host = chip->priv;
 355         uint8_t *buf = chip->oob_poi;
 356         int length = mtd->oobsize;
 357         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 358         uint8_t *bufpoi = buf;
 359         int i, toread;
 360
 361         MTDDEBUG(MTD_DEBUG_LEVEL0,
 362                         "%s: Reading OOB area of page %u to oob %p\n",
 363                          __FUNCTION__, host->page_addr, buf);
 364
 365         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 366         for (i = 0; i < chip->ecc.steps; i++) {
 367                 toread = min_t(int, length, chip->ecc.prepad);
 368                 if (toread) {
 369                         chip->read_buf(mtd, bufpoi, toread);
 370                         bufpoi += toread;
 371                         length -= toread;
 372                 }
 373                 bufpoi += chip->ecc.bytes;
 374                 host->col_addr += chip->ecc.bytes;
 375                 length -= chip->ecc.bytes;
 376
 377                 toread = min_t(int, length, chip->ecc.postpad);
 378                 if (toread) {
 379                         chip->read_buf(mtd, bufpoi, toread);
 380                         bufpoi += toread;
 381                         length -= toread;
 382                 }
 383         }
 384         if (length > 0)
 385                 chip->read_buf(mtd, bufpoi, length);
 386
 387         _mxc_nand_enable_hwecc(mtd, 0);
 388         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 389                         mtd->writesize + chip->ecc.prepad, page);
 390         bufpoi = buf + chip->ecc.prepad;
 391         length = mtd->oobsize - chip->ecc.prepad;
 392         for (i = 0; i < chip->ecc.steps; i++) {
 393                 toread = min_t(int, length, chip->ecc.bytes);
 394                 chip->read_buf(mtd, bufpoi, toread);
 395                 bufpoi += eccpitch;
 396                 length -= eccpitch;
 397                 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
 398         }
 399         _mxc_nand_enable_hwecc(mtd, 1);
 400         return 1;
 401 }
 402
 403 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 404                                            struct nand_chip *chip,
 405                                            uint8_t *buf,
 406                                            int page)
 407 {
 408         struct mxc_nand_host *host = chip->priv;
 409         int eccsize = chip->ecc.size;
 410         int eccbytes = chip->ecc.bytes;
 411         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 412         uint8_t *oob = chip->oob_poi;
 413         int steps, size;
 414         int n;
 415
 416         _mxc_nand_enable_hwecc(mtd, 0);
 417         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
 418
 419         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 420                 host->col_addr = n * eccsize;
 421                 chip->read_buf(mtd, buf, eccsize);
 422                 buf += eccsize;
 423
 424                 host->col_addr = mtd->writesize + n * eccpitch;
 425                 if (chip->ecc.prepad) {
 426                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 427                         oob += chip->ecc.prepad;
 428                 }
 429
 430                 chip->read_buf(mtd, oob, eccbytes);
 431                 oob += eccbytes;
 432
 433                 if (chip->ecc.postpad) {
 434                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 435                         oob += chip->ecc.postpad;
 436                 }
 437         }
 438
 439         size = mtd->oobsize - (oob - chip->oob_poi);
 440         if (size)
 441                 chip->read_buf(mtd, oob, size);
 442         _mxc_nand_enable_hwecc(mtd, 1);
 443
 444         return 0;
 445 }
 446
 447 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 448                                        struct nand_chip *chip,
 449                                        uint8_t *buf,
 450                                        int page)
 451 {
 452         struct mxc_nand_host *host = chip->priv;
 453         int n, eccsize = chip->ecc.size;
 454         int eccbytes = chip->ecc.bytes;
 455         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 456         int eccsteps = chip->ecc.steps;
 457         uint8_t *p = buf;
 458         uint8_t *oob = chip->oob_poi;
 459
 460         MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
 461               host->page_addr, buf, oob);
 462
 463         /* first read the data area and the available portion of OOB */
 464         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 465                 int stat;
 466
 467                 host->col_addr = n * eccsize;
 468
 469                 chip->read_buf(mtd, p, eccsize);
 470
 471                 host->col_addr = mtd->writesize + n * eccpitch;
 472
 473                 if (chip->ecc.prepad) {
 474                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 475                         oob += chip->ecc.prepad;
 476                 }
 477
 478                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 479
 480                 if (stat < 0)
 481                         mtd->ecc_stats.failed++;
 482                 else
 483                         mtd->ecc_stats.corrected += stat;
 484                 oob += eccbytes;
 485
 486                 if (chip->ecc.postpad) {
 487                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 488                         oob += chip->ecc.postpad;
 489                 }
 490         }
 491
 492         /* Calculate remaining oob bytes */
 493         n = mtd->oobsize - (oob - chip->oob_poi);
 494         if (n)
 495                 chip->read_buf(mtd, oob, n);
 496
 497         /* Then switch ECC off and read the OOB area to get the ECC code */
 498         _mxc_nand_enable_hwecc(mtd, 0);
 499         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
 500         eccsteps = chip->ecc.steps;
 501         oob = chip->oob_poi + chip->ecc.prepad;
 502         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 503                 host->col_addr = mtd->writesize +
 504                                  n * eccpitch +
 505                                  chip->ecc.prepad;
 506                 chip->read_buf(mtd, oob, eccbytes);
 507                 oob += eccbytes + chip->ecc.postpad;
 508         }
 509         _mxc_nand_enable_hwecc(mtd, 1);
 510         return 0;
 511 }
 512
 513 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 514                                        struct nand_chip *chip, int page)
 515 {
 516         struct mxc_nand_host *host = chip->priv;
 517         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 518         int length = mtd->oobsize;
 519         int i, len, status, steps = chip->ecc.steps;
 520         const uint8_t *bufpoi = chip->oob_poi;
 521
 522         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 523         for (i = 0; i < steps; i++) {
 524                 len = min_t(int, length, eccpitch);
 525
 526                 chip->write_buf(mtd, bufpoi, len);
 527                 bufpoi += len;
 528                 length -= len;
 529                 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
 530         }
 531         if (length > 0)
 532                 chip->write_buf(mtd, bufpoi, length);
 533
 534         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 535         status = chip->waitfunc(mtd, chip);
 536         return status & NAND_STATUS_FAIL ? -EIO : 0;
 537 }
 538
 539 static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 540                                              struct nand_chip *chip,
 541                                              const uint8_t *buf)
 542 {
 543         struct mxc_nand_host *host = chip->priv;
 544         int eccsize = chip->ecc.size;
 545         int eccbytes = chip->ecc.bytes;
 546         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 547         uint8_t *oob = chip->oob_poi;
 548         int steps, size;
 549         int n;
 550
 551         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 552                 host->col_addr = n * eccsize;
 553                 chip->write_buf(mtd, buf, eccsize);
 554                 buf += eccsize;
 555
 556                 host->col_addr = mtd->writesize + n * eccpitch;
 557
 558                 if (chip->ecc.prepad) {
 559                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 560                         oob += chip->ecc.prepad;
 561                 }
 562
 563                 host->col_addr += eccbytes;
 564                 oob += eccbytes;
 565
 566                 if (chip->ecc.postpad) {
 567                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 568                         oob += chip->ecc.postpad;
 569                 }
 570         }
 571
 572         size = mtd->oobsize - (oob - chip->oob_poi);
 573         if (size)
 574                 chip->write_buf(mtd, oob, size);
 575 }
 576
 577 static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 578                                          struct nand_chip *chip,
 579                                          const uint8_t *buf)
 580 {
 581         struct mxc_nand_host *host = chip->priv;
 582         int i, n, eccsize = chip->ecc.size;
 583         int eccbytes = chip->ecc.bytes;
 584         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 585         int eccsteps = chip->ecc.steps;
 586         const uint8_t *p = buf;
 587         uint8_t *oob = chip->oob_poi;
 588
 589         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 590
 591         for (i = n = 0;
 592              eccsteps;
 593              n++, eccsteps--, i += eccbytes, p += eccsize) {
 594                 host->col_addr = n * eccsize;
 595
 596                 chip->write_buf(mtd, p, eccsize);
 597
 598                 host->col_addr = mtd->writesize + n * eccpitch;
 599
 600                 if (chip->ecc.prepad) {
 601                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 602                         oob += chip->ecc.prepad;
 603                 }
 604
 605                 chip->write_buf(mtd, oob, eccbytes);
 606                 oob += eccbytes;
 607
 608                 if (chip->ecc.postpad) {
 609                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 610                         oob += chip->ecc.postpad;
 611                 }
 612         }
 613
 614         /* Calculate remaining oob bytes */
 615         i = mtd->oobsize - (oob - chip->oob_poi);
 616         if (i)
 617                 chip->write_buf(mtd, oob, i);
 618 }
 619
 620 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 621                                  u_char *read_ecc, u_char *calc_ecc)
 622 {
 623         struct nand_chip *nand_chip = mtd->priv;
 624         struct mxc_nand_host *host = nand_chip->priv;
 625         uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 626         int subpages = mtd->writesize / nand_chip->subpagesize;
 627         int pg2blk_shift = nand_chip->phys_erase_shift -
 628                            nand_chip->page_shift;
 629
 630         do {
 631                 if ((ecc_status & 0xf) > 4) {
 632                         static int last_bad = -1;
 633
 634                         if (last_bad != host->page_addr >> pg2blk_shift) {
 635                                 last_bad = host->page_addr >> pg2blk_shift;
 636                                 printk(KERN_DEBUG
 637                                        "MXC_NAND: HWECC uncorrectable ECC error"
 638                                        " in block %u page %u subpage %d\n",
 639                                        last_bad, host->page_addr,
 640                                        mtd->writesize / nand_chip->subpagesize
 641                                             - subpages);
 642                         }
 643                         return -1;
 644                 }
 645                 ecc_status >>= 4;
 646                 subpages--;
 647         } while (subpages > 0);
 648
 649         return 0;
 650 }
 651 #else
 652 #define mxc_nand_read_page_syndrome NULL
 653 #define mxc_nand_read_page_raw_syndrome NULL
 654 #define mxc_nand_read_oob_syndrome NULL
 655 #define mxc_nand_write_page_syndrome NULL
 656 #define mxc_nand_write_page_raw_syndrome NULL
 657 #define mxc_nand_write_oob_syndrome NULL
 658
 659 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 660                                  u_char *read_ecc, u_char *calc_ecc)
 661 {
 662         struct nand_chip *nand_chip = mtd->priv;
 663         struct mxc_nand_host *host = nand_chip->priv;
 664
 665         /*
 666          * 1-Bit errors are automatically corrected in HW.  No need for
 667          * additional correction.  2-Bit errors cannot be corrected by
 668          * HW ECC, so we need to return failure
 669          */
 670         uint16_t ecc_status = readw(&host->regs->ecc_status_result);
 671
 672         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 673                 MTDDEBUG(MTD_DEBUG_LEVEL0,
 674                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 675                 return -1;
 676         }
 677
 678         return 0;
 679 }
 680 #endif
 681
 682 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 683                                   u_char *ecc_code)
 684 {
 685         return 0;
 686 }
 687 #endif
 688
 689 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 690 {
 691         struct nand_chip *nand_chip = mtd->priv;
 692         struct mxc_nand_host *host = nand_chip->priv;
 693         uint8_t ret = 0;
 694         uint16_t col;
 695         uint16_t __iomem *main_buf =
 696                 (uint16_t __iomem *)host->regs->main_area[0];
 697         uint16_t __iomem *spare_buf =
 698                 (uint16_t __iomem *)host->regs->spare_area[0];
 699         union {
 700                 uint16_t word;
 701                 uint8_t bytes[2];
 702         } nfc_word;
 703
 704         /* Check for status request */
 705         if (host->status_request)
 706                 return get_dev_status(host) & 0xFF;
 707
 708         /* Get column for 16-bit access */
 709         col = host->col_addr >> 1;
 710
 711         /* If we are accessing the spare region */
 712         if (host->spare_only)
 713                 nfc_word.word = readw(&spare_buf[col]);
 714         else
 715                 nfc_word.word = readw(&main_buf[col]);
 716
 717         /* Pick upper/lower byte of word from RAM buffer */
 718         ret = nfc_word.bytes[host->col_addr & 0x1];
 719
 720         /* Update saved column address */
 721         if (nand_chip->options & NAND_BUSWIDTH_16)
 722                 host->col_addr += 2;
 723         else
 724                 host->col_addr++;
 725
 726         return ret;
 727 }
 728
 729 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 730 {
 731         struct nand_chip *nand_chip = mtd->priv;
 732         struct mxc_nand_host *host = nand_chip->priv;
 733         uint16_t col, ret;
 734         uint16_t __iomem *p;
 735
 736         MTDDEBUG(MTD_DEBUG_LEVEL3,
 737               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 738
 739         col = host->col_addr;
 740         /* Adjust saved column address */
 741         if (col < mtd->writesize && host->spare_only)
 742                 col += mtd->writesize;
 743
 744         if (col < mtd->writesize) {
 745                 p = (uint16_t __iomem *)(host->regs->main_area[0] +
 746                                 (col >> 1));
 747         } else {
 748                 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 749                                 ((col - mtd->writesize) >> 1));
 750         }
 751
 752         if (col & 1) {
 753                 union {
 754                         uint16_t word;
 755                         uint8_t bytes[2];
 756                 } nfc_word[3];
 757
 758                 nfc_word[0].word = readw(p);
 759                 nfc_word[1].word = readw(p + 1);
 760
 761                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 762                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 763
 764                 ret = nfc_word[2].word;
 765         } else {
 766                 ret = readw(p);
 767         }
 768
 769         /* Update saved column address */
 770         host->col_addr = col + 2;
 771
 772         return ret;
 773 }
 774
 775 /*
 776  * Write data of length len to buffer buf. The data to be
 777  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 778  * Operation by the NFC, the data is written to NAND Flash
 779  */
 780 static void mxc_nand_write_buf(struct mtd_info *mtd,
 781                                 const u_char *buf, int len)
 782 {
 783         struct nand_chip *nand_chip = mtd->priv;
 784         struct mxc_nand_host *host = nand_chip->priv;
 785         int n, col, i = 0;
 786
 787         MTDDEBUG(MTD_DEBUG_LEVEL3,
 788               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 789               len);
 790
 791         col = host->col_addr;
 792
 793         /* Adjust saved column address */
 794         if (col < mtd->writesize && host->spare_only)
 795                 col += mtd->writesize;
 796
 797         n = mtd->writesize + mtd->oobsize - col;
 798         n = min(len, n);
 799
 800         MTDDEBUG(MTD_DEBUG_LEVEL3,
 801               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 802
 803         while (n > 0) {
 804                 void __iomem *p;
 805
 806                 if (col < mtd->writesize) {
 807                         p = host->regs->main_area[0] + (col & ~3);
 808                 } else {
 809                         p = host->regs->spare_area[0] -
 810                                                 mtd->writesize + (col & ~3);
 811                 }
 812
 813                 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 814                       __LINE__, p);
 815
 816                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 817                         union {
 818                                 uint32_t word;
 819                                 uint8_t bytes[4];
 820                         } nfc_word;
 821
 822                         nfc_word.word = readl(p);
 823                         nfc_word.bytes[col & 3] = buf[i++];
 824                         n--;
 825                         col++;
 826
 827                         writel(nfc_word.word, p);
 828                 } else {
 829                         int m = mtd->writesize - col;
 830
 831                         if (col >= mtd->writesize)
 832                                 m += mtd->oobsize;
 833
 834                         m = min(n, m) & ~3;
 835
 836                         MTDDEBUG(MTD_DEBUG_LEVEL3,
 837                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 838                               __func__,  __LINE__, n, m, i, col);
 839
 840                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 841                         col += m;
 842                         i += m;
 843                         n -= m;
 844                 }
 845         }
 846         /* Update saved column address */
 847         host->col_addr = col;
 848 }
 849
 850 /*
 851  * Read the data buffer from the NAND Flash. To read the data from NAND
 852  * Flash first the data output cycle is initiated by the NFC, which copies
 853  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 854  */
 855 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 856 {
 857         struct nand_chip *nand_chip = mtd->priv;
 858         struct mxc_nand_host *host = nand_chip->priv;
 859         int n, col, i = 0;
 860
 861         MTDDEBUG(MTD_DEBUG_LEVEL3,
 862               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 863
 864         col = host->col_addr;
 865
 866         /* Adjust saved column address */
 867         if (col < mtd->writesize && host->spare_only)
 868                 col += mtd->writesize;
 869
 870         n = mtd->writesize + mtd->oobsize - col;
 871         n = min(len, n);
 872
 873         while (n > 0) {
 874                 void __iomem *p;
 875
 876                 if (col < mtd->writesize) {
 877                         p = host->regs->main_area[0] + (col & ~3);
 878                 } else {
 879                         p = host->regs->spare_area[0] -
 880                                         mtd->writesize + (col & ~3);
 881                 }
 882
 883                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 884                         union {
 885                                 uint32_t word;
 886                                 uint8_t bytes[4];
 887                         } nfc_word;
 888
 889                         nfc_word.word = readl(p);
 890                         buf[i++] = nfc_word.bytes[col & 3];
 891                         n--;
 892                         col++;
 893                 } else {
 894                         int m = mtd->writesize - col;
 895
 896                         if (col >= mtd->writesize)
 897                                 m += mtd->oobsize;
 898
 899                         m = min(n, m) & ~3;
 900                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 901
 902                         col += m;
 903                         i += m;
 904                         n -= m;
 905                 }
 906         }
 907         /* Update saved column address */
 908         host->col_addr = col;
 909 }
 910
 911 /*
 912  * Used by the upper layer to verify the data in NAND Flash
 913  * with the data in the buf.
 914  */
 915 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 916                                 const u_char *buf, int len)
 917 {
 918         u_char tmp[256];
 919         uint bsize;
 920
 921         while (len) {
 922                 bsize = min(len, 256);
 923                 mxc_nand_read_buf(mtd, tmp, bsize);
 924
 925                 if (memcmp(buf, tmp, bsize))
 926                         return 1;
 927
 928                 buf += bsize;
 929                 len -= bsize;
 930         }
 931
 932         return 0;
 933 }
 934
 935 /*
 936  * This function is used by upper layer for select and
 937  * deselect of the NAND chip
 938  */
 939 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 940 {
 941         struct nand_chip *nand_chip = mtd->priv;
 942         struct mxc_nand_host *host = nand_chip->priv;
 943
 944         switch (chip) {
 945         case -1:
 946                 /* TODO: Disable the NFC clock */
 947                 if (host->clk_act)
 948                         host->clk_act = 0;
 949                 break;
 950         case 0:
 951                 /* TODO: Enable the NFC clock */
 952                 if (!host->clk_act)
 953                         host->clk_act = 1;
 954                 break;
 955
 956         default:
 957                 break;
 958         }
 959 }
 960
 961 /*
 962  * Used by the upper layer to write command to NAND Flash for
 963  * different operations to be carried out on NAND Flash
 964  */
 965 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 966                                 int column, int page_addr)
 967 {
 968         struct nand_chip *nand_chip = mtd->priv;
 969         struct mxc_nand_host *host = nand_chip->priv;
 970
 971         MTDDEBUG(MTD_DEBUG_LEVEL3,
 972               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 973               command, column, page_addr);
 974
 975         /* Reset command state information */
 976         host->status_request = false;
 977
 978         /* Command pre-processing step */
 979         switch (command) {
 980
 981         case NAND_CMD_STATUS:
 982                 host->col_addr = 0;
 983                 host->status_request = true;
 984                 break;
 985
 986         case NAND_CMD_READ0:
 987                 host->page_addr = page_addr;
 988                 host->col_addr = column;
 989                 host->spare_only = false;
 990                 break;
 991
 992         case NAND_CMD_READOOB:
 993                 host->col_addr = column;
 994                 host->spare_only = true;
 995                 if (host->pagesize_2k)
 996                         command = NAND_CMD_READ0; /* only READ0 is valid */
 997                 break;
 998
 999         case NAND_CMD_SEQIN:
1000                 if (column >= mtd->writesize) {
1001                         /*
1002                          * before sending SEQIN command for partial write,
1003                          * we need read one page out. FSL NFC does not support
1004                          * partial write. It always sends out 512+ecc+512+ecc
1005                          * for large page nand flash. But for small page nand
1006                          * flash, it does support SPARE ONLY operation.
1007                          */
1008                         if (host->pagesize_2k) {
1009                                 /* call ourself to read a page */
1010                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1011                                                 page_addr);
1012                         }
1013
1014                         host->col_addr = column - mtd->writesize;
1015                         host->spare_only = true;
1016
1017                         /* Set program pointer to spare region */
1018                         if (!host->pagesize_2k)
1019                                 send_cmd(host, NAND_CMD_READOOB);
1020                 } else {
1021                         host->spare_only = false;
1022                         host->col_addr = column;
1023
1024                         /* Set program pointer to page start */
1025                         if (!host->pagesize_2k)
1026                                 send_cmd(host, NAND_CMD_READ0);
1027                 }
1028                 break;
1029
1030         case NAND_CMD_PAGEPROG:
1031                 send_prog_page(host, 0, host->spare_only);
1032
1033                 if (host->pagesize_2k && is_mxc_nfc_1()) {
1034                         /* data in 4 areas */
1035                         send_prog_page(host, 1, host->spare_only);
1036                         send_prog_page(host, 2, host->spare_only);
1037                         send_prog_page(host, 3, host->spare_only);
1038                 }
1039
1040                 break;
1041         }
1042
1043         /* Write out the command to the device. */
1044         send_cmd(host, command);
1045
1046         /* Write out column address, if necessary */
1047         if (column != -1) {
1048                 /*
1049                  * MXC NANDFC can only perform full page+spare or
1050                  * spare-only read/write. When the upper layers perform
1051                  * a read/write buffer operation, we will use the saved
1052                  * column address to index into the full page.
1053                  */
1054                 send_addr(host, 0);
1055                 if (host->pagesize_2k)
1056                         /* another col addr cycle for 2k page */
1057                         send_addr(host, 0);
1058         }
1059
1060         /* Write out page address, if necessary */
1061         if (page_addr != -1) {
1062                 u32 page_mask = nand_chip->pagemask;
1063                 do {
1064                         send_addr(host, page_addr & 0xFF);
1065                         page_addr >>= 8;
1066                         page_mask >>= 8;
1067                 } while (page_mask);
1068         }
1069
1070         /* Command post-processing step */
1071         switch (command) {
1072
1073         case NAND_CMD_RESET:
1074                 break;
1075
1076         case NAND_CMD_READOOB:
1077         case NAND_CMD_READ0:
1078                 if (host->pagesize_2k) {
1079                         /* send read confirm command */
1080                         send_cmd(host, NAND_CMD_READSTART);
1081                         /* read for each AREA */
1082                         send_read_page(host, 0, host->spare_only);
1083                         if (is_mxc_nfc_1()) {
1084                                 send_read_page(host, 1, host->spare_only);
1085                                 send_read_page(host, 2, host->spare_only);
1086                                 send_read_page(host, 3, host->spare_only);
1087                         }
1088                 } else {
1089                         send_read_page(host, 0, host->spare_only);
1090                 }
1091                 break;
1092
1093         case NAND_CMD_READID:
1094                 host->col_addr = 0;
1095                 send_read_id(host);
1096                 break;
1097
1098         case NAND_CMD_PAGEPROG:
1099                 break;
1100
1101         case NAND_CMD_STATUS:
1102                 break;
1103
1104         case NAND_CMD_ERASE2:
1105                 break;
1106         }
1107 }
1108
1109 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1110
1111 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1112 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1113
1114 static struct nand_bbt_descr bbt_main_descr = {
1115         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1116                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1117         .offs = 0,
1118         .len = 4,
1119         .veroffs = 4,
1120         .maxblocks = 4,
1121         .pattern = bbt_pattern,
1122 };
1123
1124 static struct nand_bbt_descr bbt_mirror_descr = {
1125         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1126                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1127         .offs = 0,
1128         .len = 4,
1129         .veroffs = 4,
1130         .maxblocks = 4,
1131         .pattern = mirror_pattern,
1132 };
1133
1134 #endif
1135
1136 int board_nand_init(struct nand_chip *this)
1137 {
1138         struct mtd_info *mtd;
1139 #ifdef MXC_NFC_V2_1
1140         uint16_t tmp;
1141 #endif
1142
1143 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1144         this->options |= NAND_USE_FLASH_BBT;
1145         this->bbt_td = &bbt_main_descr;
1146         this->bbt_md = &bbt_mirror_descr;
1147 #endif
1148
1149         /* structures must be linked */
1150         mtd = &host->mtd;
1151         mtd->priv = this;
1152         host->nand = this;
1153
1154         /* 5 us command delay time */
1155         this->chip_delay = 5;
1156
1157         this->priv = host;
1158         this->dev_ready = mxc_nand_dev_ready;
1159         this->cmdfunc = mxc_nand_command;
1160         this->select_chip = mxc_nand_select_chip;
1161         this->read_byte = mxc_nand_read_byte;
1162         this->read_word = mxc_nand_read_word;
1163         this->write_buf = mxc_nand_write_buf;
1164         this->read_buf = mxc_nand_read_buf;
1165         this->verify_buf = mxc_nand_verify_buf;
1166
1167         host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1168         host->clk_act = 1;
1169
1170 #ifdef CONFIG_MXC_NAND_HWECC
1171         this->ecc.calculate = mxc_nand_calculate_ecc;
1172         this->ecc.hwctl = mxc_nand_enable_hwecc;
1173         this->ecc.correct = mxc_nand_correct_data;
1174         if (is_mxc_nfc_21()) {
1175                 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1176                 this->ecc.read_page = mxc_nand_read_page_syndrome;
1177                 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1178                 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1179                 this->ecc.write_page = mxc_nand_write_page_syndrome;
1180                 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1181                 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1182                 this->ecc.bytes = 9;
1183                 this->ecc.prepad = 7;
1184         } else {
1185                 this->ecc.mode = NAND_ECC_HW;
1186         }
1187
1188         host->pagesize_2k = 0;
1189
1190         this->ecc.size = 512;
1191         _mxc_nand_enable_hwecc(mtd, 1);
1192 #else
1193         this->ecc.layout = &nand_soft_eccoob;
1194         this->ecc.mode = NAND_ECC_SOFT;
1195         _mxc_nand_enable_hwecc(mtd, 0);
1196 #endif
1197         /* Reset NAND */
1198         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1199
1200         /* NAND bus width determines access functions used by upper layer */
1201         if (is_16bit_nand())
1202                 this->options |= NAND_BUSWIDTH_16;
1203
1204 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1205         host->pagesize_2k = 1;
1206         this->ecc.layout = &nand_hw_eccoob2k;
1207 #else
1208         host->pagesize_2k = 0;
1209         this->ecc.layout = &nand_hw_eccoob;
1210 #endif
1211
1212 #ifdef MXC_NFC_V2_1
1213         tmp = readw(&host->regs->config1);
1214         tmp |= NFC_ONE_CYCLE;
1215         tmp |= NFC_4_8N_ECC;
1216         writew(tmp, &host->regs->config1);
1217         if (host->pagesize_2k)
1218                 writew(64/2, &host->regs->spare_area_size);
1219         else
1220                 writew(16/2, &host->regs->spare_area_size);
1221 #endif
1222
1223         /*
1224          * preset operation
1225          * Unlock the internal RAM Buffer
1226          */
1227         writew(0x2, &host->regs->config);
1228
1229         /* Blocks to be unlocked */
1230         writew(0x0, &host->regs->unlockstart_blkaddr);
1231         /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1232          * unlockend_blkaddr, but the magic 0x4000 does not always work
1233          * when writing more than some 32 megabytes (on 2k page nands)
1234          * However 0xFFFF doesn't seem to have this kind
1235          * of limitation (tried it back and forth several times).
1236          * The linux kernel driver sets this to 0xFFFF for the v2 controller
1237          * only, but probably this was not tested there for v1.
1238          * The very same limitation seems to apply to this kernel driver.
1239          * This might be NAND chip specific and the i.MX31 datasheet is
1240          * extremely vague about the semantics of this register.
1241          */
1242         writew(0xFFFF, &host->regs->unlockend_blkaddr);
1243
1244         /* Unlock Block Command for given address range */
1245         writew(0x4, &host->regs->wrprot);
1246
1247         return 0;
1248 }