drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *
   8  *      Additional technical information is available on
   9  *      http://www.linux-mtd.infradead.org/doc/nand.html
  10  *
  11  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  12  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  13  *
  14  *  Credits:
  15  *      David Woodhouse for adding multichip support
  16  *
  17  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  18  *      rework for 2K page size chips
  19  *
  20  *  TODO:
  21  *      Enable cached programming for 2k page size chips
  22  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  23  *      if we have HW ECC support.
  24  *      BBT table is not serialized, has to be fixed
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License version 2 as
  28  * published by the Free Software Foundation.
  29  *
  30  */
  31
  32 #ifndef __UBOOT__
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51 #else
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53 #include <common.h>
  54 #include <malloc.h>
  55 #include <watchdog.h>
  56 #include <linux/err.h>
  57 #include <linux/compat.h>
  58 #include <linux/mtd/mtd.h>
  59 #include <linux/mtd/nand.h>
  60 #include <linux/mtd/nand_ecc.h>
  61 #include <linux/mtd/nand_bch.h>
  62 #ifdef CONFIG_MTD_PARTITIONS
  63 #include <linux/mtd/partitions.h>
  64 #endif
  65 #include <asm/io.h>
  66 #include <asm/errno.h>
  67
  68 /*
  69  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  70  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  71  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  72  * which is greater than (max NAND reset time / NAND status read time).
  73  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  74  */
  75 #ifndef CONFIG_SYS_NAND_RESET_CNT
  76 #define CONFIG_SYS_NAND_RESET_CNT 200000
  77 #endif
  78
  79 static bool is_module_text_address(unsigned long addr) {return 0;}
  80 #endif
  81
  82 /* Define default oob placement schemes for large and small page devices */
  83 static struct nand_ecclayout nand_oob_8 = {
  84         .eccbytes = 3,
  85         .eccpos = {0, 1, 2},
  86         .oobfree = {
  87                 {.offset = 3,
  88                  .length = 2},
  89                 {.offset = 6,
  90                  .length = 2} }
  91 };
  92
  93 static struct nand_ecclayout nand_oob_16 = {
  94         .eccbytes = 6,
  95         .eccpos = {0, 1, 2, 3, 6, 7},
  96         .oobfree = {
  97                 {.offset = 8,
  98                  . length = 8} }
  99 };
 100
 101 static struct nand_ecclayout nand_oob_64 = {
 102         .eccbytes = 24,
 103         .eccpos = {
 104                    40, 41, 42, 43, 44, 45, 46, 47,
 105                    48, 49, 50, 51, 52, 53, 54, 55,
 106                    56, 57, 58, 59, 60, 61, 62, 63},
 107         .oobfree = {
 108                 {.offset = 2,
 109                  .length = 38} }
 110 };
 111
 112 static struct nand_ecclayout nand_oob_128 = {
 113         .eccbytes = 48,
 114         .eccpos = {
 115                    80, 81, 82, 83, 84, 85, 86, 87,
 116                    88, 89, 90, 91, 92, 93, 94, 95,
 117                    96, 97, 98, 99, 100, 101, 102, 103,
 118                    104, 105, 106, 107, 108, 109, 110, 111,
 119                    112, 113, 114, 115, 116, 117, 118, 119,
 120                    120, 121, 122, 123, 124, 125, 126, 127},
 121         .oobfree = {
 122                 {.offset = 2,
 123                  .length = 78} }
 124 };
 125
 126 static int nand_get_device(struct mtd_info *mtd, int new_state);
 127
 128 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 129                              struct mtd_oob_ops *ops);
 130
 131 /*
 132  * For devices which display every fart in the system on a separate LED. Is
 133  * compiled away when LED support is disabled.
 134  */
 135 DEFINE_LED_TRIGGER(nand_led_trigger);
 136
 137 static int check_offs_len(struct mtd_info *mtd,
 138                                         loff_t ofs, uint64_t len)
 139 {
 140         struct nand_chip *chip = mtd->priv;
 141         int ret = 0;
 142
 143         /* Start address must align on block boundary */
 144         if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
 145                 pr_debug("%s: unaligned address\n", __func__);
 146                 ret = -EINVAL;
 147         }
 148
 149         /* Length must align on block boundary */
 150         if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
 151                 pr_debug("%s: length not block aligned\n", __func__);
 152                 ret = -EINVAL;
 153         }
 154
 155         return ret;
 156 }
 157
 158 /**
 159  * nand_release_device - [GENERIC] release chip
 160  * @mtd: MTD device structure
 161  *
 162  * Release chip lock and wake up anyone waiting on the device.
 163  */
 164 static void nand_release_device(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *chip = mtd->priv;
 167
 168 #ifndef __UBOOT__
 169         /* Release the controller and the chip */
 170         spin_lock(&chip->controller->lock);
 171         chip->controller->active = NULL;
 172         chip->state = FL_READY;
 173         wake_up(&chip->controller->wq);
 174         spin_unlock(&chip->controller->lock);
 175 #else
 176         /* De-select the NAND device */
 177         chip->select_chip(mtd, -1);
 178 #endif
 179 }
 180
 181 /**
 182  * nand_read_byte - [DEFAULT] read one byte from the chip
 183  * @mtd: MTD device structure
 184  *
 185  * Default read function for 8bit buswidth
 186  */
 187 #ifndef __UBOOT__
 188 static uint8_t nand_read_byte(struct mtd_info *mtd)
 189 #else
 190 uint8_t nand_read_byte(struct mtd_info *mtd)
 191 #endif
 192 {
 193         struct nand_chip *chip = mtd->priv;
 194         return readb(chip->IO_ADDR_R);
 195 }
 196
 197 /**
 198  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 199  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 200  * @mtd: MTD device structure
 201  *
 202  * Default read function for 16bit buswidth with endianness conversion.
 203  *
 204  */
 205 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 206 {
 207         struct nand_chip *chip = mtd->priv;
 208         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 209 }
 210
 211 /**
 212  * nand_read_word - [DEFAULT] read one word from the chip
 213  * @mtd: MTD device structure
 214  *
 215  * Default read function for 16bit buswidth without endianness conversion.
 216  */
 217 static u16 nand_read_word(struct mtd_info *mtd)
 218 {
 219         struct nand_chip *chip = mtd->priv;
 220         return readw(chip->IO_ADDR_R);
 221 }
 222
 223 /**
 224  * nand_select_chip - [DEFAULT] control CE line
 225  * @mtd: MTD device structure
 226  * @chipnr: chipnumber to select, -1 for deselect
 227  *
 228  * Default select function for 1 chip devices.
 229  */
 230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 231 {
 232         struct nand_chip *chip = mtd->priv;
 233
 234         switch (chipnr) {
 235         case -1:
 236                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 237                 break;
 238         case 0:
 239                 break;
 240
 241         default:
 242                 BUG();
 243         }
 244 }
 245
 246 /**
 247  * nand_write_byte - [DEFAULT] write single byte to chip
 248  * @mtd: MTD device structure
 249  * @byte: value to write
 250  *
 251  * Default function to write a byte to I/O[7:0]
 252  */
 253 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
 254 {
 255         struct nand_chip *chip = mtd->priv;
 256
 257         chip->write_buf(mtd, &byte, 1);
 258 }
 259
 260 /**
 261  * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 262  * @mtd: MTD device structure
 263  * @byte: value to write
 264  *
 265  * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 266  */
 267 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 268 {
 269         struct nand_chip *chip = mtd->priv;
 270         uint16_t word = byte;
 271
 272         /*
 273          * It's not entirely clear what should happen to I/O[15:8] when writing
 274          * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
 275          *
 276          *    When the host supports a 16-bit bus width, only data is
 277          *    transferred at the 16-bit width. All address and command line
 278          *    transfers shall use only the lower 8-bits of the data bus. During
 279          *    command transfers, the host may place any value on the upper
 280          *    8-bits of the data bus. During address transfers, the host shall
 281          *    set the upper 8-bits of the data bus to 00h.
 282          *
 283          * One user of the write_byte callback is nand_onfi_set_features. The
 284          * four parameters are specified to be written to I/O[7:0], but this is
 285          * neither an address nor a command transfer. Let's assume a 0 on the
 286          * upper I/O lines is OK.
 287          */
 288         chip->write_buf(mtd, (uint8_t *)&word, 2);
 289 }
 290
 291 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
 292 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
 293 {
 294         int i;
 295
 296         for (i = 0; i < len; i++)
 297                 writeb(buf[i], addr);
 298 }
 299 static void ioread8_rep(void *addr, uint8_t *buf, int len)
 300 {
 301         int i;
 302
 303         for (i = 0; i < len; i++)
 304                 buf[i] = readb(addr);
 305 }
 306
 307 static void ioread16_rep(void *addr, void *buf, int len)
 308 {
 309         int i;
 310         u16 *p = (u16 *) buf;
 311
 312         for (i = 0; i < len; i++)
 313                 p[i] = readw(addr);
 314 }
 315
 316 static void iowrite16_rep(void *addr, void *buf, int len)
 317 {
 318         int i;
 319         u16 *p = (u16 *) buf;
 320
 321         for (i = 0; i < len; i++)
 322                 writew(p[i], addr);
 323 }
 324 #endif
 325
 326 /**
 327  * nand_write_buf - [DEFAULT] write buffer to chip
 328  * @mtd: MTD device structure
 329  * @buf: data buffer
 330  * @len: number of bytes to write
 331  *
 332  * Default write function for 8bit buswidth.
 333  */
 334 #ifndef __UBOOT__
 335 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 336 #else
 337 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 338 #endif
 339 {
 340         struct nand_chip *chip = mtd->priv;
 341
 342         iowrite8_rep(chip->IO_ADDR_W, buf, len);
 343 }
 344
 345 /**
 346  * nand_read_buf - [DEFAULT] read chip data into buffer
 347  * @mtd: MTD device structure
 348  * @buf: buffer to store date
 349  * @len: number of bytes to read
 350  *
 351  * Default read function for 8bit buswidth.
 352  */
 353 #ifndef __UBOOT__
 354 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 355 #else
 356 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 357 #endif
 358 {
 359         struct nand_chip *chip = mtd->priv;
 360
 361         ioread8_rep(chip->IO_ADDR_R, buf, len);
 362 }
 363
 364 #ifdef __UBOOT__
 365 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 366 /**
 367  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 368  * @mtd: MTD device structure
 369  * @buf: buffer containing the data to compare
 370  * @len: number of bytes to compare
 371  *
 372  * Default verify function for 8bit buswidth.
 373  */
 374 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 375 {
 376         int i;
 377         struct nand_chip *chip = mtd->priv;
 378
 379         for (i = 0; i < len; i++)
 380                 if (buf[i] != readb(chip->IO_ADDR_R))
 381                         return -EFAULT;
 382         return 0;
 383 }
 384
 385 /**
 386  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 387  * @mtd: MTD device structure
 388  * @buf: buffer containing the data to compare
 389  * @len: number of bytes to compare
 390  *
 391  * Default verify function for 16bit buswidth.
 392  */
 393 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 394 {
 395         int i;
 396         struct nand_chip *chip = mtd->priv;
 397         u16 *p = (u16 *) buf;
 398         len >>= 1;
 399
 400         for (i = 0; i < len; i++)
 401                 if (p[i] != readw(chip->IO_ADDR_R))
 402                         return -EFAULT;
 403
 404         return 0;
 405 }
 406 #endif
 407 #endif
 408
 409 /**
 410  * nand_write_buf16 - [DEFAULT] write buffer to chip
 411  * @mtd: MTD device structure
 412  * @buf: data buffer
 413  * @len: number of bytes to write
 414  *
 415  * Default write function for 16bit buswidth.
 416  */
 417 #ifndef __UBOOT__
 418 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 419 #else
 420 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 421 #endif
 422 {
 423         struct nand_chip *chip = mtd->priv;
 424         u16 *p = (u16 *) buf;
 425
 426         iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
 427 }
 428
 429 /**
 430  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 431  * @mtd: MTD device structure
 432  * @buf: buffer to store date
 433  * @len: number of bytes to read
 434  *
 435  * Default read function for 16bit buswidth.
 436  */
 437 #ifndef __UBOOT__
 438 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 439 #else
 440 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 441 #endif
 442 {
 443         struct nand_chip *chip = mtd->priv;
 444         u16 *p = (u16 *) buf;
 445
 446         ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
 447 }
 448
 449 /**
 450  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 451  * @mtd: MTD device structure
 452  * @ofs: offset from device start
 453  * @getchip: 0, if the chip is already selected
 454  *
 455  * Check, if the block is bad.
 456  */
 457 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 458 {
 459         int page, chipnr, res = 0, i = 0;
 460         struct nand_chip *chip = mtd->priv;
 461         u16 bad;
 462
 463         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 464                 ofs += mtd->erasesize - mtd->writesize;
 465
 466         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 467
 468         if (getchip) {
 469                 chipnr = (int)(ofs >> chip->chip_shift);
 470
 471                 nand_get_device(mtd, FL_READING);
 472
 473                 /* Select the NAND device */
 474                 chip->select_chip(mtd, chipnr);
 475         }
 476
 477         do {
 478                 if (chip->options & NAND_BUSWIDTH_16) {
 479                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 480                                         chip->badblockpos & 0xFE, page);
 481                         bad = cpu_to_le16(chip->read_word(mtd));
 482                         if (chip->badblockpos & 0x1)
 483                                 bad >>= 8;
 484                         else
 485                                 bad &= 0xFF;
 486                 } else {
 487                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 488                                         page);
 489                         bad = chip->read_byte(mtd);
 490                 }
 491
 492                 if (likely(chip->badblockbits == 8))
 493                         res = bad != 0xFF;
 494                 else
 495                         res = hweight8(bad) < chip->badblockbits;
 496                 ofs += mtd->writesize;
 497                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 498                 i++;
 499         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 500
 501         if (getchip) {
 502                 chip->select_chip(mtd, -1);
 503                 nand_release_device(mtd);
 504         }
 505
 506         return res;
 507 }
 508
 509 /**
 510  * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
 511  * @mtd: MTD device structure
 512  * @ofs: offset from device start
 513  *
 514  * This is the default implementation, which can be overridden by a hardware
 515  * specific driver. It provides the details for writing a bad block marker to a
 516  * block.
 517  */
 518 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 519 {
 520         struct nand_chip *chip = mtd->priv;
 521         struct mtd_oob_ops ops;
 522         uint8_t buf[2] = { 0, 0 };
 523         int ret = 0, res, i = 0;
 524
 525         ops.datbuf = NULL;
 526         ops.oobbuf = buf;
 527         ops.ooboffs = chip->badblockpos;
 528         if (chip->options & NAND_BUSWIDTH_16) {
 529                 ops.ooboffs &= ~0x01;
 530                 ops.len = ops.ooblen = 2;
 531         } else {
 532                 ops.len = ops.ooblen = 1;
 533         }
 534         ops.mode = MTD_OPS_PLACE_OOB;
 535
 536         /* Write to first/last page(s) if necessary */
 537         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 538                 ofs += mtd->erasesize - mtd->writesize;
 539         do {
 540                 res = nand_do_write_oob(mtd, ofs, &ops);
 541                 if (!ret)
 542                         ret = res;
 543
 544                 i++;
 545                 ofs += mtd->writesize;
 546         } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 547
 548         return ret;
 549 }
 550
 551 /**
 552  * nand_block_markbad_lowlevel - mark a block bad
 553  * @mtd: MTD device structure
 554  * @ofs: offset from device start
 555  *
 556  * This function performs the generic NAND bad block marking steps (i.e., bad
 557  * block table(s) and/or marker(s)). We only allow the hardware driver to
 558  * specify how to write bad block markers to OOB (chip->block_markbad).
 559  *
 560  * We try operations in the following order:
 561  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 562  *  (2) write bad block marker to OOB area of affected block (unless flag
 563  *      NAND_BBT_NO_OOB_BBM is present)
 564  *  (3) update the BBT
 565  * Note that we retain the first error encountered in (2) or (3), finish the
 566  * procedures, and dump the error in the end.
 567 */
 568 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 569 {
 570         struct nand_chip *chip = mtd->priv;
 571         int res, ret = 0;
 572
 573         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
 574                 struct erase_info einfo;
 575
 576                 /* Attempt erase before marking OOB */
 577                 memset(&einfo, 0, sizeof(einfo));
 578                 einfo.mtd = mtd;
 579                 einfo.addr = ofs;
 580                 einfo.len = 1ULL << chip->phys_erase_shift;
 581                 nand_erase_nand(mtd, &einfo, 0);
 582
 583                 /* Write bad block marker to OOB */
 584                 nand_get_device(mtd, FL_WRITING);
 585                 ret = chip->block_markbad(mtd, ofs);
 586                 nand_release_device(mtd);
 587         }
 588
 589         /* Mark block bad in BBT */
 590         if (chip->bbt) {
 591                 res = nand_markbad_bbt(mtd, ofs);
 592                 if (!ret)
 593                         ret = res;
 594         }
 595
 596         if (!ret)
 597                 mtd->ecc_stats.badblocks++;
 598
 599         return ret;
 600 }
 601
 602 /**
 603  * nand_check_wp - [GENERIC] check if the chip is write protected
 604  * @mtd: MTD device structure
 605  *
 606  * Check, if the device is write protected. The function expects, that the
 607  * device is already selected.
 608  */
 609 static int nand_check_wp(struct mtd_info *mtd)
 610 {
 611         struct nand_chip *chip = mtd->priv;
 612
 613         /* Broken xD cards report WP despite being writable */
 614         if (chip->options & NAND_BROKEN_XD)
 615                 return 0;
 616
 617         /* Check the WP bit */
 618         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 619         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 620 }
 621
 622 /**
 623  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 624  * @mtd: MTD device structure
 625  * @ofs: offset from device start
 626  * @getchip: 0, if the chip is already selected
 627  * @allowbbt: 1, if its allowed to access the bbt area
 628  *
 629  * Check, if the block is bad. Either by reading the bad block table or
 630  * calling of the scan function.
 631  */
 632 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 633                                int allowbbt)
 634 {
 635         struct nand_chip *chip = mtd->priv;
 636
 637         if (!(chip->options & NAND_BBT_SCANNED)) {
 638                 chip->scan_bbt(mtd);
 639                 chip->options |= NAND_BBT_SCANNED;
 640         }
 641
 642         if (!chip->bbt)
 643                 return chip->block_bad(mtd, ofs, getchip);
 644
 645         /* Return info from the table */
 646         return nand_isbad_bbt(mtd, ofs, allowbbt);
 647 }
 648
 649 #ifndef __UBOOT__
 650 /**
 651  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 652  * @mtd: MTD device structure
 653  * @timeo: Timeout
 654  *
 655  * Helper function for nand_wait_ready used when needing to wait in interrupt
 656  * context.
 657  */
 658 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 659 {
 660         struct nand_chip *chip = mtd->priv;
 661         int i;
 662
 663         /* Wait for the device to get ready */
 664         for (i = 0; i < timeo; i++) {
 665                 if (chip->dev_ready(mtd))
 666                         break;
 667                 touch_softlockup_watchdog();
 668                 mdelay(1);
 669         }
 670 }
 671 #endif
 672
 673 /* Wait for the ready pin, after a command. The timeout is caught later. */
 674 void nand_wait_ready(struct mtd_info *mtd)
 675 {
 676         struct nand_chip *chip = mtd->priv;
 677 #ifndef __UBOOT__
 678         unsigned long timeo = jiffies + msecs_to_jiffies(20);
 679
 680         /* 400ms timeout */
 681         if (in_interrupt() || oops_in_progress)
 682                 return panic_nand_wait_ready(mtd, 400);
 683
 684         led_trigger_event(nand_led_trigger, LED_FULL);
 685         /* Wait until command is processed or timeout occurs */
 686         do {
 687                 if (chip->dev_ready(mtd))
 688                         break;
 689                 touch_softlockup_watchdog();
 690         } while (time_before(jiffies, timeo));
 691         led_trigger_event(nand_led_trigger, LED_OFF);
 692 #else
 693         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 694         u32 time_start;
 695
 696         time_start = get_timer(0);
 697         /* Wait until command is processed or timeout occurs */
 698         while (get_timer(time_start) < timeo) {
 699                 if (chip->dev_ready)
 700                         if (chip->dev_ready(mtd))
 701                                 break;
 702         }
 703 #endif
 704 }
 705 EXPORT_SYMBOL_GPL(nand_wait_ready);
 706
 707 /**
 708  * nand_command - [DEFAULT] Send command to NAND device
 709  * @mtd: MTD device structure
 710  * @command: the command to be sent
 711  * @column: the column address for this command, -1 if none
 712  * @page_addr: the page address for this command, -1 if none
 713  *
 714  * Send command to NAND device. This function is used for small page devices
 715  * (512 Bytes per page).
 716  */
 717 static void nand_command(struct mtd_info *mtd, unsigned int command,
 718                          int column, int page_addr)
 719 {
 720         register struct nand_chip *chip = mtd->priv;
 721         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 722         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 723
 724         /* Write out the command to the device */
 725         if (command == NAND_CMD_SEQIN) {
 726                 int readcmd;
 727
 728                 if (column >= mtd->writesize) {
 729                         /* OOB area */
 730                         column -= mtd->writesize;
 731                         readcmd = NAND_CMD_READOOB;
 732                 } else if (column < 256) {
 733                         /* First 256 bytes --> READ0 */
 734                         readcmd = NAND_CMD_READ0;
 735                 } else {
 736                         column -= 256;
 737                         readcmd = NAND_CMD_READ1;
 738                 }
 739                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 740                 ctrl &= ~NAND_CTRL_CHANGE;
 741         }
 742         chip->cmd_ctrl(mtd, command, ctrl);
 743
 744         /* Address cycle, when necessary */
 745         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 746         /* Serially input address */
 747         if (column != -1) {
 748                 /* Adjust columns for 16 bit buswidth */
 749                 if (chip->options & NAND_BUSWIDTH_16 &&
 750                                 !nand_opcode_8bits(command))
 751                         column >>= 1;
 752                 chip->cmd_ctrl(mtd, column, ctrl);
 753                 ctrl &= ~NAND_CTRL_CHANGE;
 754         }
 755         if (page_addr != -1) {
 756                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 757                 ctrl &= ~NAND_CTRL_CHANGE;
 758                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 759                 /* One more address cycle for devices > 32MiB */
 760                 if (chip->chipsize > (32 << 20))
 761                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 762         }
 763         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 764
 765         /*
 766          * Program and erase have their own busy handlers status and sequential
 767          * in needs no delay
 768          */
 769         switch (command) {
 770
 771         case NAND_CMD_PAGEPROG:
 772         case NAND_CMD_ERASE1:
 773         case NAND_CMD_ERASE2:
 774         case NAND_CMD_SEQIN:
 775         case NAND_CMD_STATUS:
 776                 return;
 777
 778         case NAND_CMD_RESET:
 779                 if (chip->dev_ready)
 780                         break;
 781                 udelay(chip->chip_delay);
 782                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 783                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 784                 chip->cmd_ctrl(mtd,
 785                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 786                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 787                         (rst_sts_cnt--));
 788                 return;
 789
 790                 /* This applies to read commands */
 791         default:
 792                 /*
 793                  * If we don't have access to the busy pin, we apply the given
 794                  * command delay
 795                  */
 796                 if (!chip->dev_ready) {
 797                         udelay(chip->chip_delay);
 798                         return;
 799                 }
 800         }
 801         /*
 802          * Apply this short delay always to ensure that we do wait tWB in
 803          * any case on any machine.
 804          */
 805         ndelay(100);
 806
 807         nand_wait_ready(mtd);
 808 }
 809
 810 /**
 811  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 812  * @mtd: MTD device structure
 813  * @command: the command to be sent
 814  * @column: the column address for this command, -1 if none
 815  * @page_addr: the page address for this command, -1 if none
 816  *
 817  * Send command to NAND device. This is the version for the new large page
 818  * devices. We don't have the separate regions as we have in the small page
 819  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 820  */
 821 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 822                             int column, int page_addr)
 823 {
 824         register struct nand_chip *chip = mtd->priv;
 825         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 826
 827         /* Emulate NAND_CMD_READOOB */
 828         if (command == NAND_CMD_READOOB) {
 829                 column += mtd->writesize;
 830                 command = NAND_CMD_READ0;
 831         }
 832
 833         /* Command latch cycle */
 834         chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 835
 836         if (column != -1 || page_addr != -1) {
 837                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 838
 839                 /* Serially input address */
 840                 if (column != -1) {
 841                         /* Adjust columns for 16 bit buswidth */
 842                         if (chip->options & NAND_BUSWIDTH_16 &&
 843                                         !nand_opcode_8bits(command))
 844                                 column >>= 1;
 845                         chip->cmd_ctrl(mtd, column, ctrl);
 846                         ctrl &= ~NAND_CTRL_CHANGE;
 847                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 848                 }
 849                 if (page_addr != -1) {
 850                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 851                         chip->cmd_ctrl(mtd, page_addr >> 8,
 852                                        NAND_NCE | NAND_ALE);
 853                         /* One more address cycle for devices > 128MiB */
 854                         if (chip->chipsize > (128 << 20))
 855                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 856                                                NAND_NCE | NAND_ALE);
 857                 }
 858         }
 859         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 860
 861         /*
 862          * Program and erase have their own busy handlers status, sequential
 863          * in, and deplete1 need no delay.
 864          */
 865         switch (command) {
 866
 867         case NAND_CMD_CACHEDPROG:
 868         case NAND_CMD_PAGEPROG:
 869         case NAND_CMD_ERASE1:
 870         case NAND_CMD_ERASE2:
 871         case NAND_CMD_SEQIN:
 872         case NAND_CMD_RNDIN:
 873         case NAND_CMD_STATUS:
 874                 return;
 875
 876         case NAND_CMD_RESET:
 877                 if (chip->dev_ready)
 878                         break;
 879                 udelay(chip->chip_delay);
 880                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 881                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 882                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 883                                NAND_NCE | NAND_CTRL_CHANGE);
 884                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 885                         (rst_sts_cnt--));
 886                 return;
 887
 888         case NAND_CMD_RNDOUT:
 889                 /* No ready / busy check necessary */
 890                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 891                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 892                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 893                                NAND_NCE | NAND_CTRL_CHANGE);
 894                 return;
 895
 896         case NAND_CMD_READ0:
 897                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 898                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 899                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 900                                NAND_NCE | NAND_CTRL_CHANGE);
 901
 902                 /* This applies to read commands */
 903         default:
 904                 /*
 905                  * If we don't have access to the busy pin, we apply the given
 906                  * command delay.
 907                  */
 908                 if (!chip->dev_ready) {
 909                         udelay(chip->chip_delay);
 910                         return;
 911                 }
 912         }
 913
 914         /*
 915          * Apply this short delay always to ensure that we do wait tWB in
 916          * any case on any machine.
 917          */
 918         ndelay(100);
 919
 920         nand_wait_ready(mtd);
 921 }
 922
 923 /**
 924  * panic_nand_get_device - [GENERIC] Get chip for selected access
 925  * @chip: the nand chip descriptor
 926  * @mtd: MTD device structure
 927  * @new_state: the state which is requested
 928  *
 929  * Used when in panic, no locks are taken.
 930  */
 931 static void panic_nand_get_device(struct nand_chip *chip,
 932                       struct mtd_info *mtd, int new_state)
 933 {
 934         /* Hardware controller shared among independent devices */
 935         chip->controller->active = chip;
 936         chip->state = new_state;
 937 }
 938
 939 /**
 940  * nand_get_device - [GENERIC] Get chip for selected access
 941  * @mtd: MTD device structure
 942  * @new_state: the state which is requested
 943  *
 944  * Get the device and lock it for exclusive access
 945  */
 946 static int
 947 nand_get_device(struct mtd_info *mtd, int new_state)
 948 {
 949         struct nand_chip *chip = mtd->priv;
 950 #ifndef __UBOOT__
 951         spinlock_t *lock = &chip->controller->lock;
 952         wait_queue_head_t *wq = &chip->controller->wq;
 953         DECLARE_WAITQUEUE(wait, current);
 954 retry:
 955         spin_lock(lock);
 956
 957         /* Hardware controller shared among independent devices */
 958         if (!chip->controller->active)
 959                 chip->controller->active = chip;
 960
 961         if (chip->controller->active == chip && chip->state == FL_READY) {
 962                 chip->state = new_state;
 963                 spin_unlock(lock);
 964                 return 0;
 965         }
 966         if (new_state == FL_PM_SUSPENDED) {
 967                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 968                         chip->state = FL_PM_SUSPENDED;
 969                         spin_unlock(lock);
 970                         return 0;
 971                 }
 972         }
 973         set_current_state(TASK_UNINTERRUPTIBLE);
 974         add_wait_queue(wq, &wait);
 975         spin_unlock(lock);
 976         schedule();
 977         remove_wait_queue(wq, &wait);
 978         goto retry;
 979 #else
 980         chip->state = new_state;
 981         return 0;
 982 #endif
 983 }
 984
 985 /**
 986  * panic_nand_wait - [GENERIC] wait until the command is done
 987  * @mtd: MTD device structure
 988  * @chip: NAND chip structure
 989  * @timeo: timeout
 990  *
 991  * Wait for command done. This is a helper function for nand_wait used when
 992  * we are in interrupt context. May happen when in panic and trying to write
 993  * an oops through mtdoops.
 994  */
 995 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 996                             unsigned long timeo)
 997 {
 998         int i;
 999         for (i = 0; i < timeo; i++) {
1000                 if (chip->dev_ready) {
1001                         if (chip->dev_ready(mtd))
1002                                 break;
1003                 } else {
1004                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
1005                                 break;
1006                 }
1007                 mdelay(1);
1008         }
1009 }
1010
1011 /**
1012  * nand_wait - [DEFAULT] wait until the command is done
1013  * @mtd: MTD device structure
1014  * @chip: NAND chip structure
1015  *
1016  * Wait for command done. This applies to erase and program only. Erase can
1017  * take up to 400ms and program up to 20ms according to general NAND and
1018  * SmartMedia specs.
1019  */
1020 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1021 {
1022
1023         int status, state = chip->state;
1024         unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1025
1026         led_trigger_event(nand_led_trigger, LED_FULL);
1027
1028         /*
1029          * Apply this short delay always to ensure that we do wait tWB in any
1030          * case on any machine.
1031          */
1032         ndelay(100);
1033
1034         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1035
1036 #ifndef __UBOOT__
1037         if (in_interrupt() || oops_in_progress)
1038                 panic_nand_wait(mtd, chip, timeo);
1039         else {
1040                 timeo = jiffies + msecs_to_jiffies(timeo);
1041                 while (time_before(jiffies, timeo)) {
1042                         if (chip->dev_ready) {
1043                                 if (chip->dev_ready(mtd))
1044                                         break;
1045                         } else {
1046                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1047                                         break;
1048                         }
1049                         cond_resched();
1050                 }
1051         }
1052 #else
1053         u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1054         u32 time_start;
1055
1056         time_start = get_timer(0);
1057         while (get_timer(time_start) < timer) {
1058                 if (chip->dev_ready) {
1059                         if (chip->dev_ready(mtd))
1060                                 break;
1061                 } else {
1062                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
1063                                 break;
1064                 }
1065         }
1066 #endif
1067 #ifdef PPCHAMELON_NAND_TIMER_HACK
1068         time_start = get_timer(0);
1069         while (get_timer(time_start) < 10)
1070                 ;
1071 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
1072         led_trigger_event(nand_led_trigger, LED_OFF);
1073
1074         status = (int)chip->read_byte(mtd);
1075         /* This can happen if in case of timeout or buggy dev_ready */
1076         WARN_ON(!(status & NAND_STATUS_READY));
1077         return status;
1078 }
1079
1080 #ifndef __UBOOT__
1081 /**
1082  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1083  * @mtd: mtd info
1084  * @ofs: offset to start unlock from
1085  * @len: length to unlock
1086  * @invert: when = 0, unlock the range of blocks within the lower and
1087  *                    upper boundary address
1088  *          when = 1, unlock the range of blocks outside the boundaries
1089  *                    of the lower and upper boundary address
1090  *
1091  * Returs unlock status.
1092  */
1093 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1094                                         uint64_t len, int invert)
1095 {
1096         int ret = 0;
1097         int status, page;
1098         struct nand_chip *chip = mtd->priv;
1099
1100         /* Submit address of first page to unlock */
1101         page = ofs >> chip->page_shift;
1102         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1103
1104         /* Submit address of last page to unlock */
1105         page = (ofs + len) >> chip->page_shift;
1106         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1107                                 (page | invert) & chip->pagemask);
1108
1109         /* Call wait ready function */
1110         status = chip->waitfunc(mtd, chip);
1111         /* See if device thinks it succeeded */
1112         if (status & NAND_STATUS_FAIL) {
1113                 pr_debug("%s: error status = 0x%08x\n",
1114                                         __func__, status);
1115                 ret = -EIO;
1116         }
1117
1118         return ret;
1119 }
1120
1121 /**
1122  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1123  * @mtd: mtd info
1124  * @ofs: offset to start unlock from
1125  * @len: length to unlock
1126  *
1127  * Returns unlock status.
1128  */
1129 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1130 {
1131         int ret = 0;
1132         int chipnr;
1133         struct nand_chip *chip = mtd->priv;
1134
1135         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1136                         __func__, (unsigned long long)ofs, len);
1137
1138         if (check_offs_len(mtd, ofs, len))
1139                 ret = -EINVAL;
1140
1141         /* Align to last block address if size addresses end of the device */
1142         if (ofs + len == mtd->size)
1143                 len -= mtd->erasesize;
1144
1145         nand_get_device(mtd, FL_UNLOCKING);
1146
1147         /* Shift to get chip number */
1148         chipnr = ofs >> chip->chip_shift;
1149
1150         chip->select_chip(mtd, chipnr);
1151
1152         /* Check, if it is write protected */
1153         if (nand_check_wp(mtd)) {
1154                 pr_debug("%s: device is write protected!\n",
1155                                         __func__);
1156                 ret = -EIO;
1157                 goto out;
1158         }
1159
1160         ret = __nand_unlock(mtd, ofs, len, 0);
1161
1162 out:
1163         chip->select_chip(mtd, -1);
1164         nand_release_device(mtd);
1165
1166         return ret;
1167 }
1168 EXPORT_SYMBOL(nand_unlock);
1169
1170 /**
1171  * nand_lock - [REPLACEABLE] locks all blocks present in the device
1172  * @mtd: mtd info
1173  * @ofs: offset to start unlock from
1174  * @len: length to unlock
1175  *
1176  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1177  * have this feature, but it allows only to lock all blocks, not for specified
1178  * range for block. Implementing 'lock' feature by making use of 'unlock', for
1179  * now.
1180  *
1181  * Returns lock status.
1182  */
1183 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1184 {
1185         int ret = 0;
1186         int chipnr, status, page;
1187         struct nand_chip *chip = mtd->priv;
1188
1189         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1190                         __func__, (unsigned long long)ofs, len);
1191
1192         if (check_offs_len(mtd, ofs, len))
1193                 ret = -EINVAL;
1194
1195         nand_get_device(mtd, FL_LOCKING);
1196
1197         /* Shift to get chip number */
1198         chipnr = ofs >> chip->chip_shift;
1199
1200         chip->select_chip(mtd, chipnr);
1201
1202         /* Check, if it is write protected */
1203         if (nand_check_wp(mtd)) {
1204                 pr_debug("%s: device is write protected!\n",
1205                                         __func__);
1206                 status = MTD_ERASE_FAILED;
1207                 ret = -EIO;
1208                 goto out;
1209         }
1210
1211         /* Submit address of first page to lock */
1212         page = ofs >> chip->page_shift;
1213         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1214
1215         /* Call wait ready function */
1216         status = chip->waitfunc(mtd, chip);
1217         /* See if device thinks it succeeded */
1218         if (status & NAND_STATUS_FAIL) {
1219                 pr_debug("%s: error status = 0x%08x\n",
1220                                         __func__, status);
1221                 ret = -EIO;
1222                 goto out;
1223         }
1224
1225         ret = __nand_unlock(mtd, ofs, len, 0x1);
1226
1227 out:
1228         chip->select_chip(mtd, -1);
1229         nand_release_device(mtd);
1230
1231         return ret;
1232 }
1233 EXPORT_SYMBOL(nand_lock);
1234 #endif
1235
1236 /**
1237  * nand_read_page_raw - [INTERN] read raw page data without ecc
1238  * @mtd: mtd info structure
1239  * @chip: nand chip info structure
1240  * @buf: buffer to store read data
1241  * @oob_required: caller requires OOB data read to chip->oob_poi
1242  * @page: page number to read
1243  *
1244  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1245  */
1246 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1247                               uint8_t *buf, int oob_required, int page)
1248 {
1249         chip->read_buf(mtd, buf, mtd->writesize);
1250         if (oob_required)
1251                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1252         return 0;
1253 }
1254
1255 /**
1256  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1257  * @mtd: mtd info structure
1258  * @chip: nand chip info structure
1259  * @buf: buffer to store read data
1260  * @oob_required: caller requires OOB data read to chip->oob_poi
1261  * @page: page number to read
1262  *
1263  * We need a special oob layout and handling even when OOB isn't used.
1264  */
1265 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1266                                        struct nand_chip *chip, uint8_t *buf,
1267                                        int oob_required, int page)
1268 {
1269         int eccsize = chip->ecc.size;
1270         int eccbytes = chip->ecc.bytes;
1271         uint8_t *oob = chip->oob_poi;
1272         int steps, size;
1273
1274         for (steps = chip->ecc.steps; steps > 0; steps--) {
1275                 chip->read_buf(mtd, buf, eccsize);
1276                 buf += eccsize;
1277
1278                 if (chip->ecc.prepad) {
1279                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1280                         oob += chip->ecc.prepad;
1281                 }
1282
1283                 chip->read_buf(mtd, oob, eccbytes);
1284                 oob += eccbytes;
1285
1286                 if (chip->ecc.postpad) {
1287                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1288                         oob += chip->ecc.postpad;
1289                 }
1290         }
1291
1292         size = mtd->oobsize - (oob - chip->oob_poi);
1293         if (size)
1294                 chip->read_buf(mtd, oob, size);
1295
1296         return 0;
1297 }
1298
1299 /**
1300  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1301  * @mtd: mtd info structure
1302  * @chip: nand chip info structure
1303  * @buf: buffer to store read data
1304  * @oob_required: caller requires OOB data read to chip->oob_poi
1305  * @page: page number to read
1306  */
1307 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1308                                 uint8_t *buf, int oob_required, int page)
1309 {
1310         int i, eccsize = chip->ecc.size;
1311         int eccbytes = chip->ecc.bytes;
1312         int eccsteps = chip->ecc.steps;
1313         uint8_t *p = buf;
1314         uint8_t *ecc_calc = chip->buffers->ecccalc;
1315         uint8_t *ecc_code = chip->buffers->ecccode;
1316         uint32_t *eccpos = chip->ecc.layout->eccpos;
1317         unsigned int max_bitflips = 0;
1318
1319         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1320
1321         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1322                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1323
1324         for (i = 0; i < chip->ecc.total; i++)
1325                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1326
1327         eccsteps = chip->ecc.steps;
1328         p = buf;
1329
1330         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1331                 int stat;
1332
1333                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1334                 if (stat < 0) {
1335                         mtd->ecc_stats.failed++;
1336                 } else {
1337                         mtd->ecc_stats.corrected += stat;
1338                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1339                 }
1340         }
1341         return max_bitflips;
1342 }
1343
1344 /**
1345  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1346  * @mtd: mtd info structure
1347  * @chip: nand chip info structure
1348  * @data_offs: offset of requested data within the page
1349  * @readlen: data length
1350  * @bufpoi: buffer to store read data
1351  * @page: page number to read
1352  */
1353 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1354                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1355                         int page)
1356 {
1357         int start_step, end_step, num_steps;
1358         uint32_t *eccpos = chip->ecc.layout->eccpos;
1359         uint8_t *p;
1360         int data_col_addr, i, gaps = 0;
1361         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1362         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1363         int index;
1364         unsigned int max_bitflips = 0;
1365
1366         /* Column address within the page aligned to ECC size (256bytes) */
1367         start_step = data_offs / chip->ecc.size;
1368         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1369         num_steps = end_step - start_step + 1;
1370         index = start_step * chip->ecc.bytes;
1371
1372         /* Data size aligned to ECC ecc.size */
1373         datafrag_len = num_steps * chip->ecc.size;
1374         eccfrag_len = num_steps * chip->ecc.bytes;
1375
1376         data_col_addr = start_step * chip->ecc.size;
1377         /* If we read not a page aligned data */
1378         if (data_col_addr != 0)
1379                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1380
1381         p = bufpoi + data_col_addr;
1382         chip->read_buf(mtd, p, datafrag_len);
1383
1384         /* Calculate ECC */
1385         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1386                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1387
1388         /*
1389          * The performance is faster if we position offsets according to
1390          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1391          */
1392         for (i = 0; i < eccfrag_len - 1; i++) {
1393                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1394                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1395                         gaps = 1;
1396                         break;
1397                 }
1398         }
1399         if (gaps) {
1400                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1401                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1402         } else {
1403                 /*
1404                  * Send the command to read the particular ECC bytes take care
1405                  * about buswidth alignment in read_buf.
1406                  */
1407                 aligned_pos = eccpos[index] & ~(busw - 1);
1408                 aligned_len = eccfrag_len;
1409                 if (eccpos[index] & (busw - 1))
1410                         aligned_len++;
1411                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1412                         aligned_len++;
1413
1414                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1415                                         mtd->writesize + aligned_pos, -1);
1416                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1417         }
1418
1419         for (i = 0; i < eccfrag_len; i++)
1420                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1421
1422         p = bufpoi + data_col_addr;
1423         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1424                 int stat;
1425
1426                 stat = chip->ecc.correct(mtd, p,
1427                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1428                 if (stat < 0) {
1429                         mtd->ecc_stats.failed++;
1430                 } else {
1431                         mtd->ecc_stats.corrected += stat;
1432                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1433                 }
1434         }
1435         return max_bitflips;
1436 }
1437
1438 /**
1439  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1440  * @mtd: mtd info structure
1441  * @chip: nand chip info structure
1442  * @buf: buffer to store read data
1443  * @oob_required: caller requires OOB data read to chip->oob_poi
1444  * @page: page number to read
1445  *
1446  * Not for syndrome calculating ECC controllers which need a special oob layout.
1447  */
1448 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1449                                 uint8_t *buf, int oob_required, int page)
1450 {
1451         int i, eccsize = chip->ecc.size;
1452         int eccbytes = chip->ecc.bytes;
1453         int eccsteps = chip->ecc.steps;
1454         uint8_t *p = buf;
1455         uint8_t *ecc_calc = chip->buffers->ecccalc;
1456         uint8_t *ecc_code = chip->buffers->ecccode;
1457         uint32_t *eccpos = chip->ecc.layout->eccpos;
1458         unsigned int max_bitflips = 0;
1459
1460         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1461                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1462                 chip->read_buf(mtd, p, eccsize);
1463                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1464         }
1465         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1466
1467         for (i = 0; i < chip->ecc.total; i++)
1468                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1469
1470         eccsteps = chip->ecc.steps;
1471         p = buf;
1472
1473         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1474                 int stat;
1475
1476                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1477                 if (stat < 0) {
1478                         mtd->ecc_stats.failed++;
1479                 } else {
1480                         mtd->ecc_stats.corrected += stat;
1481                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1482                 }
1483         }
1484         return max_bitflips;
1485 }
1486
1487 /**
1488  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1489  * @mtd: mtd info structure
1490  * @chip: nand chip info structure
1491  * @buf: buffer to store read data
1492  * @oob_required: caller requires OOB data read to chip->oob_poi
1493  * @page: page number to read
1494  *
1495  * Hardware ECC for large page chips, require OOB to be read first. For this
1496  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1497  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1498  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1499  * the data area, by overwriting the NAND manufacturer bad block markings.
1500  */
1501 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1502         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1503 {
1504         int i, eccsize = chip->ecc.size;
1505         int eccbytes = chip->ecc.bytes;
1506         int eccsteps = chip->ecc.steps;
1507         uint8_t *p = buf;
1508         uint8_t *ecc_code = chip->buffers->ecccode;
1509         uint32_t *eccpos = chip->ecc.layout->eccpos;
1510         uint8_t *ecc_calc = chip->buffers->ecccalc;
1511         unsigned int max_bitflips = 0;
1512
1513         /* Read the OOB area first */
1514         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1515         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1516         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1517
1518         for (i = 0; i < chip->ecc.total; i++)
1519                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1520
1521         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1522                 int stat;
1523
1524                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1525                 chip->read_buf(mtd, p, eccsize);
1526                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1527
1528                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1529                 if (stat < 0) {
1530                         mtd->ecc_stats.failed++;
1531                 } else {
1532                         mtd->ecc_stats.corrected += stat;
1533                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1534                 }
1535         }
1536         return max_bitflips;
1537 }
1538
1539 /**
1540  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1541  * @mtd: mtd info structure
1542  * @chip: nand chip info structure
1543  * @buf: buffer to store read data
1544  * @oob_required: caller requires OOB data read to chip->oob_poi
1545  * @page: page number to read
1546  *
1547  * The hw generator calculates the error syndrome automatically. Therefore we
1548  * need a special oob layout and handling.
1549  */
1550 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1551                                    uint8_t *buf, int oob_required, int page)
1552 {
1553         int i, eccsize = chip->ecc.size;
1554         int eccbytes = chip->ecc.bytes;
1555         int eccsteps = chip->ecc.steps;
1556         uint8_t *p = buf;
1557         uint8_t *oob = chip->oob_poi;
1558         unsigned int max_bitflips = 0;
1559
1560         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1561                 int stat;
1562
1563                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1564                 chip->read_buf(mtd, p, eccsize);
1565
1566                 if (chip->ecc.prepad) {
1567                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1568                         oob += chip->ecc.prepad;
1569                 }
1570
1571                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1572                 chip->read_buf(mtd, oob, eccbytes);
1573                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1574
1575                 if (stat < 0) {
1576                         mtd->ecc_stats.failed++;
1577                 } else {
1578                         mtd->ecc_stats.corrected += stat;
1579                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1580                 }
1581
1582                 oob += eccbytes;
1583
1584                 if (chip->ecc.postpad) {
1585                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1586                         oob += chip->ecc.postpad;
1587                 }
1588         }
1589
1590         /* Calculate remaining oob bytes */
1591         i = mtd->oobsize - (oob - chip->oob_poi);
1592         if (i)
1593                 chip->read_buf(mtd, oob, i);
1594
1595         return max_bitflips;
1596 }
1597
1598 /**
1599  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1600  * @chip: nand chip structure
1601  * @oob: oob destination address
1602  * @ops: oob ops structure
1603  * @len: size of oob to transfer
1604  */
1605 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1606                                   struct mtd_oob_ops *ops, size_t len)
1607 {
1608         switch (ops->mode) {
1609
1610         case MTD_OPS_PLACE_OOB:
1611         case MTD_OPS_RAW:
1612                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1613                 return oob + len;
1614
1615         case MTD_OPS_AUTO_OOB: {
1616                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1617                 uint32_t boffs = 0, roffs = ops->ooboffs;
1618                 size_t bytes = 0;
1619
1620                 for (; free->length && len; free++, len -= bytes) {
1621                         /* Read request not from offset 0? */
1622                         if (unlikely(roffs)) {
1623                                 if (roffs >= free->length) {
1624                                         roffs -= free->length;
1625                                         continue;
1626                                 }
1627                                 boffs = free->offset + roffs;
1628                                 bytes = min_t(size_t, len,
1629                                               (free->length - roffs));
1630                                 roffs = 0;
1631                         } else {
1632                                 bytes = min_t(size_t, len, free->length);
1633                                 boffs = free->offset;
1634                         }
1635                         memcpy(oob, chip->oob_poi + boffs, bytes);
1636                         oob += bytes;
1637                 }
1638                 return oob;
1639         }
1640         default:
1641                 BUG();
1642         }
1643         return NULL;
1644 }
1645
1646 /**
1647  * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1648  * @mtd: MTD device structure
1649  * @retry_mode: the retry mode to use
1650  *
1651  * Some vendors supply a special command to shift the Vt threshold, to be used
1652  * when there are too many bitflips in a page (i.e., ECC error). After setting
1653  * a new threshold, the host should retry reading the page.
1654  */
1655 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1656 {
1657         struct nand_chip *chip = mtd->priv;
1658
1659         pr_debug("setting READ RETRY mode %d\n", retry_mode);
1660
1661         if (retry_mode >= chip->read_retries)
1662                 return -EINVAL;
1663
1664         if (!chip->setup_read_retry)
1665                 return -EOPNOTSUPP;
1666
1667         return chip->setup_read_retry(mtd, retry_mode);
1668 }
1669
1670 /**
1671  * nand_do_read_ops - [INTERN] Read data with ECC
1672  * @mtd: MTD device structure
1673  * @from: offset to read from
1674  * @ops: oob ops structure
1675  *
1676  * Internal function. Called with chip held.
1677  */
1678 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1679                             struct mtd_oob_ops *ops)
1680 {
1681         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1682         struct nand_chip *chip = mtd->priv;
1683         int ret = 0;
1684         uint32_t readlen = ops->len;
1685         uint32_t oobreadlen = ops->ooblen;
1686         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1687                 mtd->oobavail : mtd->oobsize;
1688
1689         uint8_t *bufpoi, *oob, *buf;
1690         unsigned int max_bitflips = 0;
1691         int retry_mode = 0;
1692         bool ecc_fail = false;
1693
1694         chipnr = (int)(from >> chip->chip_shift);
1695         chip->select_chip(mtd, chipnr);
1696
1697         realpage = (int)(from >> chip->page_shift);
1698         page = realpage & chip->pagemask;
1699
1700         col = (int)(from & (mtd->writesize - 1));
1701
1702         buf = ops->datbuf;
1703         oob = ops->oobbuf;
1704         oob_required = oob ? 1 : 0;
1705
1706         while (1) {
1707                 unsigned int ecc_failures = mtd->ecc_stats.failed;
1708
1709                 WATCHDOG_RESET();
1710                 bytes = min(mtd->writesize - col, readlen);
1711                 aligned = (bytes == mtd->writesize);
1712
1713                 /* Is the current page in the buffer? */
1714                 if (realpage != chip->pagebuf || oob) {
1715                         bufpoi = aligned ? buf : chip->buffers->databuf;
1716
1717 read_retry:
1718                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1719
1720                         /*
1721                          * Now read the page into the buffer.  Absent an error,
1722                          * the read methods return max bitflips per ecc step.
1723                          */
1724                         if (unlikely(ops->mode == MTD_OPS_RAW))
1725                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1726                                                               oob_required,
1727                                                               page);
1728                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1729                                  !oob)
1730                                 ret = chip->ecc.read_subpage(mtd, chip,
1731                                                         col, bytes, bufpoi,
1732                                                         page);
1733                         else
1734                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1735                                                           oob_required, page);
1736                         if (ret < 0) {
1737                                 if (!aligned)
1738                                         /* Invalidate page cache */
1739                                         chip->pagebuf = -1;
1740                                 break;
1741                         }
1742
1743                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1744
1745                         /* Transfer not aligned data */
1746                         if (!aligned) {
1747                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1748                                     !(mtd->ecc_stats.failed - ecc_failures) &&
1749                                     (ops->mode != MTD_OPS_RAW)) {
1750                                         chip->pagebuf = realpage;
1751                                         chip->pagebuf_bitflips = ret;
1752                                 } else {
1753                                         /* Invalidate page cache */
1754                                         chip->pagebuf = -1;
1755                                 }
1756                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1757                         }
1758
1759                         if (unlikely(oob)) {
1760                                 int toread = min(oobreadlen, max_oobsize);
1761
1762                                 if (toread) {
1763                                         oob = nand_transfer_oob(chip,
1764                                                 oob, ops, toread);
1765                                         oobreadlen -= toread;
1766                                 }
1767                         }
1768
1769                         if (chip->options & NAND_NEED_READRDY) {
1770                                 /* Apply delay or wait for ready/busy pin */
1771                                 if (!chip->dev_ready)
1772                                         udelay(chip->chip_delay);
1773                                 else
1774                                         nand_wait_ready(mtd);
1775                         }
1776
1777                         if (mtd->ecc_stats.failed - ecc_failures) {
1778                                 if (retry_mode + 1 < chip->read_retries) {
1779                                         retry_mode++;
1780                                         ret = nand_setup_read_retry(mtd,
1781                                                         retry_mode);
1782                                         if (ret < 0)
1783                                                 break;
1784
1785                                         /* Reset failures; retry */
1786                                         mtd->ecc_stats.failed = ecc_failures;
1787                                         goto read_retry;
1788                                 } else {
1789                                         /* No more retry modes; real failure */
1790                                         ecc_fail = true;
1791                                 }
1792                         }
1793
1794                         buf += bytes;
1795                 } else {
1796                         memcpy(buf, chip->buffers->databuf + col, bytes);
1797                         buf += bytes;
1798                         max_bitflips = max_t(unsigned int, max_bitflips,
1799                                              chip->pagebuf_bitflips);
1800                 }
1801
1802                 readlen -= bytes;
1803
1804                 /* Reset to retry mode 0 */
1805                 if (retry_mode) {
1806                         ret = nand_setup_read_retry(mtd, 0);
1807                         if (ret < 0)
1808                                 break;
1809                         retry_mode = 0;
1810                 }
1811
1812                 if (!readlen)
1813                         break;
1814
1815                 /* For subsequent reads align to page boundary */
1816                 col = 0;
1817                 /* Increment page address */
1818                 realpage++;
1819
1820                 page = realpage & chip->pagemask;
1821                 /* Check, if we cross a chip boundary */
1822                 if (!page) {
1823                         chipnr++;
1824                         chip->select_chip(mtd, -1);
1825                         chip->select_chip(mtd, chipnr);
1826                 }
1827         }
1828         chip->select_chip(mtd, -1);
1829
1830         ops->retlen = ops->len - (size_t) readlen;
1831         if (oob)
1832                 ops->oobretlen = ops->ooblen - oobreadlen;
1833
1834         if (ret < 0)
1835                 return ret;
1836
1837         if (ecc_fail)
1838                 return -EBADMSG;
1839
1840         return max_bitflips;
1841 }
1842
1843 /**
1844  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1845  * @mtd: MTD device structure
1846  * @from: offset to read from
1847  * @len: number of bytes to read
1848  * @retlen: pointer to variable to store the number of read bytes
1849  * @buf: the databuffer to put data
1850  *
1851  * Get hold of the chip and call nand_do_read.
1852  */
1853 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1854                      size_t *retlen, uint8_t *buf)
1855 {
1856         struct mtd_oob_ops ops;
1857         int ret;
1858
1859         nand_get_device(mtd, FL_READING);
1860         ops.len = len;
1861         ops.datbuf = buf;
1862         ops.oobbuf = NULL;
1863         ops.mode = MTD_OPS_PLACE_OOB;
1864         ret = nand_do_read_ops(mtd, from, &ops);
1865         *retlen = ops.retlen;
1866         nand_release_device(mtd);
1867         return ret;
1868 }
1869
1870 /**
1871  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1872  * @mtd: mtd info structure
1873  * @chip: nand chip info structure
1874  * @page: page number to read
1875  */
1876 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1877                              int page)
1878 {
1879         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1880         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1881         return 0;
1882 }
1883
1884 /**
1885  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1886  *                          with syndromes
1887  * @mtd: mtd info structure
1888  * @chip: nand chip info structure
1889  * @page: page number to read
1890  */
1891 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1892                                   int page)
1893 {
1894         uint8_t *buf = chip->oob_poi;
1895         int length = mtd->oobsize;
1896         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1897         int eccsize = chip->ecc.size;
1898         uint8_t *bufpoi = buf;
1899         int i, toread, sndrnd = 0, pos;
1900
1901         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1902         for (i = 0; i < chip->ecc.steps; i++) {
1903                 if (sndrnd) {
1904                         pos = eccsize + i * (eccsize + chunk);
1905                         if (mtd->writesize > 512)
1906                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1907                         else
1908                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1909                 } else
1910                         sndrnd = 1;
1911                 toread = min_t(int, length, chunk);
1912                 chip->read_buf(mtd, bufpoi, toread);
1913                 bufpoi += toread;
1914                 length -= toread;
1915         }
1916         if (length > 0)
1917                 chip->read_buf(mtd, bufpoi, length);
1918
1919         return 0;
1920 }
1921
1922 /**
1923  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1924  * @mtd: mtd info structure
1925  * @chip: nand chip info structure
1926  * @page: page number to write
1927  */
1928 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1929                               int page)
1930 {
1931         int status = 0;
1932         const uint8_t *buf = chip->oob_poi;
1933         int length = mtd->oobsize;
1934
1935         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1936         chip->write_buf(mtd, buf, length);
1937         /* Send command to program the OOB data */
1938         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1939
1940         status = chip->waitfunc(mtd, chip);
1941
1942         return status & NAND_STATUS_FAIL ? -EIO : 0;
1943 }
1944
1945 /**
1946  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1947  *                           with syndrome - only for large page flash
1948  * @mtd: mtd info structure
1949  * @chip: nand chip info structure
1950  * @page: page number to write
1951  */
1952 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1953                                    struct nand_chip *chip, int page)
1954 {
1955         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1956         int eccsize = chip->ecc.size, length = mtd->oobsize;
1957         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1958         const uint8_t *bufpoi = chip->oob_poi;
1959
1960         /*
1961          * data-ecc-data-ecc ... ecc-oob
1962          * or
1963          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1964          */
1965         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1966                 pos = steps * (eccsize + chunk);
1967                 steps = 0;
1968         } else
1969                 pos = eccsize;
1970
1971         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1972         for (i = 0; i < steps; i++) {
1973                 if (sndcmd) {
1974                         if (mtd->writesize <= 512) {
1975                                 uint32_t fill = 0xFFFFFFFF;
1976
1977                                 len = eccsize;
1978                                 while (len > 0) {
1979                                         int num = min_t(int, len, 4);
1980                                         chip->write_buf(mtd, (uint8_t *)&fill,
1981                                                         num);
1982                                         len -= num;
1983                                 }
1984                         } else {
1985                                 pos = eccsize + i * (eccsize + chunk);
1986                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1987                         }
1988                 } else
1989                         sndcmd = 1;
1990                 len = min_t(int, length, chunk);
1991                 chip->write_buf(mtd, bufpoi, len);
1992                 bufpoi += len;
1993                 length -= len;
1994         }
1995         if (length > 0)
1996                 chip->write_buf(mtd, bufpoi, length);
1997
1998         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1999         status = chip->waitfunc(mtd, chip);
2000
2001         return status & NAND_STATUS_FAIL ? -EIO : 0;
2002 }
2003
2004 /**
2005  * nand_do_read_oob - [INTERN] NAND read out-of-band
2006  * @mtd: MTD device structure
2007  * @from: offset to read from
2008  * @ops: oob operations description structure
2009  *
2010  * NAND read out-of-band data from the spare area.
2011  */
2012 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2013                             struct mtd_oob_ops *ops)
2014 {
2015         int page, realpage, chipnr;
2016         struct nand_chip *chip = mtd->priv;
2017         struct mtd_ecc_stats stats;
2018         int readlen = ops->ooblen;
2019         int len;
2020         uint8_t *buf = ops->oobbuf;
2021         int ret = 0;
2022
2023         pr_debug("%s: from = 0x%08Lx, len = %i\n",
2024                         __func__, (unsigned long long)from, readlen);
2025
2026         stats = mtd->ecc_stats;
2027
2028         if (ops->mode == MTD_OPS_AUTO_OOB)
2029                 len = chip->ecc.layout->oobavail;
2030         else
2031                 len = mtd->oobsize;
2032
2033         if (unlikely(ops->ooboffs >= len)) {
2034                 pr_debug("%s: attempt to start read outside oob\n",
2035                                 __func__);
2036                 return -EINVAL;
2037         }
2038
2039         /* Do not allow reads past end of device */
2040         if (unlikely(from >= mtd->size ||
2041                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2042                                         (from >> chip->page_shift)) * len)) {
2043                 pr_debug("%s: attempt to read beyond end of device\n",
2044                                 __func__);
2045                 return -EINVAL;
2046         }
2047
2048         chipnr = (int)(from >> chip->chip_shift);
2049         chip->select_chip(mtd, chipnr);
2050
2051         /* Shift to get page */
2052         realpage = (int)(from >> chip->page_shift);
2053         page = realpage & chip->pagemask;
2054
2055         while (1) {
2056                 WATCHDOG_RESET();
2057
2058                 if (ops->mode == MTD_OPS_RAW)
2059                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
2060                 else
2061                         ret = chip->ecc.read_oob(mtd, chip, page);
2062
2063                 if (ret < 0)
2064                         break;
2065
2066                 len = min(len, readlen);
2067                 buf = nand_transfer_oob(chip, buf, ops, len);
2068
2069                 if (chip->options & NAND_NEED_READRDY) {
2070                         /* Apply delay or wait for ready/busy pin */
2071                         if (!chip->dev_ready)
2072                                 udelay(chip->chip_delay);
2073                         else
2074                                 nand_wait_ready(mtd);
2075                 }
2076
2077                 readlen -= len;
2078                 if (!readlen)
2079                         break;
2080
2081                 /* Increment page address */
2082                 realpage++;
2083
2084                 page = realpage & chip->pagemask;
2085                 /* Check, if we cross a chip boundary */
2086                 if (!page) {
2087                         chipnr++;
2088                         chip->select_chip(mtd, -1);
2089                         chip->select_chip(mtd, chipnr);
2090                 }
2091         }
2092         chip->select_chip(mtd, -1);
2093
2094         ops->oobretlen = ops->ooblen - readlen;
2095
2096         if (ret < 0)
2097                 return ret;
2098
2099         if (mtd->ecc_stats.failed - stats.failed)
2100                 return -EBADMSG;
2101
2102         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2103 }
2104
2105 /**
2106  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2107  * @mtd: MTD device structure
2108  * @from: offset to read from
2109  * @ops: oob operation description structure
2110  *
2111  * NAND read data and/or out-of-band data.
2112  */
2113 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2114                          struct mtd_oob_ops *ops)
2115 {
2116         int ret = -ENOTSUPP;
2117
2118         ops->retlen = 0;
2119
2120         /* Do not allow reads past end of device */
2121         if (ops->datbuf && (from + ops->len) > mtd->size) {
2122                 pr_debug("%s: attempt to read beyond end of device\n",
2123                                 __func__);
2124                 return -EINVAL;
2125         }
2126
2127         nand_get_device(mtd, FL_READING);
2128
2129         switch (ops->mode) {
2130         case MTD_OPS_PLACE_OOB:
2131         case MTD_OPS_AUTO_OOB:
2132         case MTD_OPS_RAW:
2133                 break;
2134
2135         default:
2136                 goto out;
2137         }
2138
2139         if (!ops->datbuf)
2140                 ret = nand_do_read_oob(mtd, from, ops);
2141         else
2142                 ret = nand_do_read_ops(mtd, from, ops);
2143
2144 out:
2145         nand_release_device(mtd);
2146         return ret;
2147 }
2148
2149
2150 /**
2151  * nand_write_page_raw - [INTERN] raw page write function
2152  * @mtd: mtd info structure
2153  * @chip: nand chip info structure
2154  * @buf: data buffer
2155  * @oob_required: must write chip->oob_poi to OOB
2156  *
2157  * Not for syndrome calculating ECC controllers, which use a special oob layout.
2158  */
2159 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2160                                 const uint8_t *buf, int oob_required)
2161 {
2162         chip->write_buf(mtd, buf, mtd->writesize);
2163         if (oob_required)
2164                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2165
2166         return 0;
2167 }
2168
2169 /**
2170  * nand_write_page_raw_syndrome - [INTERN] raw page write function
2171  * @mtd: mtd info structure
2172  * @chip: nand chip info structure
2173  * @buf: data buffer
2174  * @oob_required: must write chip->oob_poi to OOB
2175  *
2176  * We need a special oob layout and handling even when ECC isn't checked.
2177  */
2178 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2179                                         struct nand_chip *chip,
2180                                         const uint8_t *buf, int oob_required)
2181 {
2182         int eccsize = chip->ecc.size;
2183         int eccbytes = chip->ecc.bytes;
2184         uint8_t *oob = chip->oob_poi;
2185         int steps, size;
2186
2187         for (steps = chip->ecc.steps; steps > 0; steps--) {
2188                 chip->write_buf(mtd, buf, eccsize);
2189                 buf += eccsize;
2190
2191                 if (chip->ecc.prepad) {
2192                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2193                         oob += chip->ecc.prepad;
2194                 }
2195
2196                 chip->write_buf(mtd, oob, eccbytes);
2197                 oob += eccbytes;
2198
2199                 if (chip->ecc.postpad) {
2200                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2201                         oob += chip->ecc.postpad;
2202                 }
2203         }
2204
2205         size = mtd->oobsize - (oob - chip->oob_poi);
2206         if (size)
2207                 chip->write_buf(mtd, oob, size);
2208
2209         return 0;
2210 }
2211 /**
2212  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2213  * @mtd: mtd info structure
2214  * @chip: nand chip info structure
2215  * @buf: data buffer
2216  * @oob_required: must write chip->oob_poi to OOB
2217  */
2218 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2219                                   const uint8_t *buf, int oob_required)
2220 {
2221         int i, eccsize = chip->ecc.size;
2222         int eccbytes = chip->ecc.bytes;
2223         int eccsteps = chip->ecc.steps;
2224         uint8_t *ecc_calc = chip->buffers->ecccalc;
2225         const uint8_t *p = buf;
2226         uint32_t *eccpos = chip->ecc.layout->eccpos;
2227
2228         /* Software ECC calculation */
2229         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2230                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2231
2232         for (i = 0; i < chip->ecc.total; i++)
2233                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2234
2235         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2236 }
2237
2238 /**
2239  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2240  * @mtd: mtd info structure
2241  * @chip: nand chip info structure
2242  * @buf: data buffer
2243  * @oob_required: must write chip->oob_poi to OOB
2244  */
2245 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2246                                   const uint8_t *buf, int oob_required)
2247 {
2248         int i, eccsize = chip->ecc.size;
2249         int eccbytes = chip->ecc.bytes;
2250         int eccsteps = chip->ecc.steps;
2251         uint8_t *ecc_calc = chip->buffers->ecccalc;
2252         const uint8_t *p = buf;
2253         uint32_t *eccpos = chip->ecc.layout->eccpos;
2254
2255         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2256                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2257                 chip->write_buf(mtd, p, eccsize);
2258                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2259         }
2260
2261         for (i = 0; i < chip->ecc.total; i++)
2262                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2263
2264         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2265
2266         return 0;
2267 }
2268
2269
2270 /**
2271  * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2272  * @mtd:        mtd info structure
2273  * @chip:       nand chip info structure
2274  * @offset:     column address of subpage within the page
2275  * @data_len:   data length
2276  * @buf:        data buffer
2277  * @oob_required: must write chip->oob_poi to OOB
2278  */
2279 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2280                                 struct nand_chip *chip, uint32_t offset,
2281                                 uint32_t data_len, const uint8_t *buf,
2282                                 int oob_required)
2283 {
2284         uint8_t *oob_buf  = chip->oob_poi;
2285         uint8_t *ecc_calc = chip->buffers->ecccalc;
2286         int ecc_size      = chip->ecc.size;
2287         int ecc_bytes     = chip->ecc.bytes;
2288         int ecc_steps     = chip->ecc.steps;
2289         uint32_t *eccpos  = chip->ecc.layout->eccpos;
2290         uint32_t start_step = offset / ecc_size;
2291         uint32_t end_step   = (offset + data_len - 1) / ecc_size;
2292         int oob_bytes       = mtd->oobsize / ecc_steps;
2293         int step, i;
2294
2295         for (step = 0; step < ecc_steps; step++) {
2296                 /* configure controller for WRITE access */
2297                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2298
2299                 /* write data (untouched subpages already masked by 0xFF) */
2300                 chip->write_buf(mtd, buf, ecc_size);
2301
2302                 /* mask ECC of un-touched subpages by padding 0xFF */
2303                 if ((step < start_step) || (step > end_step))
2304                         memset(ecc_calc, 0xff, ecc_bytes);
2305                 else
2306                         chip->ecc.calculate(mtd, buf, ecc_calc);
2307
2308                 /* mask OOB of un-touched subpages by padding 0xFF */
2309                 /* if oob_required, preserve OOB metadata of written subpage */
2310                 if (!oob_required || (step < start_step) || (step > end_step))
2311                         memset(oob_buf, 0xff, oob_bytes);
2312
2313                 buf += ecc_size;
2314                 ecc_calc += ecc_bytes;
2315                 oob_buf  += oob_bytes;
2316         }
2317
2318         /* copy calculated ECC for whole page to chip->buffer->oob */
2319         /* this include masked-value(0xFF) for unwritten subpages */
2320         ecc_calc = chip->buffers->ecccalc;
2321         for (i = 0; i < chip->ecc.total; i++)
2322                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2323
2324         /* write OOB buffer to NAND device */
2325         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2326
2327         return 0;
2328 }
2329
2330
2331 /**
2332  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2333  * @mtd: mtd info structure
2334  * @chip: nand chip info structure
2335  * @buf: data buffer
2336  * @oob_required: must write chip->oob_poi to OOB
2337  *
2338  * The hw generator calculates the error syndrome automatically. Therefore we
2339  * need a special oob layout and handling.
2340  */
2341 static int nand_write_page_syndrome(struct mtd_info *mtd,
2342                                     struct nand_chip *chip,
2343                                     const uint8_t *buf, int oob_required)
2344 {
2345         int i, eccsize = chip->ecc.size;
2346         int eccbytes = chip->ecc.bytes;
2347         int eccsteps = chip->ecc.steps;
2348         const uint8_t *p = buf;
2349         uint8_t *oob = chip->oob_poi;
2350
2351         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2352
2353                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2354                 chip->write_buf(mtd, p, eccsize);
2355
2356                 if (chip->ecc.prepad) {
2357                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2358                         oob += chip->ecc.prepad;
2359                 }
2360
2361                 chip->ecc.calculate(mtd, p, oob);
2362                 chip->write_buf(mtd, oob, eccbytes);
2363                 oob += eccbytes;
2364
2365                 if (chip->ecc.postpad) {
2366                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2367                         oob += chip->ecc.postpad;
2368                 }
2369         }
2370
2371         /* Calculate remaining oob bytes */
2372         i = mtd->oobsize - (oob - chip->oob_poi);
2373         if (i)
2374                 chip->write_buf(mtd, oob, i);
2375
2376         return 0;
2377 }
2378
2379 /**
2380  * nand_write_page - [REPLACEABLE] write one page
2381  * @mtd: MTD device structure
2382  * @chip: NAND chip descriptor
2383  * @offset: address offset within the page
2384  * @data_len: length of actual data to be written
2385  * @buf: the data to write
2386  * @oob_required: must write chip->oob_poi to OOB
2387  * @page: page number to write
2388  * @cached: cached programming
2389  * @raw: use _raw version of write_page
2390  */
2391 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2392                 uint32_t offset, int data_len, const uint8_t *buf,
2393                 int oob_required, int page, int cached, int raw)
2394 {
2395         int status, subpage;
2396
2397         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2398                 chip->ecc.write_subpage)
2399                 subpage = offset || (data_len < mtd->writesize);
2400         else
2401                 subpage = 0;
2402
2403         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2404
2405         if (unlikely(raw))
2406                 status = chip->ecc.write_page_raw(mtd, chip, buf,
2407                                                         oob_required);
2408         else if (subpage)
2409                 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2410                                                          buf, oob_required);
2411         else
2412                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2413
2414         if (status < 0)
2415                 return status;
2416
2417         /*
2418          * Cached progamming disabled for now. Not sure if it's worth the
2419          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2420          */
2421         cached = 0;
2422
2423         if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2424
2425                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2426                 status = chip->waitfunc(mtd, chip);
2427                 /*
2428                  * See if operation failed and additional status checks are
2429                  * available.
2430                  */
2431                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2432                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2433                                                page);
2434
2435                 if (status & NAND_STATUS_FAIL)
2436                         return -EIO;
2437         } else {
2438                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2439                 status = chip->waitfunc(mtd, chip);
2440         }
2441
2442
2443 #ifdef __UBOOT__
2444 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2445         /* Send command to read back the data */
2446         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2447
2448         if (chip->verify_buf(mtd, buf, mtd->writesize))
2449                 return -EIO;
2450
2451         /* Make sure the next page prog is preceded by a status read */
2452         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2453 #endif
2454 #endif
2455
2456         return 0;
2457 }
2458
2459 /**
2460  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2461  * @mtd: MTD device structure
2462  * @oob: oob data buffer
2463  * @len: oob data write length
2464  * @ops: oob ops structure
2465  */
2466 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2467                               struct mtd_oob_ops *ops)
2468 {
2469         struct nand_chip *chip = mtd->priv;
2470
2471         /*
2472          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2473          * data from a previous OOB read.
2474          */
2475         memset(chip->oob_poi, 0xff, mtd->oobsize);
2476
2477         switch (ops->mode) {
2478
2479         case MTD_OPS_PLACE_OOB:
2480         case MTD_OPS_RAW:
2481                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2482                 return oob + len;
2483
2484         case MTD_OPS_AUTO_OOB: {
2485                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2486                 uint32_t boffs = 0, woffs = ops->ooboffs;
2487                 size_t bytes = 0;
2488
2489                 for (; free->length && len; free++, len -= bytes) {
2490                         /* Write request not from offset 0? */
2491                         if (unlikely(woffs)) {
2492                                 if (woffs >= free->length) {
2493                                         woffs -= free->length;
2494                                         continue;
2495                                 }
2496                                 boffs = free->offset + woffs;
2497                                 bytes = min_t(size_t, len,
2498                                               (free->length - woffs));
2499                                 woffs = 0;
2500                         } else {
2501                                 bytes = min_t(size_t, len, free->length);
2502                                 boffs = free->offset;
2503                         }
2504                         memcpy(chip->oob_poi + boffs, oob, bytes);
2505                         oob += bytes;
2506                 }
2507                 return oob;
2508         }
2509         default:
2510                 BUG();
2511         }
2512         return NULL;
2513 }
2514
2515 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2516
2517 /**
2518  * nand_do_write_ops - [INTERN] NAND write with ECC
2519  * @mtd: MTD device structure
2520  * @to: offset to write to
2521  * @ops: oob operations description structure
2522  *
2523  * NAND write with ECC.
2524  */
2525 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2526                              struct mtd_oob_ops *ops)
2527 {
2528         int chipnr, realpage, page, blockmask, column;
2529         struct nand_chip *chip = mtd->priv;
2530         uint32_t writelen = ops->len;
2531
2532         uint32_t oobwritelen = ops->ooblen;
2533         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2534                                 mtd->oobavail : mtd->oobsize;
2535
2536         uint8_t *oob = ops->oobbuf;
2537         uint8_t *buf = ops->datbuf;
2538         int ret;
2539         int oob_required = oob ? 1 : 0;
2540
2541         ops->retlen = 0;
2542         if (!writelen)
2543                 return 0;
2544
2545 #ifndef __UBOOT__
2546         /* Reject writes, which are not page aligned */
2547         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2548 #else
2549         /* Reject writes, which are not page aligned */
2550         if (NOTALIGNED(to)) {
2551 #endif
2552                 pr_notice("%s: attempt to write non page aligned data\n",
2553                            __func__);
2554                 return -EINVAL;
2555         }
2556
2557         column = to & (mtd->writesize - 1);
2558
2559         chipnr = (int)(to >> chip->chip_shift);
2560         chip->select_chip(mtd, chipnr);
2561
2562         /* Check, if it is write protected */
2563         if (nand_check_wp(mtd)) {
2564                 ret = -EIO;
2565                 goto err_out;
2566         }
2567
2568         realpage = (int)(to >> chip->page_shift);
2569         page = realpage & chip->pagemask;
2570         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2571
2572         /* Invalidate the page cache, when we write to the cached page */
2573         if (to <= (chip->pagebuf << chip->page_shift) &&
2574             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2575                 chip->pagebuf = -1;
2576
2577         /* Don't allow multipage oob writes with offset */
2578         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2579                 ret = -EINVAL;
2580                 goto err_out;
2581         }
2582
2583         while (1) {
2584                 int bytes = mtd->writesize;
2585                 int cached = writelen > bytes && page != blockmask;
2586                 uint8_t *wbuf = buf;
2587
2588                 WATCHDOG_RESET();
2589                 /* Partial page write? */
2590                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2591                         cached = 0;
2592                         bytes = min_t(int, bytes - column, (int) writelen);
2593                         chip->pagebuf = -1;
2594                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2595                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2596                         wbuf = chip->buffers->databuf;
2597                 }
2598
2599                 if (unlikely(oob)) {
2600                         size_t len = min(oobwritelen, oobmaxlen);
2601                         oob = nand_fill_oob(mtd, oob, len, ops);
2602                         oobwritelen -= len;
2603                 } else {
2604                         /* We still need to erase leftover OOB data */
2605                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2606                 }
2607                 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2608                                         oob_required, page, cached,
2609                                         (ops->mode == MTD_OPS_RAW));
2610                 if (ret)
2611                         break;
2612
2613                 writelen -= bytes;
2614                 if (!writelen)
2615                         break;
2616
2617                 column = 0;
2618                 buf += bytes;
2619                 realpage++;
2620
2621                 page = realpage & chip->pagemask;
2622                 /* Check, if we cross a chip boundary */
2623                 if (!page) {
2624                         chipnr++;
2625                         chip->select_chip(mtd, -1);
2626                         chip->select_chip(mtd, chipnr);
2627                 }
2628         }
2629
2630         ops->retlen = ops->len - writelen;
2631         if (unlikely(oob))
2632                 ops->oobretlen = ops->ooblen;
2633
2634 err_out:
2635         chip->select_chip(mtd, -1);
2636         return ret;
2637 }
2638
2639 /**
2640  * panic_nand_write - [MTD Interface] NAND write with ECC
2641  * @mtd: MTD device structure
2642  * @to: offset to write to
2643  * @len: number of bytes to write
2644  * @retlen: pointer to variable to store the number of written bytes
2645  * @buf: the data to write
2646  *
2647  * NAND write with ECC. Used when performing writes in interrupt context, this
2648  * may for example be called by mtdoops when writing an oops while in panic.
2649  */
2650 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2651                             size_t *retlen, const uint8_t *buf)
2652 {
2653         struct nand_chip *chip = mtd->priv;
2654         struct mtd_oob_ops ops;
2655         int ret;
2656
2657         /* Wait for the device to get ready */
2658         panic_nand_wait(mtd, chip, 400);
2659
2660         /* Grab the device */
2661         panic_nand_get_device(chip, mtd, FL_WRITING);
2662
2663         ops.len = len;
2664         ops.datbuf = (uint8_t *)buf;
2665         ops.oobbuf = NULL;
2666         ops.mode = MTD_OPS_PLACE_OOB;
2667
2668         ret = nand_do_write_ops(mtd, to, &ops);
2669
2670         *retlen = ops.retlen;
2671         return ret;
2672 }
2673
2674 /**
2675  * nand_write - [MTD Interface] NAND write with ECC
2676  * @mtd: MTD device structure
2677  * @to: offset to write to
2678  * @len: number of bytes to write
2679  * @retlen: pointer to variable to store the number of written bytes
2680  * @buf: the data to write
2681  *
2682  * NAND write with ECC.
2683  */
2684 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2685                           size_t *retlen, const uint8_t *buf)
2686 {
2687         struct mtd_oob_ops ops;
2688         int ret;
2689
2690         nand_get_device(mtd, FL_WRITING);
2691         ops.len = len;
2692         ops.datbuf = (uint8_t *)buf;
2693         ops.oobbuf = NULL;
2694         ops.mode = MTD_OPS_PLACE_OOB;
2695         ret = nand_do_write_ops(mtd, to, &ops);
2696         *retlen = ops.retlen;
2697         nand_release_device(mtd);
2698         return ret;
2699 }
2700
2701 /**
2702  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2703  * @mtd: MTD device structure
2704  * @to: offset to write to
2705  * @ops: oob operation description structure
2706  *
2707  * NAND write out-of-band.
2708  */
2709 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2710                              struct mtd_oob_ops *ops)
2711 {
2712         int chipnr, page, status, len;
2713         struct nand_chip *chip = mtd->priv;
2714
2715         pr_debug("%s: to = 0x%08x, len = %i\n",
2716                          __func__, (unsigned int)to, (int)ops->ooblen);
2717
2718         if (ops->mode == MTD_OPS_AUTO_OOB)
2719                 len = chip->ecc.layout->oobavail;
2720         else
2721                 len = mtd->oobsize;
2722
2723         /* Do not allow write past end of page */
2724         if ((ops->ooboffs + ops->ooblen) > len) {
2725                 pr_debug("%s: attempt to write past end of page\n",
2726                                 __func__);
2727                 return -EINVAL;
2728         }
2729
2730         if (unlikely(ops->ooboffs >= len)) {
2731                 pr_debug("%s: attempt to start write outside oob\n",
2732                                 __func__);
2733                 return -EINVAL;
2734         }
2735
2736         /* Do not allow write past end of device */
2737         if (unlikely(to >= mtd->size ||
2738                      ops->ooboffs + ops->ooblen >
2739                         ((mtd->size >> chip->page_shift) -
2740                          (to >> chip->page_shift)) * len)) {
2741                 pr_debug("%s: attempt to write beyond end of device\n",
2742                                 __func__);
2743                 return -EINVAL;
2744         }
2745
2746         chipnr = (int)(to >> chip->chip_shift);
2747         chip->select_chip(mtd, chipnr);
2748
2749         /* Shift to get page */
2750         page = (int)(to >> chip->page_shift);
2751
2752         /*
2753          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2754          * of my DiskOnChip 2000 test units) will clear the whole data page too
2755          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2756          * it in the doc2000 driver in August 1999.  dwmw2.
2757          */
2758         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2759
2760         /* Check, if it is write protected */
2761         if (nand_check_wp(mtd)) {
2762                 chip->select_chip(mtd, -1);
2763                 return -EROFS;
2764         }
2765
2766         /* Invalidate the page cache, if we write to the cached page */
2767         if (page == chip->pagebuf)
2768                 chip->pagebuf = -1;
2769
2770         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2771
2772         if (ops->mode == MTD_OPS_RAW)
2773                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2774         else
2775                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2776
2777         chip->select_chip(mtd, -1);
2778
2779         if (status)
2780                 return status;
2781
2782         ops->oobretlen = ops->ooblen;
2783
2784         return 0;
2785 }
2786
2787 /**
2788  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2789  * @mtd: MTD device structure
2790  * @to: offset to write to
2791  * @ops: oob operation description structure
2792  */
2793 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2794                           struct mtd_oob_ops *ops)
2795 {
2796         int ret = -ENOTSUPP;
2797
2798         ops->retlen = 0;
2799
2800         /* Do not allow writes past end of device */
2801         if (ops->datbuf && (to + ops->len) > mtd->size) {
2802                 pr_debug("%s: attempt to write beyond end of device\n",
2803                                 __func__);
2804                 return -EINVAL;
2805         }
2806
2807         nand_get_device(mtd, FL_WRITING);
2808
2809         switch (ops->mode) {
2810         case MTD_OPS_PLACE_OOB:
2811         case MTD_OPS_AUTO_OOB:
2812         case MTD_OPS_RAW:
2813                 break;
2814
2815         default:
2816                 goto out;
2817         }
2818
2819         if (!ops->datbuf)
2820                 ret = nand_do_write_oob(mtd, to, ops);
2821         else
2822                 ret = nand_do_write_ops(mtd, to, ops);
2823
2824 out:
2825         nand_release_device(mtd);
2826         return ret;
2827 }
2828
2829 /**
2830  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2831  * @mtd: MTD device structure
2832  * @page: the page address of the block which will be erased
2833  *
2834  * Standard erase command for NAND chips.
2835  */
2836 static void single_erase_cmd(struct mtd_info *mtd, int page)
2837 {
2838         struct nand_chip *chip = mtd->priv;
2839         /* Send commands to erase a block */
2840         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2841         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2842 }
2843
2844 /**
2845  * nand_erase - [MTD Interface] erase block(s)
2846  * @mtd: MTD device structure
2847  * @instr: erase instruction
2848  *
2849  * Erase one ore more blocks.
2850  */
2851 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2852 {
2853         return nand_erase_nand(mtd, instr, 0);
2854 }
2855
2856 /**
2857  * nand_erase_nand - [INTERN] erase block(s)
2858  * @mtd: MTD device structure
2859  * @instr: erase instruction
2860  * @allowbbt: allow erasing the bbt area
2861  *
2862  * Erase one ore more blocks.
2863  */
2864 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2865                     int allowbbt)
2866 {
2867         int page, status, pages_per_block, ret, chipnr;
2868         struct nand_chip *chip = mtd->priv;
2869         loff_t len;
2870
2871         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2872                         __func__, (unsigned long long)instr->addr,
2873                         (unsigned long long)instr->len);
2874
2875         if (check_offs_len(mtd, instr->addr, instr->len))
2876                 return -EINVAL;
2877
2878         /* Grab the lock and see if the device is available */
2879         nand_get_device(mtd, FL_ERASING);
2880
2881         /* Shift to get first page */
2882         page = (int)(instr->addr >> chip->page_shift);
2883         chipnr = (int)(instr->addr >> chip->chip_shift);
2884
2885         /* Calculate pages in each block */
2886         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2887
2888         /* Select the NAND device */
2889         chip->select_chip(mtd, chipnr);
2890
2891         /* Check, if it is write protected */
2892         if (nand_check_wp(mtd)) {
2893                 pr_debug("%s: device is write protected!\n",
2894                                 __func__);
2895                 instr->state = MTD_ERASE_FAILED;
2896                 goto erase_exit;
2897         }
2898
2899         /* Loop through the pages */
2900         len = instr->len;
2901
2902         instr->state = MTD_ERASING;
2903
2904         while (len) {
2905                 WATCHDOG_RESET();
2906
2907                 /* Check if we have a bad block, we do not erase bad blocks! */
2908                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2909                                         chip->page_shift, 0, allowbbt)) {
2910                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2911                                     __func__, page);
2912                         instr->state = MTD_ERASE_FAILED;
2913                         goto erase_exit;
2914                 }
2915
2916                 /*
2917                  * Invalidate the page cache, if we erase the block which
2918                  * contains the current cached page.
2919                  */
2920                 if (page <= chip->pagebuf && chip->pagebuf <
2921                     (page + pages_per_block))
2922                         chip->pagebuf = -1;
2923
2924                 chip->erase_cmd(mtd, page & chip->pagemask);
2925
2926                 status = chip->waitfunc(mtd, chip);
2927
2928                 /*
2929                  * See if operation failed and additional status checks are
2930                  * available
2931                  */
2932                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2933                         status = chip->errstat(mtd, chip, FL_ERASING,
2934                                                status, page);
2935
2936                 /* See if block erase succeeded */
2937                 if (status & NAND_STATUS_FAIL) {
2938                         pr_debug("%s: failed erase, page 0x%08x\n",
2939                                         __func__, page);
2940                         instr->state = MTD_ERASE_FAILED;
2941                         instr->fail_addr =
2942                                 ((loff_t)page << chip->page_shift);
2943                         goto erase_exit;
2944                 }
2945
2946                 /* Increment page address and decrement length */
2947                 len -= (1ULL << chip->phys_erase_shift);
2948                 page += pages_per_block;
2949
2950                 /* Check, if we cross a chip boundary */
2951                 if (len && !(page & chip->pagemask)) {
2952                         chipnr++;
2953                         chip->select_chip(mtd, -1);
2954                         chip->select_chip(mtd, chipnr);
2955                 }
2956         }
2957         instr->state = MTD_ERASE_DONE;
2958
2959 erase_exit:
2960
2961         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2962
2963         /* Deselect and wake up anyone waiting on the device */
2964         chip->select_chip(mtd, -1);
2965         nand_release_device(mtd);
2966
2967         /* Do call back function */
2968         if (!ret)
2969                 mtd_erase_callback(instr);
2970
2971         /* Return more or less happy */
2972         return ret;
2973 }
2974
2975 /**
2976  * nand_sync - [MTD Interface] sync
2977  * @mtd: MTD device structure
2978  *
2979  * Sync is actually a wait for chip ready function.
2980  */
2981 static void nand_sync(struct mtd_info *mtd)
2982 {
2983         pr_debug("%s: called\n", __func__);
2984
2985         /* Grab the lock and see if the device is available */
2986         nand_get_device(mtd, FL_SYNCING);
2987         /* Release it and go back */
2988         nand_release_device(mtd);
2989 }
2990
2991 /**
2992  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2993  * @mtd: MTD device structure
2994  * @offs: offset relative to mtd start
2995  */
2996 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2997 {
2998         return nand_block_checkbad(mtd, offs, 1, 0);
2999 }
3000
3001 /**
3002  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3003  * @mtd: MTD device structure
3004  * @ofs: offset relative to mtd start
3005  */
3006 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3007 {
3008         int ret;
3009
3010         ret = nand_block_isbad(mtd, ofs);
3011         if (ret) {
3012                 /* If it was bad already, return success and do nothing */
3013                 if (ret > 0)
3014                         return 0;
3015                 return ret;
3016         }
3017
3018         return nand_block_markbad_lowlevel(mtd, ofs);
3019 }
3020
3021 /**
3022  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3023  * @mtd: MTD device structure
3024  * @chip: nand chip info structure
3025  * @addr: feature address.
3026  * @subfeature_param: the subfeature parameters, a four bytes array.
3027  */
3028 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3029                         int addr, uint8_t *subfeature_param)
3030 {
3031         int status;
3032         int i;
3033
3034 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3035         if (!chip->onfi_version ||
3036             !(le16_to_cpu(chip->onfi_params.opt_cmd)
3037               & ONFI_OPT_CMD_SET_GET_FEATURES))
3038                 return -EINVAL;
3039 #endif
3040
3041         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3042         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3043                 chip->write_byte(mtd, subfeature_param[i]);
3044
3045         status = chip->waitfunc(mtd, chip);
3046         if (status & NAND_STATUS_FAIL)
3047                 return -EIO;
3048         return 0;
3049 }
3050
3051 /**
3052  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3053  * @mtd: MTD device structure
3054  * @chip: nand chip info structure
3055  * @addr: feature address.
3056  * @subfeature_param: the subfeature parameters, a four bytes array.
3057  */
3058 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3059                         int addr, uint8_t *subfeature_param)
3060 {
3061         int i;
3062
3063 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3064         if (!chip->onfi_version ||
3065             !(le16_to_cpu(chip->onfi_params.opt_cmd)
3066               & ONFI_OPT_CMD_SET_GET_FEATURES))
3067                 return -EINVAL;
3068 #endif
3069
3070         /* clear the sub feature parameters */
3071         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3072
3073         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3074         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3075                 *subfeature_param++ = chip->read_byte(mtd);
3076         return 0;
3077 }
3078
3079 #ifndef __UBOOT__
3080 /**
3081  * nand_suspend - [MTD Interface] Suspend the NAND flash
3082  * @mtd: MTD device structure
3083  */
3084 static int nand_suspend(struct mtd_info *mtd)
3085 {
3086         return nand_get_device(mtd, FL_PM_SUSPENDED);
3087 }
3088
3089 /**
3090  * nand_resume - [MTD Interface] Resume the NAND flash
3091  * @mtd: MTD device structure
3092  */
3093 static void nand_resume(struct mtd_info *mtd)
3094 {
3095         struct nand_chip *chip = mtd->priv;
3096
3097         if (chip->state == FL_PM_SUSPENDED)
3098                 nand_release_device(mtd);
3099         else
3100                 pr_err("%s called for a chip which is not in suspended state\n",
3101                         __func__);
3102 }
3103 #endif
3104
3105 /* Set default functions */
3106 static void nand_set_defaults(struct nand_chip *chip, int busw)
3107 {
3108         /* check for proper chip_delay setup, set 20us if not */
3109         if (!chip->chip_delay)
3110                 chip->chip_delay = 20;
3111
3112         /* check, if a user supplied command function given */
3113         if (chip->cmdfunc == NULL)
3114                 chip->cmdfunc = nand_command;
3115
3116         /* check, if a user supplied wait function given */
3117         if (chip->waitfunc == NULL)
3118                 chip->waitfunc = nand_wait;
3119
3120         if (!chip->select_chip)
3121                 chip->select_chip = nand_select_chip;
3122
3123         /* set for ONFI nand */
3124         if (!chip->onfi_set_features)
3125                 chip->onfi_set_features = nand_onfi_set_features;
3126         if (!chip->onfi_get_features)
3127                 chip->onfi_get_features = nand_onfi_get_features;
3128
3129         /* If called twice, pointers that depend on busw may need to be reset */
3130         if (!chip->read_byte || chip->read_byte == nand_read_byte)
3131                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3132         if (!chip->read_word)
3133                 chip->read_word = nand_read_word;
3134         if (!chip->block_bad)
3135                 chip->block_bad = nand_block_bad;
3136         if (!chip->block_markbad)
3137                 chip->block_markbad = nand_default_block_markbad;
3138         if (!chip->write_buf || chip->write_buf == nand_write_buf)
3139                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3140         if (!chip->write_byte || chip->write_byte == nand_write_byte)
3141                 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3142         if (!chip->read_buf || chip->read_buf == nand_read_buf)
3143                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3144         if (!chip->scan_bbt)
3145                 chip->scan_bbt = nand_default_bbt;
3146 #ifdef __UBOOT__
3147 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3148         if (!chip->verify_buf)
3149                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3150 #endif
3151 #endif
3152
3153         if (!chip->controller) {
3154                 chip->controller = &chip->hwcontrol;
3155                 spin_lock_init(&chip->controller->lock);
3156                 init_waitqueue_head(&chip->controller->wq);
3157         }
3158
3159 }
3160
3161 /* Sanitize ONFI strings so we can safely print them */
3162 #ifndef __UBOOT__
3163 static void sanitize_string(uint8_t *s, size_t len)
3164 #else
3165 static void sanitize_string(char *s, size_t len)
3166 #endif
3167 {
3168         ssize_t i;
3169
3170         /* Null terminate */
3171         s[len - 1] = 0;
3172
3173         /* Remove non printable chars */
3174         for (i = 0; i < len - 1; i++) {
3175                 if (s[i] < ' ' || s[i] > 127)
3176                         s[i] = '?';
3177         }
3178
3179         /* Remove trailing spaces */
3180         strim(s);
3181 }
3182
3183 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3184 {
3185         int i;
3186         while (len--) {
3187                 crc ^= *p++ << 8;
3188                 for (i = 0; i < 8; i++)
3189                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3190         }
3191
3192         return crc;
3193 }
3194
3195 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3196 /* Parse the Extended Parameter Page. */
3197 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3198                 struct nand_chip *chip, struct nand_onfi_params *p)
3199 {
3200         struct onfi_ext_param_page *ep;
3201         struct onfi_ext_section *s;
3202         struct onfi_ext_ecc_info *ecc;
3203         uint8_t *cursor;
3204         int ret = -EINVAL;
3205         int len;
3206         int i;
3207
3208         len = le16_to_cpu(p->ext_param_page_length) * 16;
3209         ep = kmalloc(len, GFP_KERNEL);
3210         if (!ep)
3211                 return -ENOMEM;
3212
3213         /* Send our own NAND_CMD_PARAM. */
3214         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3215
3216         /* Use the Change Read Column command to skip the ONFI param pages. */
3217         chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3218                         sizeof(*p) * p->num_of_param_pages , -1);
3219
3220         /* Read out the Extended Parameter Page. */
3221         chip->read_buf(mtd, (uint8_t *)ep, len);
3222         if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3223                 != le16_to_cpu(ep->crc))) {
3224                 pr_debug("fail in the CRC.\n");
3225                 goto ext_out;
3226         }
3227
3228         /*
3229          * Check the signature.
3230          * Do not strictly follow the ONFI spec, maybe changed in future.
3231          */
3232 #ifndef __UBOOT__
3233         if (strncmp(ep->sig, "EPPS", 4)) {
3234 #else
3235         if (strncmp((char *)ep->sig, "EPPS", 4)) {
3236 #endif
3237                 pr_debug("The signature is invalid.\n");
3238                 goto ext_out;
3239         }
3240
3241         /* find the ECC section. */
3242         cursor = (uint8_t *)(ep + 1);
3243         for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3244                 s = ep->sections + i;
3245                 if (s->type == ONFI_SECTION_TYPE_2)
3246                         break;
3247                 cursor += s->length * 16;
3248         }
3249         if (i == ONFI_EXT_SECTION_MAX) {
3250                 pr_debug("We can not find the ECC section.\n");
3251                 goto ext_out;
3252         }
3253
3254         /* get the info we want. */
3255         ecc = (struct onfi_ext_ecc_info *)cursor;
3256
3257         if (!ecc->codeword_size) {
3258                 pr_debug("Invalid codeword size\n");
3259                 goto ext_out;
3260         }
3261
3262         chip->ecc_strength_ds = ecc->ecc_bits;
3263         chip->ecc_step_ds = 1 << ecc->codeword_size;
3264         ret = 0;
3265
3266 ext_out:
3267         kfree(ep);
3268         return ret;
3269 }
3270
3271 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3272 {
3273         struct nand_chip *chip = mtd->priv;
3274         uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3275
3276         return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3277                         feature);
3278 }
3279
3280 /*
3281  * Configure chip properties from Micron vendor-specific ONFI table
3282  */
3283 static void nand_onfi_detect_micron(struct nand_chip *chip,
3284                 struct nand_onfi_params *p)
3285 {
3286         struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3287
3288         if (le16_to_cpu(p->vendor_revision) < 1)
3289                 return;
3290
3291         chip->read_retries = micron->read_retry_options;
3292         chip->setup_read_retry = nand_setup_read_retry_micron;
3293 }
3294
3295 /*
3296  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3297  */
3298 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3299                                         int *busw)
3300 {
3301         struct nand_onfi_params *p = &chip->onfi_params;
3302         int i, j;
3303         int val;
3304
3305         /* Try ONFI for unknown chip or LP */
3306         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3307         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3308                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3309                 return 0;
3310
3311         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3312         for (i = 0; i < 3; i++) {
3313                 for (j = 0; j < sizeof(*p); j++)
3314                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3315                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3316                                 le16_to_cpu(p->crc)) {
3317                         break;
3318                 }
3319         }
3320
3321         if (i == 3) {
3322                 pr_err("Could not find valid ONFI parameter page; aborting\n");
3323                 return 0;
3324         }
3325
3326         /* Check version */
3327         val = le16_to_cpu(p->revision);
3328         if (val & (1 << 5))
3329                 chip->onfi_version = 23;
3330         else if (val & (1 << 4))
3331                 chip->onfi_version = 22;
3332         else if (val & (1 << 3))
3333                 chip->onfi_version = 21;
3334         else if (val & (1 << 2))
3335                 chip->onfi_version = 20;
3336         else if (val & (1 << 1))
3337                 chip->onfi_version = 10;
3338
3339         if (!chip->onfi_version) {
3340                 pr_info("unsupported ONFI version: %d\n", val);
3341                 return 0;
3342         }
3343
3344         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3345         sanitize_string(p->model, sizeof(p->model));
3346         if (!mtd->name)
3347                 mtd->name = p->model;
3348
3349         mtd->writesize = le32_to_cpu(p->byte_per_page);
3350
3351         /*
3352          * pages_per_block and blocks_per_lun may not be a power-of-2 size
3353          * (don't ask me who thought of this...). MTD assumes that these
3354          * dimensions will be power-of-2, so just truncate the remaining area.
3355          */
3356         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3357         mtd->erasesize *= mtd->writesize;
3358
3359         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3360
3361         /* See erasesize comment */
3362         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3363         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3364         chip->bits_per_cell = p->bits_per_cell;
3365
3366         if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3367                 *busw = NAND_BUSWIDTH_16;
3368         else
3369                 *busw = 0;
3370
3371         if (p->ecc_bits != 0xff) {
3372                 chip->ecc_strength_ds = p->ecc_bits;
3373                 chip->ecc_step_ds = 512;
3374         } else if (chip->onfi_version >= 21 &&
3375                 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3376
3377                 /*
3378                  * The nand_flash_detect_ext_param_page() uses the
3379                  * Change Read Column command which maybe not supported
3380                  * by the chip->cmdfunc. So try to update the chip->cmdfunc
3381                  * now. We do not replace user supplied command function.
3382                  */
3383                 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3384                         chip->cmdfunc = nand_command_lp;
3385
3386                 /* The Extended Parameter Page is supported since ONFI 2.1. */
3387                 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3388                         pr_warn("Failed to detect ONFI extended param page\n");
3389         } else {
3390                 pr_warn("Could not retrieve ONFI ECC requirements\n");
3391         }
3392
3393         if (p->jedec_id == NAND_MFR_MICRON)
3394                 nand_onfi_detect_micron(chip, p);
3395
3396         return 1;
3397 }
3398 #else
3399 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3400                                         int *busw)
3401 {
3402         return 0;
3403 }
3404 #endif
3405
3406 /*
3407  * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3408  */
3409 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3410                                         int *busw)
3411 {
3412         struct nand_jedec_params *p = &chip->jedec_params;
3413         struct jedec_ecc_info *ecc;
3414         int val;
3415         int i, j;
3416
3417         /* Try JEDEC for unknown chip or LP */
3418         chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3419         if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3420                 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3421                 chip->read_byte(mtd) != 'C')
3422                 return 0;
3423
3424         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3425         for (i = 0; i < 3; i++) {
3426                 for (j = 0; j < sizeof(*p); j++)
3427                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3428
3429                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3430                                 le16_to_cpu(p->crc))
3431                         break;
3432         }
3433
3434         if (i == 3) {
3435                 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3436                 return 0;
3437         }
3438
3439         /* Check version */
3440         val = le16_to_cpu(p->revision);
3441         if (val & (1 << 2))
3442                 chip->jedec_version = 10;
3443         else if (val & (1 << 1))
3444                 chip->jedec_version = 1; /* vendor specific version */
3445
3446         if (!chip->jedec_version) {
3447                 pr_info("unsupported JEDEC version: %d\n", val);
3448                 return 0;
3449         }
3450
3451         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3452         sanitize_string(p->model, sizeof(p->model));
3453         if (!mtd->name)
3454                 mtd->name = p->model;
3455
3456         mtd->writesize = le32_to_cpu(p->byte_per_page);
3457
3458         /* Please reference to the comment for nand_flash_detect_onfi. */
3459         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3460         mtd->erasesize *= mtd->writesize;
3461
3462         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3463
3464         /* Please reference to the comment for nand_flash_detect_onfi. */
3465         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3466         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3467         chip->bits_per_cell = p->bits_per_cell;
3468
3469         if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3470                 *busw = NAND_BUSWIDTH_16;
3471         else
3472                 *busw = 0;
3473
3474         /* ECC info */
3475         ecc = &p->ecc_info[0];
3476
3477         if (ecc->codeword_size >= 9) {
3478                 chip->ecc_strength_ds = ecc->ecc_bits;
3479                 chip->ecc_step_ds = 1 << ecc->codeword_size;
3480         } else {
3481                 pr_warn("Invalid codeword size\n");
3482         }
3483
3484         return 1;
3485 }
3486
3487 /*
3488  * nand_id_has_period - Check if an ID string has a given wraparound period
3489  * @id_data: the ID string
3490  * @arrlen: the length of the @id_data array
3491  * @period: the period of repitition
3492  *
3493  * Check if an ID string is repeated within a given sequence of bytes at
3494  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3495  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3496  * if the repetition has a period of @period; otherwise, returns zero.
3497  */
3498 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3499 {
3500         int i, j;
3501         for (i = 0; i < period; i++)
3502                 for (j = i + period; j < arrlen; j += period)
3503                         if (id_data[i] != id_data[j])
3504                                 return 0;
3505         return 1;
3506 }
3507
3508 /*
3509  * nand_id_len - Get the length of an ID string returned by CMD_READID
3510  * @id_data: the ID string
3511  * @arrlen: the length of the @id_data array
3512
3513  * Returns the length of the ID string, according to known wraparound/trailing
3514  * zero patterns. If no pattern exists, returns the length of the array.
3515  */
3516 static int nand_id_len(u8 *id_data, int arrlen)
3517 {
3518         int last_nonzero, period;
3519
3520         /* Find last non-zero byte */
3521         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3522                 if (id_data[last_nonzero])
3523                         break;
3524
3525         /* All zeros */
3526         if (last_nonzero < 0)
3527                 return 0;
3528
3529         /* Calculate wraparound period */
3530         for (period = 1; period < arrlen; period++)
3531                 if (nand_id_has_period(id_data, arrlen, period))
3532                         break;
3533
3534         /* There's a repeated pattern */
3535         if (period < arrlen)
3536                 return period;
3537
3538         /* There are trailing zeros */
3539         if (last_nonzero < arrlen - 1)
3540                 return last_nonzero + 1;
3541
3542         /* No pattern detected */
3543         return arrlen;
3544 }
3545
3546 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3547 static int nand_get_bits_per_cell(u8 cellinfo)
3548 {
3549         int bits;
3550
3551         bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3552         bits >>= NAND_CI_CELLTYPE_SHIFT;
3553         return bits + 1;
3554 }
3555
3556 /*
3557  * Many new NAND share similar device ID codes, which represent the size of the
3558  * chip. The rest of the parameters must be decoded according to generic or
3559  * manufacturer-specific "extended ID" decoding patterns.
3560  */
3561 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3562                                 u8 id_data[8], int *busw)
3563 {
3564         int extid, id_len;
3565         /* The 3rd id byte holds MLC / multichip data */
3566         chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3567         /* The 4th id byte is the important one */
3568         extid = id_data[3];
3569
3570         id_len = nand_id_len(id_data, 8);
3571
3572         /*
3573          * Field definitions are in the following datasheets:
3574          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3575          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3576          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
3577          *
3578          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3579          * ID to decide what to do.
3580          */
3581         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3582                         !nand_is_slc(chip) && id_data[5] != 0x00) {
3583                 /* Calc pagesize */
3584                 mtd->writesize = 2048 << (extid & 0x03);
3585                 extid >>= 2;
3586                 /* Calc oobsize */
3587                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3588                 case 1:
3589                         mtd->oobsize = 128;
3590                         break;
3591                 case 2:
3592                         mtd->oobsize = 218;
3593                         break;
3594                 case 3:
3595                         mtd->oobsize = 400;
3596                         break;
3597                 case 4:
3598                         mtd->oobsize = 436;
3599                         break;
3600                 case 5:
3601                         mtd->oobsize = 512;
3602                         break;
3603                 case 6:
3604                         mtd->oobsize = 640;
3605                         break;
3606                 case 7:
3607                 default: /* Other cases are "reserved" (unknown) */
3608                         mtd->oobsize = 1024;
3609                         break;
3610                 }
3611                 extid >>= 2;
3612                 /* Calc blocksize */
3613                 mtd->erasesize = (128 * 1024) <<
3614                         (((extid >> 1) & 0x04) | (extid & 0x03));
3615                 *busw = 0;
3616         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3617                         !nand_is_slc(chip)) {
3618                 unsigned int tmp;
3619
3620                 /* Calc pagesize */
3621                 mtd->writesize = 2048 << (extid & 0x03);
3622                 extid >>= 2;
3623                 /* Calc oobsize */
3624                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3625                 case 0:
3626                         mtd->oobsize = 128;
3627                         break;
3628                 case 1:
3629                         mtd->oobsize = 224;
3630                         break;
3631                 case 2:
3632                         mtd->oobsize = 448;
3633                         break;
3634                 case 3:
3635                         mtd->oobsize = 64;
3636                         break;
3637                 case 4:
3638                         mtd->oobsize = 32;
3639                         break;
3640                 case 5:
3641                         mtd->oobsize = 16;
3642                         break;
3643                 default:
3644                         mtd->oobsize = 640;
3645                         break;
3646                 }
3647                 extid >>= 2;
3648                 /* Calc blocksize */
3649                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3650                 if (tmp < 0x03)
3651                         mtd->erasesize = (128 * 1024) << tmp;
3652                 else if (tmp == 0x03)
3653                         mtd->erasesize = 768 * 1024;
3654                 else
3655                         mtd->erasesize = (64 * 1024) << tmp;
3656                 *busw = 0;
3657         } else {
3658                 /* Calc pagesize */
3659                 mtd->writesize = 1024 << (extid & 0x03);
3660                 extid >>= 2;
3661                 /* Calc oobsize */
3662                 mtd->oobsize = (8 << (extid & 0x01)) *
3663                         (mtd->writesize >> 9);
3664                 extid >>= 2;
3665                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3666                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3667                 extid >>= 2;
3668                 /* Get buswidth information */
3669                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3670
3671                 /*
3672                  * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3673                  * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3674                  * follows:
3675                  * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3676                  *                         110b -> 24nm
3677                  * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
3678                  */
3679                 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3680                                 nand_is_slc(chip) &&
3681                                 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3682                                 !(id_data[4] & 0x80) /* !BENAND */) {
3683                         mtd->oobsize = 32 * mtd->writesize >> 9;
3684                 }
3685
3686         }
3687 }
3688
3689 /*
3690  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3691  * decodes a matching ID table entry and assigns the MTD size parameters for
3692  * the chip.
3693  */
3694 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3695                                 struct nand_flash_dev *type, u8 id_data[8],
3696                                 int *busw)
3697 {
3698         int maf_id = id_data[0];
3699
3700         mtd->erasesize = type->erasesize;
3701         mtd->writesize = type->pagesize;
3702         mtd->oobsize = mtd->writesize / 32;
3703         *busw = type->options & NAND_BUSWIDTH_16;
3704
3705         /* All legacy ID NAND are small-page, SLC */
3706         chip->bits_per_cell = 1;
3707
3708         /*
3709          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3710          * some Spansion chips have erasesize that conflicts with size
3711          * listed in nand_ids table.
3712          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3713          */
3714         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3715                         && id_data[6] == 0x00 && id_data[7] == 0x00
3716                         && mtd->writesize == 512) {
3717                 mtd->erasesize = 128 * 1024;
3718                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3719         }
3720 }
3721
3722 /*
3723  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3724  * heuristic patterns using various detected parameters (e.g., manufacturer,
3725  * page size, cell-type information).
3726  */
3727 static void nand_decode_bbm_options(struct mtd_info *mtd,
3728                                     struct nand_chip *chip, u8 id_data[8])
3729 {
3730         int maf_id = id_data[0];
3731
3732         /* Set the bad block position */
3733         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3734                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3735         else
3736                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3737
3738         /*
3739          * Bad block marker is stored in the last page of each block on Samsung
3740          * and Hynix MLC devices; stored in first two pages of each block on
3741          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3742          * AMD/Spansion, and Macronix.  All others scan only the first page.
3743          */
3744         if (!nand_is_slc(chip) &&
3745                         (maf_id == NAND_MFR_SAMSUNG ||
3746                          maf_id == NAND_MFR_HYNIX))
3747                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3748         else if ((nand_is_slc(chip) &&
3749                                 (maf_id == NAND_MFR_SAMSUNG ||
3750                                  maf_id == NAND_MFR_HYNIX ||
3751                                  maf_id == NAND_MFR_TOSHIBA ||
3752                                  maf_id == NAND_MFR_AMD ||
3753                                  maf_id == NAND_MFR_MACRONIX)) ||
3754                         (mtd->writesize == 2048 &&
3755                          maf_id == NAND_MFR_MICRON))
3756                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3757 }
3758
3759 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3760 {
3761         return type->id_len;
3762 }
3763
3764 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3765                    struct nand_flash_dev *type, u8 *id_data, int *busw)
3766 {
3767 #ifndef __UBOOT__
3768         if (!strncmp(type->id, id_data, type->id_len)) {
3769 #else
3770         if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3771 #endif
3772                 mtd->writesize = type->pagesize;
3773                 mtd->erasesize = type->erasesize;
3774                 mtd->oobsize = type->oobsize;
3775
3776                 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3777                 chip->chipsize = (uint64_t)type->chipsize << 20;
3778                 chip->options |= type->options;
3779                 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3780                 chip->ecc_step_ds = NAND_ECC_STEP(type);
3781
3782                 *busw = type->options & NAND_BUSWIDTH_16;
3783
3784                 if (!mtd->name)
3785                         mtd->name = type->name;
3786
3787                 return true;
3788         }
3789         return false;
3790 }
3791
3792 /*
3793  * Get the flash and manufacturer id and lookup if the type is supported.
3794  */
3795 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3796                                                   struct nand_chip *chip,
3797                                                   int *maf_id, int *dev_id,
3798                                                   struct nand_flash_dev *type)
3799 {
3800         int busw;
3801         int i, maf_idx;
3802         u8 id_data[8];
3803
3804         /* Select the device */
3805         chip->select_chip(mtd, 0);
3806
3807         /*
3808          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3809          * after power-up.
3810          */
3811         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3812
3813         /* Send the command for reading device ID */
3814         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3815
3816         /* Read manufacturer and device IDs */
3817         *maf_id = chip->read_byte(mtd);
3818         *dev_id = chip->read_byte(mtd);
3819
3820         /*
3821          * Try again to make sure, as some systems the bus-hold or other
3822          * interface concerns can cause random data which looks like a
3823          * possibly credible NAND flash to appear. If the two results do
3824          * not match, ignore the device completely.
3825          */
3826
3827         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3828
3829         /* Read entire ID string */
3830         for (i = 0; i < 8; i++)
3831                 id_data[i] = chip->read_byte(mtd);
3832
3833         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3834                 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3835                         *maf_id, *dev_id, id_data[0], id_data[1]);
3836                 return ERR_PTR(-ENODEV);
3837         }
3838
3839         if (!type)
3840                 type = nand_flash_ids;
3841
3842         for (; type->name != NULL; type++) {
3843                 if (is_full_id_nand(type)) {
3844                         if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3845                                 goto ident_done;
3846                 } else if (*dev_id == type->dev_id) {
3847                                 break;
3848                 }
3849         }
3850
3851         chip->onfi_version = 0;
3852         if (!type->name || !type->pagesize) {
3853                 /* Check is chip is ONFI compliant */
3854                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3855                         goto ident_done;
3856
3857                 /* Check if the chip is JEDEC compliant */
3858                 if (nand_flash_detect_jedec(mtd, chip, &busw))
3859                         goto ident_done;
3860         }
3861
3862         if (!type->name)
3863                 return ERR_PTR(-ENODEV);
3864
3865         if (!mtd->name)
3866                 mtd->name = type->name;
3867
3868         chip->chipsize = (uint64_t)type->chipsize << 20;
3869
3870         if (!type->pagesize && chip->init_size) {
3871                 /* Set the pagesize, oobsize, erasesize by the driver */
3872                 busw = chip->init_size(mtd, chip, id_data);
3873         } else if (!type->pagesize) {
3874                 /* Decode parameters from extended ID */
3875                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3876         } else {
3877                 nand_decode_id(mtd, chip, type, id_data, &busw);
3878         }
3879         /* Get chip options */
3880         chip->options |= type->options;
3881
3882         /*
3883          * Check if chip is not a Samsung device. Do not clear the
3884          * options for chips which do not have an extended id.
3885          */
3886         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3887                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3888 ident_done:
3889
3890         /* Try to identify manufacturer */
3891         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3892                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3893                         break;
3894         }
3895
3896         if (chip->options & NAND_BUSWIDTH_AUTO) {
3897                 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3898                 chip->options |= busw;
3899                 nand_set_defaults(chip, busw);
3900         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3901                 /*
3902                  * Check, if buswidth is correct. Hardware drivers should set
3903                  * chip correct!
3904                  */
3905                 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3906                         *maf_id, *dev_id);
3907                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3908                 pr_warn("bus width %d instead %d bit\n",
3909                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3910                            busw ? 16 : 8);
3911                 return ERR_PTR(-EINVAL);
3912         }
3913
3914         nand_decode_bbm_options(mtd, chip, id_data);
3915
3916         /* Calculate the address shift from the page size */
3917         chip->page_shift = ffs(mtd->writesize) - 1;
3918         /* Convert chipsize to number of pages per chip -1 */
3919         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3920
3921         chip->bbt_erase_shift = chip->phys_erase_shift =
3922                 ffs(mtd->erasesize) - 1;
3923         if (chip->chipsize & 0xffffffff)
3924                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3925         else {
3926                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3927                 chip->chip_shift += 32 - 1;
3928         }
3929
3930         chip->badblockbits = 8;
3931         chip->erase_cmd = single_erase_cmd;
3932
3933         /* Do not replace user supplied command function! */
3934         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3935                 chip->cmdfunc = nand_command_lp;
3936
3937         pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3938                 *maf_id, *dev_id);
3939
3940 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3941         if (chip->onfi_version)
3942                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3943                                 chip->onfi_params.model);
3944         else if (chip->jedec_version)
3945                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3946                                 chip->jedec_params.model);
3947         else
3948                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3949                                 type->name);
3950 #else
3951         if (chip->jedec_version)
3952                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3953                                 chip->jedec_params.model);
3954         else
3955                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3956                                 type->name);
3957
3958         pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3959                 type->name);
3960 #endif
3961
3962         pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3963                 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3964                 mtd->writesize, mtd->oobsize);
3965         return type;
3966 }
3967
3968 /**
3969  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3970  * @mtd: MTD device structure
3971  * @maxchips: number of chips to scan for
3972  * @table: alternative NAND ID table
3973  *
3974  * This is the first phase of the normal nand_scan() function. It reads the
3975  * flash ID and sets up MTD fields accordingly.
3976  *
3977  * The mtd->owner field must be set to the module of the caller.
3978  */
3979 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3980                     struct nand_flash_dev *table)
3981 {
3982         int i, nand_maf_id, nand_dev_id;
3983         struct nand_chip *chip = mtd->priv;
3984         struct nand_flash_dev *type;
3985
3986         /* Set the default functions */
3987         nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3988
3989         /* Read the flash type */
3990         type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3991                                    &nand_dev_id, table);
3992
3993         if (IS_ERR(type)) {
3994                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3995                         pr_warn("No NAND device found\n");
3996                 chip->select_chip(mtd, -1);
3997                 return PTR_ERR(type);
3998         }
3999
4000         chip->select_chip(mtd, -1);
4001
4002         /* Check for a chip array */
4003         for (i = 1; i < maxchips; i++) {
4004                 chip->select_chip(mtd, i);
4005                 /* See comment in nand_get_flash_type for reset */
4006                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4007                 /* Send the command for reading device ID */
4008                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4009                 /* Read manufacturer and device IDs */
4010                 if (nand_maf_id != chip->read_byte(mtd) ||
4011                     nand_dev_id != chip->read_byte(mtd)) {
4012                         chip->select_chip(mtd, -1);
4013                         break;
4014                 }
4015                 chip->select_chip(mtd, -1);
4016         }
4017
4018 #ifdef DEBUG
4019         if (i > 1)
4020                 pr_info("%d chips detected\n", i);
4021 #endif
4022
4023         /* Store the number of chips and calc total size for mtd */
4024         chip->numchips = i;
4025         mtd->size = i * chip->chipsize;
4026
4027         return 0;
4028 }
4029 EXPORT_SYMBOL(nand_scan_ident);
4030
4031
4032 /**
4033  * nand_scan_tail - [NAND Interface] Scan for the NAND device
4034  * @mtd: MTD device structure
4035  *
4036  * This is the second phase of the normal nand_scan() function. It fills out
4037  * all the uninitialized function pointers with the defaults and scans for a
4038  * bad block table if appropriate.
4039  */
4040 int nand_scan_tail(struct mtd_info *mtd)
4041 {
4042         int i;
4043         struct nand_chip *chip = mtd->priv;
4044         struct nand_ecc_ctrl *ecc = &chip->ecc;
4045         struct nand_buffers *nbuf;
4046
4047         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4048         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4049                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
4050
4051         if (!(chip->options & NAND_OWN_BUFFERS)) {
4052 #ifndef __UBOOT__
4053                 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4054                                 + mtd->oobsize * 3, GFP_KERNEL);
4055                 if (!nbuf)
4056                         return -ENOMEM;
4057                 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4058                 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4059                 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4060 #else
4061                 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4062 #endif
4063
4064                 chip->buffers = nbuf;
4065         } else {
4066                 if (!chip->buffers)
4067                         return -ENOMEM;
4068         }
4069
4070         /* Set the internal oob buffer location, just after the page data */
4071         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4072
4073         /*
4074          * If no default placement scheme is given, select an appropriate one.
4075          */
4076         if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4077                 switch (mtd->oobsize) {
4078                 case 8:
4079                         ecc->layout = &nand_oob_8;
4080                         break;
4081                 case 16:
4082                         ecc->layout = &nand_oob_16;
4083                         break;
4084                 case 64:
4085                         ecc->layout = &nand_oob_64;
4086                         break;
4087                 case 128:
4088                         ecc->layout = &nand_oob_128;
4089                         break;
4090                 default:
4091                         pr_warn("No oob scheme defined for oobsize %d\n",
4092                                    mtd->oobsize);
4093                         BUG();
4094                 }
4095         }
4096
4097         if (!chip->write_page)
4098                 chip->write_page = nand_write_page;
4099
4100         /*
4101          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4102          * selected and we have 256 byte pagesize fallback to software ECC
4103          */
4104
4105         switch (ecc->mode) {
4106         case NAND_ECC_HW_OOB_FIRST:
4107                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4108                 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4109                         pr_warn("No ECC functions supplied; "
4110                                    "hardware ECC not possible\n");
4111                         BUG();
4112                 }
4113                 if (!ecc->read_page)
4114                         ecc->read_page = nand_read_page_hwecc_oob_first;
4115
4116         case NAND_ECC_HW:
4117                 /* Use standard hwecc read page function? */
4118                 if (!ecc->read_page)
4119                         ecc->read_page = nand_read_page_hwecc;
4120                 if (!ecc->write_page)
4121                         ecc->write_page = nand_write_page_hwecc;
4122                 if (!ecc->read_page_raw)
4123                         ecc->read_page_raw = nand_read_page_raw;
4124                 if (!ecc->write_page_raw)
4125                         ecc->write_page_raw = nand_write_page_raw;
4126                 if (!ecc->read_oob)
4127                         ecc->read_oob = nand_read_oob_std;
4128                 if (!ecc->write_oob)
4129                         ecc->write_oob = nand_write_oob_std;
4130                 if (!ecc->read_subpage)
4131                         ecc->read_subpage = nand_read_subpage;
4132                 if (!ecc->write_subpage)
4133                         ecc->write_subpage = nand_write_subpage_hwecc;
4134
4135         case NAND_ECC_HW_SYNDROME:
4136                 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4137                     (!ecc->read_page ||
4138                      ecc->read_page == nand_read_page_hwecc ||
4139                      !ecc->write_page ||
4140                      ecc->write_page == nand_write_page_hwecc)) {
4141                         pr_warn("No ECC functions supplied; "
4142                                    "hardware ECC not possible\n");
4143                         BUG();
4144                 }
4145                 /* Use standard syndrome read/write page function? */
4146                 if (!ecc->read_page)
4147                         ecc->read_page = nand_read_page_syndrome;
4148                 if (!ecc->write_page)
4149                         ecc->write_page = nand_write_page_syndrome;
4150                 if (!ecc->read_page_raw)
4151                         ecc->read_page_raw = nand_read_page_raw_syndrome;
4152                 if (!ecc->write_page_raw)
4153                         ecc->write_page_raw = nand_write_page_raw_syndrome;
4154                 if (!ecc->read_oob)
4155                         ecc->read_oob = nand_read_oob_syndrome;
4156                 if (!ecc->write_oob)
4157                         ecc->write_oob = nand_write_oob_syndrome;
4158
4159                 if (mtd->writesize >= ecc->size) {
4160                         if (!ecc->strength) {
4161                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4162                                 BUG();
4163                         }
4164                         break;
4165                 }
4166                 pr_warn("%d byte HW ECC not possible on "
4167                            "%d byte page size, fallback to SW ECC\n",
4168                            ecc->size, mtd->writesize);
4169                 ecc->mode = NAND_ECC_SOFT;
4170
4171         case NAND_ECC_SOFT:
4172                 ecc->calculate = nand_calculate_ecc;
4173                 ecc->correct = nand_correct_data;
4174                 ecc->read_page = nand_read_page_swecc;
4175                 ecc->read_subpage = nand_read_subpage;
4176                 ecc->write_page = nand_write_page_swecc;
4177                 ecc->read_page_raw = nand_read_page_raw;
4178                 ecc->write_page_raw = nand_write_page_raw;
4179                 ecc->read_oob = nand_read_oob_std;
4180                 ecc->write_oob = nand_write_oob_std;
4181                 if (!ecc->size)
4182                         ecc->size = 256;
4183                 ecc->bytes = 3;
4184                 ecc->strength = 1;
4185                 break;
4186
4187         case NAND_ECC_SOFT_BCH:
4188                 if (!mtd_nand_has_bch()) {
4189                         pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4190                         BUG();
4191                 }
4192                 ecc->calculate = nand_bch_calculate_ecc;
4193                 ecc->correct = nand_bch_correct_data;
4194                 ecc->read_page = nand_read_page_swecc;
4195                 ecc->read_subpage = nand_read_subpage;
4196                 ecc->write_page = nand_write_page_swecc;
4197                 ecc->read_page_raw = nand_read_page_raw;
4198                 ecc->write_page_raw = nand_write_page_raw;
4199                 ecc->read_oob = nand_read_oob_std;
4200                 ecc->write_oob = nand_write_oob_std;
4201                 /*
4202                  * Board driver should supply ecc.size and ecc.bytes values to
4203                  * select how many bits are correctable; see nand_bch_init()
4204                  * for details. Otherwise, default to 4 bits for large page
4205                  * devices.
4206                  */
4207                 if (!ecc->size && (mtd->oobsize >= 64)) {
4208                         ecc->size = 512;
4209                         ecc->bytes = 7;
4210                 }
4211                 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4212                                                &ecc->layout);
4213                 if (!ecc->priv) {
4214                         pr_warn("BCH ECC initialization failed!\n");
4215                         BUG();
4216                 }
4217                 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4218                 break;
4219
4220         case NAND_ECC_NONE:
4221                 pr_warn("NAND_ECC_NONE selected by board driver. "
4222                            "This is not recommended!\n");
4223                 ecc->read_page = nand_read_page_raw;
4224                 ecc->write_page = nand_write_page_raw;
4225                 ecc->read_oob = nand_read_oob_std;
4226                 ecc->read_page_raw = nand_read_page_raw;
4227                 ecc->write_page_raw = nand_write_page_raw;
4228                 ecc->write_oob = nand_write_oob_std;
4229                 ecc->size = mtd->writesize;
4230                 ecc->bytes = 0;
4231                 ecc->strength = 0;
4232                 break;
4233
4234         default:
4235                 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4236                 BUG();
4237         }
4238
4239         /* For many systems, the standard OOB write also works for raw */
4240         if (!ecc->read_oob_raw)
4241                 ecc->read_oob_raw = ecc->read_oob;
4242         if (!ecc->write_oob_raw)
4243                 ecc->write_oob_raw = ecc->write_oob;
4244
4245         /*
4246          * The number of bytes available for a client to place data into
4247          * the out of band area.
4248          */
4249         ecc->layout->oobavail = 0;
4250         for (i = 0; ecc->layout->oobfree[i].length
4251                         && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4252                 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4253         mtd->oobavail = ecc->layout->oobavail;
4254
4255         /*
4256          * Set the number of read / write steps for one page depending on ECC
4257          * mode.
4258          */
4259         ecc->steps = mtd->writesize / ecc->size;
4260         if (ecc->steps * ecc->size != mtd->writesize) {
4261                 pr_warn("Invalid ECC parameters\n");
4262                 BUG();
4263         }
4264         ecc->total = ecc->steps * ecc->bytes;
4265
4266         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4267         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4268                 switch (ecc->steps) {
4269                 case 2:
4270                         mtd->subpage_sft = 1;
4271                         break;
4272                 case 4:
4273                 case 8:
4274                 case 16:
4275                         mtd->subpage_sft = 2;
4276                         break;
4277                 }
4278         }
4279         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4280
4281         /* Initialize state */
4282         chip->state = FL_READY;
4283
4284         /* Invalidate the pagebuffer reference */
4285         chip->pagebuf = -1;
4286
4287         /* Large page NAND with SOFT_ECC should support subpage reads */
4288         if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4289                 chip->options |= NAND_SUBPAGE_READ;
4290
4291         /* Fill in remaining MTD driver data */
4292         mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4293         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4294                                                 MTD_CAP_NANDFLASH;
4295         mtd->_erase = nand_erase;
4296 #ifndef __UBOOT__
4297         mtd->_point = NULL;
4298         mtd->_unpoint = NULL;
4299 #endif
4300         mtd->_read = nand_read;
4301         mtd->_write = nand_write;
4302         mtd->_panic_write = panic_nand_write;
4303         mtd->_read_oob = nand_read_oob;
4304         mtd->_write_oob = nand_write_oob;
4305         mtd->_sync = nand_sync;
4306         mtd->_lock = NULL;
4307         mtd->_unlock = NULL;
4308 #ifndef __UBOOT__
4309         mtd->_suspend = nand_suspend;
4310         mtd->_resume = nand_resume;
4311 #endif
4312         mtd->_block_isbad = nand_block_isbad;
4313         mtd->_block_markbad = nand_block_markbad;
4314         mtd->writebufsize = mtd->writesize;
4315
4316         /* propagate ecc info to mtd_info */
4317         mtd->ecclayout = ecc->layout;
4318         mtd->ecc_strength = ecc->strength;
4319         mtd->ecc_step_size = ecc->size;
4320         /*
4321          * Initialize bitflip_threshold to its default prior scan_bbt() call.
4322          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4323          * properly set.
4324          */
4325         if (!mtd->bitflip_threshold)
4326                 mtd->bitflip_threshold = mtd->ecc_strength;
4327
4328         /* Check, if we should skip the bad block table scan */
4329         if (chip->options & NAND_SKIP_BBTSCAN)
4330                 chip->options |= NAND_BBT_SCANNED;
4331
4332         return 0;
4333 }
4334 EXPORT_SYMBOL(nand_scan_tail);
4335
4336 /*
4337  * is_module_text_address() isn't exported, and it's mostly a pointless
4338  * test if this is a module _anyway_ -- they'd have to try _really_ hard
4339  * to call us from in-kernel code if the core NAND support is modular.
4340  */
4341 #ifdef MODULE
4342 #define caller_is_module() (1)
4343 #else
4344 #define caller_is_module() \
4345         is_module_text_address((unsigned long)__builtin_return_address(0))
4346 #endif
4347
4348 /**
4349  * nand_scan - [NAND Interface] Scan for the NAND device
4350  * @mtd: MTD device structure
4351  * @maxchips: number of chips to scan for
4352  *
4353  * This fills out all the uninitialized function pointers with the defaults.
4354  * The flash ID is read and the mtd/chip structures are filled with the
4355  * appropriate values. The mtd->owner field must be set to the module of the
4356  * caller.
4357  */
4358 int nand_scan(struct mtd_info *mtd, int maxchips)
4359 {
4360         int ret;
4361
4362         /* Many callers got this wrong, so check for it for a while... */
4363         if (!mtd->owner && caller_is_module()) {
4364                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4365                 BUG();
4366         }
4367
4368         ret = nand_scan_ident(mtd, maxchips, NULL);
4369         if (!ret)
4370                 ret = nand_scan_tail(mtd);
4371         return ret;
4372 }
4373 EXPORT_SYMBOL(nand_scan);
4374
4375 #ifndef __UBOOT__
4376 /**
4377  * nand_release - [NAND Interface] Free resources held by the NAND device
4378  * @mtd: MTD device structure
4379  */
4380 void nand_release(struct mtd_info *mtd)
4381 {
4382         struct nand_chip *chip = mtd->priv;
4383
4384         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4385                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4386
4387         mtd_device_unregister(mtd);
4388
4389         /* Free bad block table memory */
4390         kfree(chip->bbt);
4391         if (!(chip->options & NAND_OWN_BUFFERS))
4392                 kfree(chip->buffers);
4393
4394         /* Free bad block descriptor memory */
4395         if (chip->badblock_pattern && chip->badblock_pattern->options
4396                         & NAND_BBT_DYNAMICSTRUCT)
4397                 kfree(chip->badblock_pattern);
4398 }
4399 EXPORT_SYMBOL_GPL(nand_release);
4400
4401 static int __init nand_base_init(void)
4402 {
4403         led_trigger_register_simple("nand-disk", &nand_led_trigger);
4404         return 0;
4405 }
4406
4407 static void __exit nand_base_exit(void)
4408 {
4409         led_trigger_unregister_simple(nand_led_trigger);
4410 }
4411 #endif
4412
4413 module_init(nand_base_init);
4414 module_exit(nand_base_exit);
4415
4416 MODULE_LICENSE("GPL");
4417 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4418 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4419 MODULE_DESCRIPTION("Generic NAND flash driver code");