2 * CPSW Ethernet Switch Driver
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
23 #include <asm/errno.h>
26 #include <asm/arch/cpu.h>
28 #define BITMASK(bits) (BIT(bits) - 1)
29 #define PHY_REG_MASK 0x1f
30 #define PHY_ID_MASK 0x1f
31 #define NUM_DESCS (PKTBUFSRX * 2)
33 #define PKT_MAX (1500 + 14 + 4 + 4)
35 #define GIGABITEN BIT(7)
36 #define FULLDUPLEXEN BIT(0)
40 #define CPDMA_TXCONTROL 0x004
41 #define CPDMA_RXCONTROL 0x014
42 #define CPDMA_SOFTRESET 0x01c
43 #define CPDMA_RXFREE 0x0e0
44 #define CPDMA_TXHDP_VER1 0x100
45 #define CPDMA_TXHDP_VER2 0x200
46 #define CPDMA_RXHDP_VER1 0x120
47 #define CPDMA_RXHDP_VER2 0x220
48 #define CPDMA_TXCP_VER1 0x140
49 #define CPDMA_TXCP_VER2 0x240
50 #define CPDMA_RXCP_VER1 0x160
51 #define CPDMA_RXCP_VER2 0x260
53 #define CPDMA_RAM_ADDR 0x4a102000
55 /* Descriptor mode bits */
56 #define CPDMA_DESC_SOP BIT(31)
57 #define CPDMA_DESC_EOP BIT(30)
58 #define CPDMA_DESC_OWNER BIT(29)
59 #define CPDMA_DESC_EOQ BIT(28)
62 * This timeout definition is a worst-case ultra defensive measure against
63 * unexpected controller lock ups. Ideally, we should never ever hit this
64 * scenario in practice.
66 #define MDIO_TIMEOUT 100 /* msecs */
67 #define CPDMA_TIMEOUT 100 /* msecs */
69 struct cpsw_mdio_regs {
72 #define CONTROL_IDLE BIT(31)
73 #define CONTROL_ENABLE BIT(30)
89 #define USERACCESS_GO BIT(31)
90 #define USERACCESS_WRITE BIT(30)
91 #define USERACCESS_ACK BIT(29)
92 #define USERACCESS_READ 0
93 #define USERACCESS_DATA 0xffff
105 struct cpsw_slave_regs {
116 struct cpsw_host_regs {
122 u32 cpdma_tx_pri_map;
123 u32 cpdma_rx_chan_map;
126 struct cpsw_sliver_regs {
139 #define ALE_ENTRY_BITS 68
140 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
143 #define ALE_CONTROL 0x08
144 #define ALE_UNKNOWNVLAN 0x18
145 #define ALE_TABLE_CONTROL 0x20
146 #define ALE_TABLE 0x34
147 #define ALE_PORTCTL 0x40
149 #define ALE_TABLE_WRITE BIT(31)
151 #define ALE_TYPE_FREE 0
152 #define ALE_TYPE_ADDR 1
153 #define ALE_TYPE_VLAN 2
154 #define ALE_TYPE_VLAN_ADDR 3
156 #define ALE_UCAST_PERSISTANT 0
157 #define ALE_UCAST_UNTOUCHED 1
158 #define ALE_UCAST_OUI 2
159 #define ALE_UCAST_TOUCHED 3
161 #define ALE_MCAST_FWD 0
162 #define ALE_MCAST_BLOCK_LEARN_FWD 1
163 #define ALE_MCAST_FWD_LEARN 2
164 #define ALE_MCAST_FWD_2 3
166 enum cpsw_ale_port_state {
167 ALE_PORT_STATE_DISABLE = 0x00,
168 ALE_PORT_STATE_BLOCK = 0x01,
169 ALE_PORT_STATE_LEARN = 0x02,
170 ALE_PORT_STATE_FORWARD = 0x03,
173 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
175 #define ALE_BLOCKED 2
178 struct cpsw_slave_regs *regs;
179 struct cpsw_sliver_regs *sliver;
182 struct cpsw_slave_data *data;
186 /* hardware fields */
191 } __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
195 struct cpsw_desc *next;
196 struct cpdma_desc *dma_desc;
200 struct cpsw_desc *head, *tail;
201 void *hdp, *cp, *rxfree;
204 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->dma_desc->fld)
205 #define desc_read(desc, fld) __raw_readl(&(desc)->dma_desc->fld)
206 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->dma_desc->fld))
208 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
209 #define chan_read(chan, fld) __raw_readl((chan)->fld)
210 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
212 #define for_each_slave(slave, priv) \
213 for (slave = (priv)->slaves; slave != (priv)->slaves + \
214 (priv)->data->slaves; slave++)
217 struct eth_device *dev;
218 struct cpsw_platform_data *data;
221 struct cpsw_regs *regs;
223 struct cpsw_host_regs *host_port_regs;
226 struct cpsw_desc descs[NUM_DESCS];
227 struct cpsw_desc *desc_free;
228 struct cpdma_chan rx_chan, tx_chan;
230 struct cpsw_slave *slaves;
231 struct phy_device *phydev;
235 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
241 idx = 2 - idx; /* flip */
242 return (ale_entry[idx] >> start) & BITMASK(bits);
245 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
250 value &= BITMASK(bits);
253 idx = 2 - idx; /* flip */
254 ale_entry[idx] &= ~(BITMASK(bits) << start);
255 ale_entry[idx] |= (value << start);
258 #define DEFINE_ALE_FIELD(name, start, bits) \
259 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
261 return cpsw_ale_get_field(ale_entry, start, bits); \
263 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
265 cpsw_ale_set_field(ale_entry, start, bits, value); \
268 DEFINE_ALE_FIELD(entry_type, 60, 2)
269 DEFINE_ALE_FIELD(mcast_state, 62, 2)
270 DEFINE_ALE_FIELD(port_mask, 66, 3)
271 DEFINE_ALE_FIELD(ucast_type, 62, 2)
272 DEFINE_ALE_FIELD(port_num, 66, 2)
273 DEFINE_ALE_FIELD(blocked, 65, 1)
274 DEFINE_ALE_FIELD(secure, 64, 1)
275 DEFINE_ALE_FIELD(mcast, 40, 1)
277 /* The MAC address field in the ALE entry cannot be macroized as above */
278 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
282 for (i = 0; i < 6; i++)
283 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
286 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
290 for (i = 0; i < 6; i++)
291 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
294 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
298 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
300 for (i = 0; i < ALE_ENTRY_WORDS; i++)
301 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
306 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
310 for (i = 0; i < ALE_ENTRY_WORDS; i++)
311 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
313 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
318 static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
320 u32 ale_entry[ALE_ENTRY_WORDS];
323 for (idx = 0; idx < priv->data->ale_entries; idx++) {
326 cpsw_ale_read(priv, idx, ale_entry);
327 type = cpsw_ale_get_entry_type(ale_entry);
328 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
330 cpsw_ale_get_addr(ale_entry, entry_addr);
331 if (memcmp(entry_addr, addr, 6) == 0)
337 static int cpsw_ale_match_free(struct cpsw_priv *priv)
339 u32 ale_entry[ALE_ENTRY_WORDS];
342 for (idx = 0; idx < priv->data->ale_entries; idx++) {
343 cpsw_ale_read(priv, idx, ale_entry);
344 type = cpsw_ale_get_entry_type(ale_entry);
345 if (type == ALE_TYPE_FREE)
351 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
353 u32 ale_entry[ALE_ENTRY_WORDS];
356 for (idx = 0; idx < priv->data->ale_entries; idx++) {
357 cpsw_ale_read(priv, idx, ale_entry);
358 type = cpsw_ale_get_entry_type(ale_entry);
359 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
361 if (cpsw_ale_get_mcast(ale_entry))
363 type = cpsw_ale_get_ucast_type(ale_entry);
364 if (type != ALE_UCAST_PERSISTANT &&
365 type != ALE_UCAST_OUI)
371 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
374 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
377 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
378 cpsw_ale_set_addr(ale_entry, addr);
379 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
380 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
381 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
382 cpsw_ale_set_port_num(ale_entry, port);
384 idx = cpsw_ale_match_addr(priv, addr);
386 idx = cpsw_ale_match_free(priv);
388 idx = cpsw_ale_find_ageable(priv);
392 cpsw_ale_write(priv, idx, ale_entry);
396 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
398 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
401 idx = cpsw_ale_match_addr(priv, addr);
403 cpsw_ale_read(priv, idx, ale_entry);
405 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
406 cpsw_ale_set_addr(ale_entry, addr);
407 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
409 mask = cpsw_ale_get_port_mask(ale_entry);
411 cpsw_ale_set_port_mask(ale_entry, port_mask);
414 idx = cpsw_ale_match_free(priv);
416 idx = cpsw_ale_find_ageable(priv);
420 cpsw_ale_write(priv, idx, ale_entry);
424 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
426 u32 tmp, mask = BIT(bit);
428 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
430 tmp |= val ? mask : 0;
431 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
434 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
435 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
436 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
438 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
441 int offset = ALE_PORTCTL + 4 * port;
444 tmp = __raw_readl(priv->ale_regs + offset);
447 __raw_writel(tmp, priv->ale_regs + offset);
450 static struct cpsw_mdio_regs *mdio_regs;
452 /* wait until hardware is ready for another user access */
453 static inline u32 wait_for_user_access(void)
455 int timeout = MDIO_TIMEOUT;
458 while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
460 if (--timeout <= 0) {
461 printf("TIMEOUT waiting for USERACCESS_GO\n");
469 /* wait until hardware state machine is idle */
470 static inline void wait_for_idle(void)
472 int timeout = MDIO_TIMEOUT;
474 while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
475 if (--timeout <= 0) {
476 printf("TIMEOUT waiting for state machine idle\n");
483 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
484 int dev_addr, int phy_reg)
489 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
492 wait_for_user_access();
493 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
495 __raw_writel(reg, &mdio_regs->user[0].access);
496 reg = wait_for_user_access();
498 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
502 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
503 int phy_reg, u16 data)
507 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
510 wait_for_user_access();
511 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
512 (phy_id << 16) | (data & USERACCESS_DATA));
513 __raw_writel(reg, &mdio_regs->user[0].access);
514 wait_for_user_access();
519 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
521 struct mii_dev *bus = mdio_alloc();
523 mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
525 /* set enable and clock divider */
526 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
529 * wait for scan logic to settle:
530 * the scan time consists of (a) a large fixed component, and (b) a
531 * small component that varies with the mii bus frequency. These
532 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
533 * silicon. Since the effect of (b) was found to be largely
534 * negligible, we keep things simple here.
538 bus->read = cpsw_mdio_read;
539 bus->write = cpsw_mdio_write;
540 sprintf(bus->name, name);
545 /* Set a self-clearing bit in a register, and wait for it to clear */
546 static inline void setbit_and_wait_for_clear32(void *addr)
550 __raw_writel(CLEAR_BIT, addr);
551 while (__raw_readl(addr) & CLEAR_BIT)
553 debug("%s: reset finished after %u loops\n", __func__, loops);
556 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
557 ((mac)[2] << 16) | ((mac)[3] << 24))
558 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
560 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
561 struct cpsw_priv *priv)
563 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
564 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
569 static void cpsw_slave_update_link(struct cpsw_slave *slave,
570 struct cpsw_priv *priv, int *link)
572 struct phy_device *phy = priv->phydev;
574 int retries = NUM_TRIES;
580 if (*link) { /* link up */
581 mac_control = priv->data->mac_control;
582 if (phy->speed == 1000)
583 mac_control |= GIGABITEN;
584 if (phy->duplex == DUPLEX_FULL)
585 mac_control |= FULLDUPLEXEN;
586 if (phy->speed == 100)
587 mac_control |= MIIEN;
591 } while (!*link && retries-- > 0);
592 debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
593 slave->mac_control, mac_control, NUM_TRIES - retries);
595 if (mac_control == slave->mac_control)
599 printf("link up on port %d, speed %d, %s duplex\n",
600 slave->slave_num, phy->speed,
601 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
603 printf("link down on port %d\n", slave->slave_num);
606 __raw_writel(mac_control, &slave->sliver->mac_control);
607 slave->mac_control = mac_control;
610 static void cpsw_slave_update_link(struct cpsw_slave *slave,
611 struct cpsw_priv *priv, int *link)
613 struct phy_device *phy = priv->phydev;
619 if (*link) { /* link up */
620 mac_control = priv->data.mac_control;
621 if (phy->speed == 1000)
622 mac_control |= GIGABITEN;
623 if (phy->duplex == DUPLEX_FULL)
624 mac_control |= FULLDUPLEXEN;
625 if (phy->speed == 100)
626 mac_control |= MIIEN;
628 debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
629 slave->mac_control, mac_control, NUM_TRIES - retries);
631 if (mac_control == slave->mac_control)
635 printf("link up on port %d, speed %d, %s duplex\n",
636 slave->slave_num, phy->speed,
637 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
639 printf("link down on port %d\n", slave->slave_num);
642 __raw_writel(mac_control, &slave->sliver->mac_control);
643 slave->mac_control = mac_control;
647 static int cpsw_update_link(struct cpsw_priv *priv)
650 struct cpsw_slave *slave;
652 for_each_slave(slave, priv)
653 cpsw_slave_update_link(slave, priv, &link);
658 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
660 if (priv->host_port == 0)
661 return slave_num + 1;
666 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
670 debug("%s\n", __func__);
671 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
673 /* setup priority mapping */
674 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
675 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
677 /* setup max packet size, and mac address */
678 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
679 cpsw_set_slave_mac(slave, priv);
681 slave->mac_control = 0; /* no link yet */
683 /* enable forwarding */
684 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
685 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
687 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
690 static void cpdma_desc_get(struct cpsw_desc *desc)
692 invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
695 static void cpdma_desc_put(struct cpsw_desc *desc)
697 flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
700 static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
702 struct cpsw_desc *desc = priv->desc_free;
705 cpdma_desc_get(desc);
706 priv->desc_free = desc->next;
711 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
714 desc_write(desc, hw_next, priv->desc_free->dma_desc);
715 cpdma_desc_put(desc);
716 desc->next = priv->desc_free;
717 priv->desc_free = desc;
721 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
722 void *buffer, int len)
724 struct cpsw_desc *desc, *prev;
728 printf("ERROR: %s() NULL buffer\n", __func__);
732 flush_dcache_range((u32)buffer, (u32)buffer + len);
734 desc = cpdma_desc_alloc(priv);
738 debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
739 chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
743 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
746 desc_write(desc, hw_next, 0);
747 desc_write(desc, hw_buffer, buffer);
748 desc_write(desc, hw_len, len);
749 desc_write(desc, hw_mode, mode | len);
751 desc->sw_buffer = buffer;
753 cpdma_desc_put(desc);
755 /* simple case - first packet enqueued */
758 chan_write(chan, hdp, desc->dma_desc);
762 /* not the first packet - enqueue at the tail */
766 cpdma_desc_get(prev);
767 desc_write(prev, hw_next, desc->dma_desc);
768 cpdma_desc_put(prev);
772 /* next check if EOQ has been triggered already */
773 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
774 chan_write(chan, hdp, desc->dma_desc);
778 chan_write(chan, rxfree, 1);
779 debug("%s@%d\n", __func__, __LINE__);
783 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
784 void **buffer, int *len)
786 struct cpsw_desc *desc = chan->head;
792 cpdma_desc_get(desc);
794 status = desc_read(desc, hw_mode);
795 if (status & CPDMA_DESC_OWNER)
799 *len = status & 0x7ff;
802 *buffer = desc->sw_buffer;
803 debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
805 chan->head = desc->next;
806 chan_write(chan, cp, desc->dma_desc);
808 cpdma_desc_free(priv, desc);
812 static int cpsw_init(struct eth_device *dev, bd_t *bis)
814 struct cpsw_priv *priv = dev->priv;
815 struct cpsw_slave *slave;
818 debug("%s\n", __func__);
819 /* soft reset the controller and initialize priv */
820 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
822 /* initialize and reset the address lookup engine */
823 cpsw_ale_enable(priv, 1);
824 cpsw_ale_clear(priv, 1);
825 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
827 /* setup host port priority mapping */
828 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
829 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
831 /* disable priority elevation and enable statistics on all ports */
832 __raw_writel(0, &priv->regs->ptype);
834 /* enable statistics collection only on the host port */
835 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
837 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
839 cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
841 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
843 for_each_slave(slave, priv)
844 cpsw_slave_init(slave, priv);
846 cpsw_update_link(priv);
848 /* init descriptor pool */
849 for (i = 0; i < NUM_DESCS; i++) {
850 struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
851 &priv->descs[i + 1] : NULL;
853 priv->descs[i].next = next_desc;
854 desc_write(&priv->descs[i], hw_next,
855 next_desc ? next_desc->dma_desc : 0);
856 cpdma_desc_put(&priv->descs[i]);
858 priv->desc_free = &priv->descs[0];
860 /* initialize channels */
861 if (priv->data->version == CPSW_CTRL_VERSION_2) {
862 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
863 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
864 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
865 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
867 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
868 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
869 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
871 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
872 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
873 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
874 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
876 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
877 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
878 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
881 /* clear dma state */
882 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
884 if (priv->data->version == CPSW_CTRL_VERSION_2) {
885 for (i = 0; i < priv->data->channels; i++) {
886 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
887 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
888 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
889 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
890 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
893 for (i = 0; i < priv->data->channels; i++) {
894 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
895 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
896 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
897 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
898 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
903 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
904 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
906 /* submit rx descs */
907 for (i = 0; i < PKTBUFSRX; i++) {
908 ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
911 printf("error %d submitting rx desc\n", ret);
919 static void cpsw_halt(struct eth_device *dev)
921 struct cpsw_priv *priv = dev->priv;
923 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
924 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
926 /* soft reset the controller and initialize priv */
927 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
929 /* clear dma state */
930 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
932 debug("%s\n", __func__);
933 priv->data->control(0);
936 static int cpsw_send(struct eth_device *dev, void *packet, int length)
938 struct cpsw_priv *priv = dev->priv;
942 debug("%s@%d: sending packet %p..%p\n", __func__, __LINE__,
943 packet, packet + length - 1);
945 if (!priv->data->mac_control && !cpsw_update_link(priv)) {
946 printf("%s: Cannot send packet; link is down\n", __func__);
950 /* first reap completed packets */
951 while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
954 return cpdma_submit(priv, &priv->tx_chan, packet, length);
957 static int cpsw_recv(struct eth_device *dev)
959 struct cpsw_priv *priv = dev->priv;
963 while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
965 NetReceive(buffer, len);
966 cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
968 printf("NULL buffer returned from cpdma_process\n");
976 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
977 struct cpsw_priv *priv)
979 void *regs = priv->regs;
980 struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
982 debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
984 slave->slave_num = slave_num;
986 slave->regs = regs + data->slave_reg_ofs;
987 slave->sliver = regs + data->sliver_reg_ofs;
990 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
992 struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
993 struct phy_device *phydev;
994 u32 supported = (SUPPORTED_10baseT_Half |
995 SUPPORTED_10baseT_Full |
996 SUPPORTED_100baseT_Half |
997 SUPPORTED_100baseT_Full |
998 SUPPORTED_1000baseT_Full);
1000 phydev = phy_connect(priv->bus,
1003 slave->data->phy_if);
1005 phydev->supported &= supported;
1006 phydev->advertising = phydev->supported;
1008 priv->phydev = phydev;
1014 int cpsw_register(struct cpsw_platform_data *data)
1016 struct cpsw_priv *priv;
1017 struct cpsw_slave *slave;
1018 void *regs = (void *)data->cpsw_base;
1019 struct eth_device *dev;
1023 debug("%s@%d\n", __func__, __LINE__);
1025 dev = calloc(sizeof(*dev), 1);
1029 priv = calloc(sizeof(*priv), 1);
1038 priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
1039 if (!priv->slaves) {
1045 for (i = 0; i < NUM_DESCS; i++) {
1046 priv->descs[i].dma_desc = memalign(CONFIG_SYS_CACHELINE_SIZE,
1047 sizeof(struct cpsw_desc) * NUM_DESCS);
1048 if (!priv->descs[i].dma_desc) {
1050 free(priv->descs[i].dma_desc);
1057 debug("DMA desc[%d] allocated @ %p desc_size %u\n",
1058 i, priv->descs[i].dma_desc,
1059 sizeof(*priv->descs[i].dma_desc));
1062 priv->host_port = data->host_port_num;
1064 priv->host_port_regs = regs + data->host_port_reg_ofs;
1065 priv->dma_regs = regs + data->cpdma_reg_ofs;
1066 priv->ale_regs = regs + data->ale_reg_ofs;
1068 for_each_slave(slave, priv) {
1069 cpsw_slave_setup(slave, idx, priv);
1073 strcpy(dev->name, "cpsw");
1075 dev->init = cpsw_init;
1076 dev->halt = cpsw_halt;
1077 dev->send = cpsw_send;
1078 dev->recv = cpsw_recv;
1083 cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
1084 priv->bus = miiphy_get_dev_by_name(dev->name);
1085 for_each_slave(slave, priv)
1086 cpsw_phy_init(dev, slave);