drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12  * SPDX-License-Identifier:     GPL-2.0+
  13
  14   Contact Information:
  15   Linux NICS <linux.nics@intel.com>
  16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18 *******************************************************************************/
  19 /*
  20  *  Copyright (C) Archway Digital Solutions.
  21  *
  22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23  *  2/9/2002
  24  *
  25  *  Copyright (C) Linux Networx.
  26  *  Massive upgrade to work with the new intel gigabit NICs.
  27  *  <ebiederman at lnxi dot com>
  28  *
  29  *  Copyright 2011 Freescale Semiconductor, Inc.
  30  */
  31
  32 #include "e1000.h"
  33
  34 #define TOUT_LOOP   100000
  35
  36 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  37 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  38
  39 #define E1000_DEFAULT_PCI_PBA   0x00000030
  40 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  41
  42 /* NIC specific static variables go here */
  43
  44 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  45 #define E1000_BUFFER_ALIGN      128
  46
  47 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  48 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  49 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  50
  51 static int tx_tail;
  52 static int rx_tail, rx_last;
  53
  54 static struct pci_device_id e1000_supported[] = {
  55         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  56         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  57         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  58         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  59         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  60         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  61         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  62         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  63         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  64         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  65         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  66         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  67         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  68         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  69         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  72         /* E1000 PCIe card */
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
  87         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX},
 103
 104         {}
 105 };
 106
 107 /* Function forward declarations */
 108 static int e1000_setup_link(struct eth_device *nic);
 109 static int e1000_setup_fiber_link(struct eth_device *nic);
 110 static int e1000_setup_copper_link(struct eth_device *nic);
 111 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 112 static void e1000_config_collision_dist(struct e1000_hw *hw);
 113 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 114 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 115 static int e1000_check_for_link(struct eth_device *nic);
 116 static int e1000_wait_autoneg(struct e1000_hw *hw);
 117 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 118                                        uint16_t * duplex);
 119 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 120                               uint16_t * phy_data);
 121 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 122                                uint16_t phy_data);
 123 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 124 static int e1000_phy_reset(struct e1000_hw *hw);
 125 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 126 static void e1000_set_media_type(struct e1000_hw *hw);
 127
 128 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 129 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
 130 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 131
 132 #ifndef CONFIG_E1000_NO_NVM
 133 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 134 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 135                 uint16_t words,
 136                 uint16_t *data);
 137 /******************************************************************************
 138  * Raises the EEPROM's clock input.
 139  *
 140  * hw - Struct containing variables accessed by shared code
 141  * eecd - EECD's current value
 142  *****************************************************************************/
 143 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 144 {
 145         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 146          * wait 50 microseconds.
 147          */
 148         *eecd = *eecd | E1000_EECD_SK;
 149         E1000_WRITE_REG(hw, EECD, *eecd);
 150         E1000_WRITE_FLUSH(hw);
 151         udelay(50);
 152 }
 153
 154 /******************************************************************************
 155  * Lowers the EEPROM's clock input.
 156  *
 157  * hw - Struct containing variables accessed by shared code
 158  * eecd - EECD's current value
 159  *****************************************************************************/
 160 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 161 {
 162         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 163          * wait 50 microseconds.
 164          */
 165         *eecd = *eecd & ~E1000_EECD_SK;
 166         E1000_WRITE_REG(hw, EECD, *eecd);
 167         E1000_WRITE_FLUSH(hw);
 168         udelay(50);
 169 }
 170
 171 /******************************************************************************
 172  * Shift data bits out to the EEPROM.
 173  *
 174  * hw - Struct containing variables accessed by shared code
 175  * data - data to send to the EEPROM
 176  * count - number of bits to shift out
 177  *****************************************************************************/
 178 static void
 179 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 180 {
 181         uint32_t eecd;
 182         uint32_t mask;
 183
 184         /* We need to shift "count" bits out to the EEPROM. So, value in the
 185          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 186          * In order to do this, "data" must be broken down into bits.
 187          */
 188         mask = 0x01 << (count - 1);
 189         eecd = E1000_READ_REG(hw, EECD);
 190         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 191         do {
 192                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 193                  * and then raising and then lowering the clock (the SK bit controls
 194                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 195                  * by setting "DI" to "0" and then raising and then lowering the clock.
 196                  */
 197                 eecd &= ~E1000_EECD_DI;
 198
 199                 if (data & mask)
 200                         eecd |= E1000_EECD_DI;
 201
 202                 E1000_WRITE_REG(hw, EECD, eecd);
 203                 E1000_WRITE_FLUSH(hw);
 204
 205                 udelay(50);
 206
 207                 e1000_raise_ee_clk(hw, &eecd);
 208                 e1000_lower_ee_clk(hw, &eecd);
 209
 210                 mask = mask >> 1;
 211
 212         } while (mask);
 213
 214         /* We leave the "DI" bit set to "0" when we leave this routine. */
 215         eecd &= ~E1000_EECD_DI;
 216         E1000_WRITE_REG(hw, EECD, eecd);
 217 }
 218
 219 /******************************************************************************
 220  * Shift data bits in from the EEPROM
 221  *
 222  * hw - Struct containing variables accessed by shared code
 223  *****************************************************************************/
 224 static uint16_t
 225 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 226 {
 227         uint32_t eecd;
 228         uint32_t i;
 229         uint16_t data;
 230
 231         /* In order to read a register from the EEPROM, we need to shift 'count'
 232          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 233          * input to the EEPROM (setting the SK bit), and then reading the
 234          * value of the "DO" bit.  During this "shifting in" process the
 235          * "DI" bit should always be clear.
 236          */
 237
 238         eecd = E1000_READ_REG(hw, EECD);
 239
 240         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 241         data = 0;
 242
 243         for (i = 0; i < count; i++) {
 244                 data = data << 1;
 245                 e1000_raise_ee_clk(hw, &eecd);
 246
 247                 eecd = E1000_READ_REG(hw, EECD);
 248
 249                 eecd &= ~(E1000_EECD_DI);
 250                 if (eecd & E1000_EECD_DO)
 251                         data |= 1;
 252
 253                 e1000_lower_ee_clk(hw, &eecd);
 254         }
 255
 256         return data;
 257 }
 258
 259 /******************************************************************************
 260  * Returns EEPROM to a "standby" state
 261  *
 262  * hw - Struct containing variables accessed by shared code
 263  *****************************************************************************/
 264 void e1000_standby_eeprom(struct e1000_hw *hw)
 265 {
 266         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 267         uint32_t eecd;
 268
 269         eecd = E1000_READ_REG(hw, EECD);
 270
 271         if (eeprom->type == e1000_eeprom_microwire) {
 272                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 273                 E1000_WRITE_REG(hw, EECD, eecd);
 274                 E1000_WRITE_FLUSH(hw);
 275                 udelay(eeprom->delay_usec);
 276
 277                 /* Clock high */
 278                 eecd |= E1000_EECD_SK;
 279                 E1000_WRITE_REG(hw, EECD, eecd);
 280                 E1000_WRITE_FLUSH(hw);
 281                 udelay(eeprom->delay_usec);
 282
 283                 /* Select EEPROM */
 284                 eecd |= E1000_EECD_CS;
 285                 E1000_WRITE_REG(hw, EECD, eecd);
 286                 E1000_WRITE_FLUSH(hw);
 287                 udelay(eeprom->delay_usec);
 288
 289                 /* Clock low */
 290                 eecd &= ~E1000_EECD_SK;
 291                 E1000_WRITE_REG(hw, EECD, eecd);
 292                 E1000_WRITE_FLUSH(hw);
 293                 udelay(eeprom->delay_usec);
 294         } else if (eeprom->type == e1000_eeprom_spi) {
 295                 /* Toggle CS to flush commands */
 296                 eecd |= E1000_EECD_CS;
 297                 E1000_WRITE_REG(hw, EECD, eecd);
 298                 E1000_WRITE_FLUSH(hw);
 299                 udelay(eeprom->delay_usec);
 300                 eecd &= ~E1000_EECD_CS;
 301                 E1000_WRITE_REG(hw, EECD, eecd);
 302                 E1000_WRITE_FLUSH(hw);
 303                 udelay(eeprom->delay_usec);
 304         }
 305 }
 306
 307 /***************************************************************************
 308 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 309 *
 310 * hw - Struct containing variables accessed by shared code
 311 ****************************************************************************/
 312 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 313 {
 314         uint32_t eecd = 0;
 315
 316         DEBUGFUNC();
 317
 318         if (hw->mac_type == e1000_ich8lan)
 319                 return false;
 320
 321         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 322                 eecd = E1000_READ_REG(hw, EECD);
 323
 324                 /* Isolate bits 15 & 16 */
 325                 eecd = ((eecd >> 15) & 0x03);
 326
 327                 /* If both bits are set, device is Flash type */
 328                 if (eecd == 0x03)
 329                         return false;
 330         }
 331         return true;
 332 }
 333
 334 /******************************************************************************
 335  * Prepares EEPROM for access
 336  *
 337  * hw - Struct containing variables accessed by shared code
 338  *
 339  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 340  * function should be called before issuing a command to the EEPROM.
 341  *****************************************************************************/
 342 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 343 {
 344         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 345         uint32_t eecd, i = 0;
 346
 347         DEBUGFUNC();
 348
 349         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 350                 return -E1000_ERR_SWFW_SYNC;
 351         eecd = E1000_READ_REG(hw, EECD);
 352
 353         if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
 354                 /* Request EEPROM Access */
 355                 if (hw->mac_type > e1000_82544) {
 356                         eecd |= E1000_EECD_REQ;
 357                         E1000_WRITE_REG(hw, EECD, eecd);
 358                         eecd = E1000_READ_REG(hw, EECD);
 359                         while ((!(eecd & E1000_EECD_GNT)) &&
 360                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 361                                 i++;
 362                                 udelay(5);
 363                                 eecd = E1000_READ_REG(hw, EECD);
 364                         }
 365                         if (!(eecd & E1000_EECD_GNT)) {
 366                                 eecd &= ~E1000_EECD_REQ;
 367                                 E1000_WRITE_REG(hw, EECD, eecd);
 368                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 369                                 return -E1000_ERR_EEPROM;
 370                         }
 371                 }
 372         }
 373
 374         /* Setup EEPROM for Read/Write */
 375
 376         if (eeprom->type == e1000_eeprom_microwire) {
 377                 /* Clear SK and DI */
 378                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 379                 E1000_WRITE_REG(hw, EECD, eecd);
 380
 381                 /* Set CS */
 382                 eecd |= E1000_EECD_CS;
 383                 E1000_WRITE_REG(hw, EECD, eecd);
 384         } else if (eeprom->type == e1000_eeprom_spi) {
 385                 /* Clear SK and CS */
 386                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 387                 E1000_WRITE_REG(hw, EECD, eecd);
 388                 udelay(1);
 389         }
 390
 391         return E1000_SUCCESS;
 392 }
 393
 394 /******************************************************************************
 395  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 396  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 397  * registers must be mapped, or this will crash.
 398  *
 399  * hw - Struct containing variables accessed by shared code
 400  *****************************************************************************/
 401 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 402 {
 403         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 404         uint32_t eecd;
 405         int32_t ret_val = E1000_SUCCESS;
 406         uint16_t eeprom_size;
 407
 408         if (hw->mac_type == e1000_igb)
 409                 eecd = E1000_READ_REG(hw, I210_EECD);
 410         else
 411                 eecd = E1000_READ_REG(hw, EECD);
 412
 413         DEBUGFUNC();
 414
 415         switch (hw->mac_type) {
 416         case e1000_82542_rev2_0:
 417         case e1000_82542_rev2_1:
 418         case e1000_82543:
 419         case e1000_82544:
 420                 eeprom->type = e1000_eeprom_microwire;
 421                 eeprom->word_size = 64;
 422                 eeprom->opcode_bits = 3;
 423                 eeprom->address_bits = 6;
 424                 eeprom->delay_usec = 50;
 425                 eeprom->use_eerd = false;
 426                 eeprom->use_eewr = false;
 427         break;
 428         case e1000_82540:
 429         case e1000_82545:
 430         case e1000_82545_rev_3:
 431         case e1000_82546:
 432         case e1000_82546_rev_3:
 433                 eeprom->type = e1000_eeprom_microwire;
 434                 eeprom->opcode_bits = 3;
 435                 eeprom->delay_usec = 50;
 436                 if (eecd & E1000_EECD_SIZE) {
 437                         eeprom->word_size = 256;
 438                         eeprom->address_bits = 8;
 439                 } else {
 440                         eeprom->word_size = 64;
 441                         eeprom->address_bits = 6;
 442                 }
 443                 eeprom->use_eerd = false;
 444                 eeprom->use_eewr = false;
 445                 break;
 446         case e1000_82541:
 447         case e1000_82541_rev_2:
 448         case e1000_82547:
 449         case e1000_82547_rev_2:
 450                 if (eecd & E1000_EECD_TYPE) {
 451                         eeprom->type = e1000_eeprom_spi;
 452                         eeprom->opcode_bits = 8;
 453                         eeprom->delay_usec = 1;
 454                         if (eecd & E1000_EECD_ADDR_BITS) {
 455                                 eeprom->page_size = 32;
 456                                 eeprom->address_bits = 16;
 457                         } else {
 458                                 eeprom->page_size = 8;
 459                                 eeprom->address_bits = 8;
 460                         }
 461                 } else {
 462                         eeprom->type = e1000_eeprom_microwire;
 463                         eeprom->opcode_bits = 3;
 464                         eeprom->delay_usec = 50;
 465                         if (eecd & E1000_EECD_ADDR_BITS) {
 466                                 eeprom->word_size = 256;
 467                                 eeprom->address_bits = 8;
 468                         } else {
 469                                 eeprom->word_size = 64;
 470                                 eeprom->address_bits = 6;
 471                         }
 472                 }
 473                 eeprom->use_eerd = false;
 474                 eeprom->use_eewr = false;
 475                 break;
 476         case e1000_82571:
 477         case e1000_82572:
 478                 eeprom->type = e1000_eeprom_spi;
 479                 eeprom->opcode_bits = 8;
 480                 eeprom->delay_usec = 1;
 481                 if (eecd & E1000_EECD_ADDR_BITS) {
 482                         eeprom->page_size = 32;
 483                         eeprom->address_bits = 16;
 484                 } else {
 485                         eeprom->page_size = 8;
 486                         eeprom->address_bits = 8;
 487                 }
 488                 eeprom->use_eerd = false;
 489                 eeprom->use_eewr = false;
 490                 break;
 491         case e1000_82573:
 492         case e1000_82574:
 493                 eeprom->type = e1000_eeprom_spi;
 494                 eeprom->opcode_bits = 8;
 495                 eeprom->delay_usec = 1;
 496                 if (eecd & E1000_EECD_ADDR_BITS) {
 497                         eeprom->page_size = 32;
 498                         eeprom->address_bits = 16;
 499                 } else {
 500                         eeprom->page_size = 8;
 501                         eeprom->address_bits = 8;
 502                 }
 503                 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 504                         eeprom->use_eerd = true;
 505                         eeprom->use_eewr = true;
 506
 507                         eeprom->type = e1000_eeprom_flash;
 508                         eeprom->word_size = 2048;
 509
 510                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 511                  * Flash update issue on parts which use a FLASH for NVM. */
 512                         eecd &= ~E1000_EECD_AUPDEN;
 513                         E1000_WRITE_REG(hw, EECD, eecd);
 514                 }
 515                 break;
 516         case e1000_80003es2lan:
 517                 eeprom->type = e1000_eeprom_spi;
 518                 eeprom->opcode_bits = 8;
 519                 eeprom->delay_usec = 1;
 520                 if (eecd & E1000_EECD_ADDR_BITS) {
 521                         eeprom->page_size = 32;
 522                         eeprom->address_bits = 16;
 523                 } else {
 524                         eeprom->page_size = 8;
 525                         eeprom->address_bits = 8;
 526                 }
 527                 eeprom->use_eerd = true;
 528                 eeprom->use_eewr = false;
 529                 break;
 530         case e1000_igb:
 531                 /* i210 has 4k of iNVM mapped as EEPROM */
 532                 eeprom->type = e1000_eeprom_invm;
 533                 eeprom->opcode_bits = 8;
 534                 eeprom->delay_usec = 1;
 535                 eeprom->page_size = 32;
 536                 eeprom->address_bits = 16;
 537                 eeprom->use_eerd = true;
 538                 eeprom->use_eewr = false;
 539                 break;
 540
 541         /* ich8lan does not support currently. if needed, please
 542          * add corresponding code and functions.
 543          */
 544 #if 0
 545         case e1000_ich8lan:
 546                 {
 547                 int32_t  i = 0;
 548
 549                 eeprom->type = e1000_eeprom_ich8;
 550                 eeprom->use_eerd = false;
 551                 eeprom->use_eewr = false;
 552                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 553                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 554                                 ICH_FLASH_GFPREG);
 555                 /* Zero the shadow RAM structure. But don't load it from NVM
 556                  * so as to save time for driver init */
 557                 if (hw->eeprom_shadow_ram != NULL) {
 558                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 559                                 hw->eeprom_shadow_ram[i].modified = false;
 560                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 561                         }
 562                 }
 563
 564                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 565                                 ICH_FLASH_SECTOR_SIZE;
 566
 567                 hw->flash_bank_size = ((flash_size >> 16)
 568                                 & ICH_GFPREG_BASE_MASK) + 1;
 569                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 570
 571                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 572
 573                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 574                 break;
 575                 }
 576 #endif
 577         default:
 578                 break;
 579         }
 580
 581         if (eeprom->type == e1000_eeprom_spi ||
 582             eeprom->type == e1000_eeprom_invm) {
 583                 /* eeprom_size will be an enum [0..8] that maps
 584                  * to eeprom sizes 128B to
 585                  * 32KB (incremented by powers of 2).
 586                  */
 587                 if (hw->mac_type <= e1000_82547_rev_2) {
 588                         /* Set to default value for initial eeprom read. */
 589                         eeprom->word_size = 64;
 590                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 591                                         &eeprom_size);
 592                         if (ret_val)
 593                                 return ret_val;
 594                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 595                                 >> EEPROM_SIZE_SHIFT;
 596                         /* 256B eeprom size was not supported in earlier
 597                          * hardware, so we bump eeprom_size up one to
 598                          * ensure that "1" (which maps to 256B) is never
 599                          * the result used in the shifting logic below. */
 600                         if (eeprom_size)
 601                                 eeprom_size++;
 602                 } else {
 603                         eeprom_size = (uint16_t)((eecd &
 604                                 E1000_EECD_SIZE_EX_MASK) >>
 605                                 E1000_EECD_SIZE_EX_SHIFT);
 606                 }
 607
 608                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 609         }
 610         return ret_val;
 611 }
 612
 613 /******************************************************************************
 614  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 615  *
 616  * hw - Struct containing variables accessed by shared code
 617  *****************************************************************************/
 618 static int32_t
 619 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 620 {
 621         uint32_t attempts = 100000;
 622         uint32_t i, reg = 0;
 623         int32_t done = E1000_ERR_EEPROM;
 624
 625         for (i = 0; i < attempts; i++) {
 626                 if (eerd == E1000_EEPROM_POLL_READ) {
 627                         if (hw->mac_type == e1000_igb)
 628                                 reg = E1000_READ_REG(hw, I210_EERD);
 629                         else
 630                                 reg = E1000_READ_REG(hw, EERD);
 631                 } else {
 632                         if (hw->mac_type == e1000_igb)
 633                                 reg = E1000_READ_REG(hw, I210_EEWR);
 634                         else
 635                                 reg = E1000_READ_REG(hw, EEWR);
 636                 }
 637
 638                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 639                         done = E1000_SUCCESS;
 640                         break;
 641                 }
 642                 udelay(5);
 643         }
 644
 645         return done;
 646 }
 647
 648 /******************************************************************************
 649  * Reads a 16 bit word from the EEPROM using the EERD register.
 650  *
 651  * hw - Struct containing variables accessed by shared code
 652  * offset - offset of  word in the EEPROM to read
 653  * data - word read from the EEPROM
 654  * words - number of words to read
 655  *****************************************************************************/
 656 static int32_t
 657 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 658                         uint16_t offset,
 659                         uint16_t words,
 660                         uint16_t *data)
 661 {
 662         uint32_t i, eerd = 0;
 663         int32_t error = 0;
 664
 665         for (i = 0; i < words; i++) {
 666                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 667                         E1000_EEPROM_RW_REG_START;
 668
 669                 if (hw->mac_type == e1000_igb)
 670                         E1000_WRITE_REG(hw, I210_EERD, eerd);
 671                 else
 672                         E1000_WRITE_REG(hw, EERD, eerd);
 673
 674                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 675
 676                 if (error)
 677                         break;
 678
 679                 if (hw->mac_type == e1000_igb) {
 680                         data[i] = (E1000_READ_REG(hw, I210_EERD) >>
 681                                 E1000_EEPROM_RW_REG_DATA);
 682                 } else {
 683                         data[i] = (E1000_READ_REG(hw, EERD) >>
 684                                 E1000_EEPROM_RW_REG_DATA);
 685                 }
 686
 687         }
 688
 689         return error;
 690 }
 691
 692 void e1000_release_eeprom(struct e1000_hw *hw)
 693 {
 694         uint32_t eecd;
 695
 696         DEBUGFUNC();
 697
 698         eecd = E1000_READ_REG(hw, EECD);
 699
 700         if (hw->eeprom.type == e1000_eeprom_spi) {
 701                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 702                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 703
 704                 E1000_WRITE_REG(hw, EECD, eecd);
 705
 706                 udelay(hw->eeprom.delay_usec);
 707         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 708                 /* cleanup eeprom */
 709
 710                 /* CS on Microwire is active-high */
 711                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 712
 713                 E1000_WRITE_REG(hw, EECD, eecd);
 714
 715                 /* Rising edge of clock */
 716                 eecd |= E1000_EECD_SK;
 717                 E1000_WRITE_REG(hw, EECD, eecd);
 718                 E1000_WRITE_FLUSH(hw);
 719                 udelay(hw->eeprom.delay_usec);
 720
 721                 /* Falling edge of clock */
 722                 eecd &= ~E1000_EECD_SK;
 723                 E1000_WRITE_REG(hw, EECD, eecd);
 724                 E1000_WRITE_FLUSH(hw);
 725                 udelay(hw->eeprom.delay_usec);
 726         }
 727
 728         /* Stop requesting EEPROM access */
 729         if (hw->mac_type > e1000_82544) {
 730                 eecd &= ~E1000_EECD_REQ;
 731                 E1000_WRITE_REG(hw, EECD, eecd);
 732         }
 733
 734         e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 735 }
 736
 737 /******************************************************************************
 738  * Reads a 16 bit word from the EEPROM.
 739  *
 740  * hw - Struct containing variables accessed by shared code
 741  *****************************************************************************/
 742 static int32_t
 743 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 744 {
 745         uint16_t retry_count = 0;
 746         uint8_t spi_stat_reg;
 747
 748         DEBUGFUNC();
 749
 750         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 751          * EEPROM will signal that the command has been completed by clearing
 752          * bit 0 of the internal status register.  If it's not cleared within
 753          * 5 milliseconds, then error out.
 754          */
 755         retry_count = 0;
 756         do {
 757                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 758                         hw->eeprom.opcode_bits);
 759                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 760                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 761                         break;
 762
 763                 udelay(5);
 764                 retry_count += 5;
 765
 766                 e1000_standby_eeprom(hw);
 767         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 768
 769         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 770          * only 0-5mSec on 5V devices)
 771          */
 772         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 773                 DEBUGOUT("SPI EEPROM Status error\n");
 774                 return -E1000_ERR_EEPROM;
 775         }
 776
 777         return E1000_SUCCESS;
 778 }
 779
 780 /******************************************************************************
 781  * Reads a 16 bit word from the EEPROM.
 782  *
 783  * hw - Struct containing variables accessed by shared code
 784  * offset - offset of  word in the EEPROM to read
 785  * data - word read from the EEPROM
 786  *****************************************************************************/
 787 static int32_t
 788 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 789                 uint16_t words, uint16_t *data)
 790 {
 791         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 792         uint32_t i = 0;
 793
 794         DEBUGFUNC();
 795
 796         /* If eeprom is not yet detected, do so now */
 797         if (eeprom->word_size == 0)
 798                 e1000_init_eeprom_params(hw);
 799
 800         /* A check for invalid values:  offset too large, too many words,
 801          * and not enough words.
 802          */
 803         if ((offset >= eeprom->word_size) ||
 804                 (words > eeprom->word_size - offset) ||
 805                 (words == 0)) {
 806                 DEBUGOUT("\"words\" parameter out of bounds."
 807                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 808                 return -E1000_ERR_EEPROM;
 809         }
 810
 811         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 812          * directly. In this case, we need to acquire the EEPROM so that
 813          * FW or other port software does not interrupt.
 814          */
 815         if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 816                 hw->eeprom.use_eerd == false) {
 817
 818                 /* Prepare the EEPROM for bit-bang reading */
 819                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 820                         return -E1000_ERR_EEPROM;
 821         }
 822
 823         /* Eerd register EEPROM access requires no eeprom aquire/release */
 824         if (eeprom->use_eerd == true)
 825                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 826
 827         /* ich8lan does not support currently. if needed, please
 828          * add corresponding code and functions.
 829          */
 830 #if 0
 831         /* ICH EEPROM access is done via the ICH flash controller */
 832         if (eeprom->type == e1000_eeprom_ich8)
 833                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 834 #endif
 835         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 836          * acquired the EEPROM at this point, so any returns should relase it */
 837         if (eeprom->type == e1000_eeprom_spi) {
 838                 uint16_t word_in;
 839                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 840
 841                 if (e1000_spi_eeprom_ready(hw)) {
 842                         e1000_release_eeprom(hw);
 843                         return -E1000_ERR_EEPROM;
 844                 }
 845
 846                 e1000_standby_eeprom(hw);
 847
 848                 /* Some SPI eeproms use the 8th address bit embedded in
 849                  * the opcode */
 850                 if ((eeprom->address_bits == 8) && (offset >= 128))
 851                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 852
 853                 /* Send the READ command (opcode + addr)  */
 854                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 855                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 856                                 eeprom->address_bits);
 857
 858                 /* Read the data.  The address of the eeprom internally
 859                  * increments with each byte (spi) being read, saving on the
 860                  * overhead of eeprom setup and tear-down.  The address
 861                  * counter will roll over if reading beyond the size of
 862                  * the eeprom, thus allowing the entire memory to be read
 863                  * starting from any offset. */
 864                 for (i = 0; i < words; i++) {
 865                         word_in = e1000_shift_in_ee_bits(hw, 16);
 866                         data[i] = (word_in >> 8) | (word_in << 8);
 867                 }
 868         } else if (eeprom->type == e1000_eeprom_microwire) {
 869                 for (i = 0; i < words; i++) {
 870                         /* Send the READ command (opcode + addr)  */
 871                         e1000_shift_out_ee_bits(hw,
 872                                 EEPROM_READ_OPCODE_MICROWIRE,
 873                                 eeprom->opcode_bits);
 874                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 875                                 eeprom->address_bits);
 876
 877                         /* Read the data.  For microwire, each word requires
 878                          * the overhead of eeprom setup and tear-down. */
 879                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 880                         e1000_standby_eeprom(hw);
 881                 }
 882         }
 883
 884         /* End this read operation */
 885         e1000_release_eeprom(hw);
 886
 887         return E1000_SUCCESS;
 888 }
 889
 890 /******************************************************************************
 891  * Verifies that the EEPROM has a valid checksum
 892  *
 893  * hw - Struct containing variables accessed by shared code
 894  *
 895  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 896  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 897  * valid.
 898  *****************************************************************************/
 899 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 900 {
 901         uint16_t i, checksum, checksum_reg, *buf;
 902
 903         DEBUGFUNC();
 904
 905         /* Allocate a temporary buffer */
 906         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
 907         if (!buf) {
 908                 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
 909                 return -E1000_ERR_EEPROM;
 910         }
 911
 912         /* Read the EEPROM */
 913         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
 914                 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
 915                 return -E1000_ERR_EEPROM;
 916         }
 917
 918         /* Compute the checksum */
 919         checksum = 0;
 920         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
 921                 checksum += buf[i];
 922         checksum = ((uint16_t)EEPROM_SUM) - checksum;
 923         checksum_reg = buf[i];
 924
 925         /* Verify it! */
 926         if (checksum == checksum_reg)
 927                 return 0;
 928
 929         /* Hrm, verification failed, print an error */
 930         E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
 931         E1000_ERR(hw->nic, "  ...register was 0x%04hx, calculated 0x%04hx\n",
 932                         checksum_reg, checksum);
 933
 934         return -E1000_ERR_EEPROM;
 935 }
 936 #endif /* CONFIG_E1000_NO_NVM */
 937
 938 /*****************************************************************************
 939  * Set PHY to class A mode
 940  * Assumes the following operations will follow to enable the new class mode.
 941  *  1. Do a PHY soft reset
 942  *  2. Restart auto-negotiation or force link.
 943  *
 944  * hw - Struct containing variables accessed by shared code
 945  ****************************************************************************/
 946 static int32_t
 947 e1000_set_phy_mode(struct e1000_hw *hw)
 948 {
 949 #ifndef CONFIG_E1000_NO_NVM
 950         int32_t ret_val;
 951         uint16_t eeprom_data;
 952
 953         DEBUGFUNC();
 954
 955         if ((hw->mac_type == e1000_82545_rev_3) &&
 956                 (hw->media_type == e1000_media_type_copper)) {
 957                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 958                                 1, &eeprom_data);
 959                 if (ret_val)
 960                         return ret_val;
 961
 962                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 963                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 964                         ret_val = e1000_write_phy_reg(hw,
 965                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 966                         if (ret_val)
 967                                 return ret_val;
 968                         ret_val = e1000_write_phy_reg(hw,
 969                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 970                         if (ret_val)
 971                                 return ret_val;
 972
 973                         hw->phy_reset_disable = false;
 974                 }
 975         }
 976 #endif
 977         return E1000_SUCCESS;
 978 }
 979
 980 #ifndef CONFIG_E1000_NO_NVM
 981 /***************************************************************************
 982  *
 983  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 984  *
 985  * hw: Struct containing variables accessed by shared code
 986  *
 987  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 988  *            E1000_SUCCESS at any other case.
 989  *
 990  ***************************************************************************/
 991 static int32_t
 992 e1000_get_software_semaphore(struct e1000_hw *hw)
 993 {
 994          int32_t timeout = hw->eeprom.word_size + 1;
 995          uint32_t swsm;
 996
 997         DEBUGFUNC();
 998
 999                 swsm = E1000_READ_REG(hw, SWSM);
1000                 swsm &= ~E1000_SWSM_SMBI;
1001                 E1000_WRITE_REG(hw, SWSM, swsm);
1002
1003         if (hw->mac_type != e1000_80003es2lan)
1004                 return E1000_SUCCESS;
1005
1006         while (timeout) {
1007                 swsm = E1000_READ_REG(hw, SWSM);
1008                 /* If SMBI bit cleared, it is now set and we hold
1009                  * the semaphore */
1010                 if (!(swsm & E1000_SWSM_SMBI))
1011                         break;
1012                 mdelay(1);
1013                 timeout--;
1014         }
1015
1016         if (!timeout) {
1017                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1018                 return -E1000_ERR_RESET;
1019         }
1020
1021         return E1000_SUCCESS;
1022 }
1023 #endif
1024
1025 /***************************************************************************
1026  * This function clears HW semaphore bits.
1027  *
1028  * hw: Struct containing variables accessed by shared code
1029  *
1030  * returns: - None.
1031  *
1032  ***************************************************************************/
1033 static void
1034 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1035 {
1036 #ifndef CONFIG_E1000_NO_NVM
1037          uint32_t swsm;
1038
1039         DEBUGFUNC();
1040
1041         if (!hw->eeprom_semaphore_present)
1042                 return;
1043
1044         swsm = E1000_READ_REG(hw, SWSM);
1045         if (hw->mac_type == e1000_80003es2lan) {
1046                 /* Release both semaphores. */
1047                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1048         } else
1049                 swsm &= ~(E1000_SWSM_SWESMBI);
1050         E1000_WRITE_REG(hw, SWSM, swsm);
1051 #endif
1052 }
1053
1054 /***************************************************************************
1055  *
1056  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1057  * adapter or Eeprom access.
1058  *
1059  * hw: Struct containing variables accessed by shared code
1060  *
1061  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1062  *            E1000_SUCCESS at any other case.
1063  *
1064  ***************************************************************************/
1065 static int32_t
1066 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1067 {
1068 #ifndef CONFIG_E1000_NO_NVM
1069         int32_t timeout;
1070         uint32_t swsm;
1071
1072         DEBUGFUNC();
1073
1074         if (!hw->eeprom_semaphore_present)
1075                 return E1000_SUCCESS;
1076
1077         if (hw->mac_type == e1000_80003es2lan) {
1078                 /* Get the SW semaphore. */
1079                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1080                         return -E1000_ERR_EEPROM;
1081         }
1082
1083         /* Get the FW semaphore. */
1084         timeout = hw->eeprom.word_size + 1;
1085         while (timeout) {
1086                 swsm = E1000_READ_REG(hw, SWSM);
1087                 swsm |= E1000_SWSM_SWESMBI;
1088                 E1000_WRITE_REG(hw, SWSM, swsm);
1089                 /* if we managed to set the bit we got the semaphore. */
1090                 swsm = E1000_READ_REG(hw, SWSM);
1091                 if (swsm & E1000_SWSM_SWESMBI)
1092                         break;
1093
1094                 udelay(50);
1095                 timeout--;
1096         }
1097
1098         if (!timeout) {
1099                 /* Release semaphores */
1100                 e1000_put_hw_eeprom_semaphore(hw);
1101                 DEBUGOUT("Driver can't access the Eeprom - "
1102                                 "SWESMBI bit is set.\n");
1103                 return -E1000_ERR_EEPROM;
1104         }
1105 #endif
1106         return E1000_SUCCESS;
1107 }
1108
1109 /* Take ownership of the PHY */
1110 static int32_t
1111 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1112 {
1113         uint32_t swfw_sync = 0;
1114         uint32_t swmask = mask;
1115         uint32_t fwmask = mask << 16;
1116         int32_t timeout = 200;
1117
1118         DEBUGFUNC();
1119         while (timeout) {
1120                 if (e1000_get_hw_eeprom_semaphore(hw))
1121                         return -E1000_ERR_SWFW_SYNC;
1122
1123                 if (hw->mac_type == e1000_igb)
1124                         swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
1125                 else
1126                         swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1127                 if (!(swfw_sync & (fwmask | swmask)))
1128                         break;
1129
1130                 /* firmware currently using resource (fwmask) */
1131                 /* or other software thread currently using resource (swmask) */
1132                 e1000_put_hw_eeprom_semaphore(hw);
1133                 mdelay(5);
1134                 timeout--;
1135         }
1136
1137         if (!timeout) {
1138                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1139                 return -E1000_ERR_SWFW_SYNC;
1140         }
1141
1142         swfw_sync |= swmask;
1143         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1144
1145         e1000_put_hw_eeprom_semaphore(hw);
1146         return E1000_SUCCESS;
1147 }
1148
1149 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1150 {
1151         uint32_t swfw_sync = 0;
1152
1153         DEBUGFUNC();
1154         while (e1000_get_hw_eeprom_semaphore(hw))
1155                 ; /* Empty */
1156
1157         swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1158         swfw_sync &= ~mask;
1159         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1160
1161         e1000_put_hw_eeprom_semaphore(hw);
1162 }
1163
1164 static bool e1000_is_second_port(struct e1000_hw *hw)
1165 {
1166         switch (hw->mac_type) {
1167         case e1000_80003es2lan:
1168         case e1000_82546:
1169         case e1000_82571:
1170                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1171                         return true;
1172                 /* Fallthrough */
1173         default:
1174                 return false;
1175         }
1176 }
1177
1178 #ifndef CONFIG_E1000_NO_NVM
1179 /******************************************************************************
1180  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1181  * second function of dual function devices
1182  *
1183  * nic - Struct containing variables accessed by shared code
1184  *****************************************************************************/
1185 static int
1186 e1000_read_mac_addr(struct eth_device *nic)
1187 {
1188         struct e1000_hw *hw = nic->priv;
1189         uint16_t offset;
1190         uint16_t eeprom_data;
1191         uint32_t reg_data = 0;
1192         int i;
1193
1194         DEBUGFUNC();
1195
1196         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1197                 offset = i >> 1;
1198                 if (hw->mac_type == e1000_igb) {
1199                         /* i210 preloads MAC address into RAL/RAH registers */
1200                         if (offset == 0)
1201                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1202                         else if (offset == 1)
1203                                 reg_data >>= 16;
1204                         else if (offset == 2)
1205                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1206                         eeprom_data = reg_data & 0xffff;
1207                 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1208                         DEBUGOUT("EEPROM Read Error\n");
1209                         return -E1000_ERR_EEPROM;
1210                 }
1211                 nic->enetaddr[i] = eeprom_data & 0xff;
1212                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1213         }
1214
1215         /* Invert the last bit if this is the second device */
1216         if (e1000_is_second_port(hw))
1217                 nic->enetaddr[5] ^= 1;
1218
1219 #ifdef CONFIG_E1000_FALLBACK_MAC
1220         if (!is_valid_ethaddr(nic->enetaddr)) {
1221                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1222
1223                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1224         }
1225 #endif
1226         return 0;
1227 }
1228 #endif
1229
1230 /******************************************************************************
1231  * Initializes receive address filters.
1232  *
1233  * hw - Struct containing variables accessed by shared code
1234  *
1235  * Places the MAC address in receive address register 0 and clears the rest
1236  * of the receive addresss registers. Clears the multicast table. Assumes
1237  * the receiver is in reset when the routine is called.
1238  *****************************************************************************/
1239 static void
1240 e1000_init_rx_addrs(struct eth_device *nic)
1241 {
1242         struct e1000_hw *hw = nic->priv;
1243         uint32_t i;
1244         uint32_t addr_low;
1245         uint32_t addr_high;
1246
1247         DEBUGFUNC();
1248
1249         /* Setup the receive address. */
1250         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1251         addr_low = (nic->enetaddr[0] |
1252                     (nic->enetaddr[1] << 8) |
1253                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1254
1255         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1256
1257         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1258         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1259
1260         /* Zero out the other 15 receive addresses. */
1261         DEBUGOUT("Clearing RAR[1-15]\n");
1262         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1263                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1264                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1265         }
1266 }
1267
1268 /******************************************************************************
1269  * Clears the VLAN filer table
1270  *
1271  * hw - Struct containing variables accessed by shared code
1272  *****************************************************************************/
1273 static void
1274 e1000_clear_vfta(struct e1000_hw *hw)
1275 {
1276         uint32_t offset;
1277
1278         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1279                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1280 }
1281
1282 /******************************************************************************
1283  * Set the mac type member in the hw struct.
1284  *
1285  * hw - Struct containing variables accessed by shared code
1286  *****************************************************************************/
1287 int32_t
1288 e1000_set_mac_type(struct e1000_hw *hw)
1289 {
1290         DEBUGFUNC();
1291
1292         switch (hw->device_id) {
1293         case E1000_DEV_ID_82542:
1294                 switch (hw->revision_id) {
1295                 case E1000_82542_2_0_REV_ID:
1296                         hw->mac_type = e1000_82542_rev2_0;
1297                         break;
1298                 case E1000_82542_2_1_REV_ID:
1299                         hw->mac_type = e1000_82542_rev2_1;
1300                         break;
1301                 default:
1302                         /* Invalid 82542 revision ID */
1303                         return -E1000_ERR_MAC_TYPE;
1304                 }
1305                 break;
1306         case E1000_DEV_ID_82543GC_FIBER:
1307         case E1000_DEV_ID_82543GC_COPPER:
1308                 hw->mac_type = e1000_82543;
1309                 break;
1310         case E1000_DEV_ID_82544EI_COPPER:
1311         case E1000_DEV_ID_82544EI_FIBER:
1312         case E1000_DEV_ID_82544GC_COPPER:
1313         case E1000_DEV_ID_82544GC_LOM:
1314                 hw->mac_type = e1000_82544;
1315                 break;
1316         case E1000_DEV_ID_82540EM:
1317         case E1000_DEV_ID_82540EM_LOM:
1318         case E1000_DEV_ID_82540EP:
1319         case E1000_DEV_ID_82540EP_LOM:
1320         case E1000_DEV_ID_82540EP_LP:
1321                 hw->mac_type = e1000_82540;
1322                 break;
1323         case E1000_DEV_ID_82545EM_COPPER:
1324         case E1000_DEV_ID_82545EM_FIBER:
1325                 hw->mac_type = e1000_82545;
1326                 break;
1327         case E1000_DEV_ID_82545GM_COPPER:
1328         case E1000_DEV_ID_82545GM_FIBER:
1329         case E1000_DEV_ID_82545GM_SERDES:
1330                 hw->mac_type = e1000_82545_rev_3;
1331                 break;
1332         case E1000_DEV_ID_82546EB_COPPER:
1333         case E1000_DEV_ID_82546EB_FIBER:
1334         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1335                 hw->mac_type = e1000_82546;
1336                 break;
1337         case E1000_DEV_ID_82546GB_COPPER:
1338         case E1000_DEV_ID_82546GB_FIBER:
1339         case E1000_DEV_ID_82546GB_SERDES:
1340         case E1000_DEV_ID_82546GB_PCIE:
1341         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1342         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1343                 hw->mac_type = e1000_82546_rev_3;
1344                 break;
1345         case E1000_DEV_ID_82541EI:
1346         case E1000_DEV_ID_82541EI_MOBILE:
1347         case E1000_DEV_ID_82541ER_LOM:
1348                 hw->mac_type = e1000_82541;
1349                 break;
1350         case E1000_DEV_ID_82541ER:
1351         case E1000_DEV_ID_82541GI:
1352         case E1000_DEV_ID_82541GI_LF:
1353         case E1000_DEV_ID_82541GI_MOBILE:
1354                 hw->mac_type = e1000_82541_rev_2;
1355                 break;
1356         case E1000_DEV_ID_82547EI:
1357         case E1000_DEV_ID_82547EI_MOBILE:
1358                 hw->mac_type = e1000_82547;
1359                 break;
1360         case E1000_DEV_ID_82547GI:
1361                 hw->mac_type = e1000_82547_rev_2;
1362                 break;
1363         case E1000_DEV_ID_82571EB_COPPER:
1364         case E1000_DEV_ID_82571EB_FIBER:
1365         case E1000_DEV_ID_82571EB_SERDES:
1366         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1367         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1368         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1369         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1370         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1371         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1372                 hw->mac_type = e1000_82571;
1373                 break;
1374         case E1000_DEV_ID_82572EI_COPPER:
1375         case E1000_DEV_ID_82572EI_FIBER:
1376         case E1000_DEV_ID_82572EI_SERDES:
1377         case E1000_DEV_ID_82572EI:
1378                 hw->mac_type = e1000_82572;
1379                 break;
1380         case E1000_DEV_ID_82573E:
1381         case E1000_DEV_ID_82573E_IAMT:
1382         case E1000_DEV_ID_82573L:
1383                 hw->mac_type = e1000_82573;
1384                 break;
1385         case E1000_DEV_ID_82574L:
1386                 hw->mac_type = e1000_82574;
1387                 break;
1388         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1389         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1390         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1391         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1392                 hw->mac_type = e1000_80003es2lan;
1393                 break;
1394         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1395         case E1000_DEV_ID_ICH8_IGP_AMT:
1396         case E1000_DEV_ID_ICH8_IGP_C:
1397         case E1000_DEV_ID_ICH8_IFE:
1398         case E1000_DEV_ID_ICH8_IFE_GT:
1399         case E1000_DEV_ID_ICH8_IFE_G:
1400         case E1000_DEV_ID_ICH8_IGP_M:
1401                 hw->mac_type = e1000_ich8lan;
1402                 break;
1403         case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1404         case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1405         case PCI_DEVICE_ID_INTEL_I210_COPPER:
1406         case PCI_DEVICE_ID_INTEL_I211_COPPER:
1407         case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1408         case PCI_DEVICE_ID_INTEL_I210_SERDES:
1409         case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1410         case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1411                 hw->mac_type = e1000_igb;
1412                 break;
1413         default:
1414                 /* Should never have loaded on this device */
1415                 return -E1000_ERR_MAC_TYPE;
1416         }
1417         return E1000_SUCCESS;
1418 }
1419
1420 /******************************************************************************
1421  * Reset the transmit and receive units; mask and clear all interrupts.
1422  *
1423  * hw - Struct containing variables accessed by shared code
1424  *****************************************************************************/
1425 void
1426 e1000_reset_hw(struct e1000_hw *hw)
1427 {
1428         uint32_t ctrl;
1429         uint32_t ctrl_ext;
1430         uint32_t manc;
1431         uint32_t pba = 0;
1432         uint32_t reg;
1433
1434         DEBUGFUNC();
1435
1436         /* get the correct pba value for both PCI and PCIe*/
1437         if (hw->mac_type <  e1000_82571)
1438                 pba = E1000_DEFAULT_PCI_PBA;
1439         else
1440                 pba = E1000_DEFAULT_PCIE_PBA;
1441
1442         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1443         if (hw->mac_type == e1000_82542_rev2_0) {
1444                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1445                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1446                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1447         }
1448
1449         /* Clear interrupt mask to stop board from generating interrupts */
1450         DEBUGOUT("Masking off all interrupts\n");
1451         if (hw->mac_type == e1000_igb)
1452                 E1000_WRITE_REG(hw, I210_IAM, 0);
1453         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1454
1455         /* Disable the Transmit and Receive units.  Then delay to allow
1456          * any pending transactions to complete before we hit the MAC with
1457          * the global reset.
1458          */
1459         E1000_WRITE_REG(hw, RCTL, 0);
1460         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1461         E1000_WRITE_FLUSH(hw);
1462
1463         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1464         hw->tbi_compatibility_on = false;
1465
1466         /* Delay to allow any outstanding PCI transactions to complete before
1467          * resetting the device
1468          */
1469         mdelay(10);
1470
1471         /* Issue a global reset to the MAC.  This will reset the chip's
1472          * transmit, receive, DMA, and link units.  It will not effect
1473          * the current PCI configuration.  The global reset bit is self-
1474          * clearing, and should clear within a microsecond.
1475          */
1476         DEBUGOUT("Issuing a global reset to MAC\n");
1477         ctrl = E1000_READ_REG(hw, CTRL);
1478
1479         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1480
1481         /* Force a reload from the EEPROM if necessary */
1482         if (hw->mac_type == e1000_igb) {
1483                 mdelay(20);
1484                 reg = E1000_READ_REG(hw, STATUS);
1485                 if (reg & E1000_STATUS_PF_RST_DONE)
1486                         DEBUGOUT("PF OK\n");
1487                 reg = E1000_READ_REG(hw, I210_EECD);
1488                 if (reg & E1000_EECD_AUTO_RD)
1489                         DEBUGOUT("EEC OK\n");
1490         } else if (hw->mac_type < e1000_82540) {
1491                 /* Wait for reset to complete */
1492                 udelay(10);
1493                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1494                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1495                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1496                 E1000_WRITE_FLUSH(hw);
1497                 /* Wait for EEPROM reload */
1498                 mdelay(2);
1499         } else {
1500                 /* Wait for EEPROM reload (it happens automatically) */
1501                 mdelay(4);
1502                 /* Dissable HW ARPs on ASF enabled adapters */
1503                 manc = E1000_READ_REG(hw, MANC);
1504                 manc &= ~(E1000_MANC_ARP_EN);
1505                 E1000_WRITE_REG(hw, MANC, manc);
1506         }
1507
1508         /* Clear interrupt mask to stop board from generating interrupts */
1509         DEBUGOUT("Masking off all interrupts\n");
1510         if (hw->mac_type == e1000_igb)
1511                 E1000_WRITE_REG(hw, I210_IAM, 0);
1512         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1513
1514         /* Clear any pending interrupt events. */
1515         E1000_READ_REG(hw, ICR);
1516
1517         /* If MWI was previously enabled, reenable it. */
1518         if (hw->mac_type == e1000_82542_rev2_0) {
1519                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1520         }
1521         if (hw->mac_type != e1000_igb)
1522                 E1000_WRITE_REG(hw, PBA, pba);
1523 }
1524
1525 /******************************************************************************
1526  *
1527  * Initialize a number of hardware-dependent bits
1528  *
1529  * hw: Struct containing variables accessed by shared code
1530  *
1531  * This function contains hardware limitation workarounds for PCI-E adapters
1532  *
1533  *****************************************************************************/
1534 static void
1535 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1536 {
1537         if ((hw->mac_type >= e1000_82571) &&
1538                         (!hw->initialize_hw_bits_disable)) {
1539                 /* Settings common to all PCI-express silicon */
1540                 uint32_t reg_ctrl, reg_ctrl_ext;
1541                 uint32_t reg_tarc0, reg_tarc1;
1542                 uint32_t reg_tctl;
1543                 uint32_t reg_txdctl, reg_txdctl1;
1544
1545                 /* link autonegotiation/sync workarounds */
1546                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1547                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1548
1549                 /* Enable not-done TX descriptor counting */
1550                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1551                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1552                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1553
1554                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1555                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1556                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1557
1558         /* IGB is cool */
1559         if (hw->mac_type == e1000_igb)
1560                 return;
1561
1562                 switch (hw->mac_type) {
1563                 case e1000_82571:
1564                 case e1000_82572:
1565                         /* Clear PHY TX compatible mode bits */
1566                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1567                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1568
1569                         /* link autonegotiation/sync workarounds */
1570                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1571
1572                         /* TX ring control fixes */
1573                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1574
1575                         /* Multiple read bit is reversed polarity */
1576                         reg_tctl = E1000_READ_REG(hw, TCTL);
1577                         if (reg_tctl & E1000_TCTL_MULR)
1578                                 reg_tarc1 &= ~(1 << 28);
1579                         else
1580                                 reg_tarc1 |= (1 << 28);
1581
1582                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1583                         break;
1584                 case e1000_82573:
1585                 case e1000_82574:
1586                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1587                         reg_ctrl_ext &= ~(1 << 23);
1588                         reg_ctrl_ext |= (1 << 22);
1589
1590                         /* TX byte count fix */
1591                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1592                         reg_ctrl &= ~(1 << 29);
1593
1594                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1595                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1596                         break;
1597                 case e1000_80003es2lan:
1598         /* improve small packet performace for fiber/serdes */
1599                         if ((hw->media_type == e1000_media_type_fiber)
1600                         || (hw->media_type ==
1601                                 e1000_media_type_internal_serdes)) {
1602                                 reg_tarc0 &= ~(1 << 20);
1603                         }
1604
1605                 /* Multiple read bit is reversed polarity */
1606                         reg_tctl = E1000_READ_REG(hw, TCTL);
1607                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1608                         if (reg_tctl & E1000_TCTL_MULR)
1609                                 reg_tarc1 &= ~(1 << 28);
1610                         else
1611                                 reg_tarc1 |= (1 << 28);
1612
1613                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1614                         break;
1615                 case e1000_ich8lan:
1616                         /* Reduce concurrent DMA requests to 3 from 4 */
1617                         if ((hw->revision_id < 3) ||
1618                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1619                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1620                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1621
1622                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1623                         reg_ctrl_ext |= (1 << 22);
1624                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1625
1626                         /* workaround TX hang with TSO=on */
1627                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1628
1629                         /* Multiple read bit is reversed polarity */
1630                         reg_tctl = E1000_READ_REG(hw, TCTL);
1631                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1632                         if (reg_tctl & E1000_TCTL_MULR)
1633                                 reg_tarc1 &= ~(1 << 28);
1634                         else
1635                                 reg_tarc1 |= (1 << 28);
1636
1637                         /* workaround TX hang with TSO=on */
1638                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1639
1640                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1641                         break;
1642                 default:
1643                         break;
1644                 }
1645
1646                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1647         }
1648 }
1649
1650 /******************************************************************************
1651  * Performs basic configuration of the adapter.
1652  *
1653  * hw - Struct containing variables accessed by shared code
1654  *
1655  * Assumes that the controller has previously been reset and is in a
1656  * post-reset uninitialized state. Initializes the receive address registers,
1657  * multicast table, and VLAN filter table. Calls routines to setup link
1658  * configuration and flow control settings. Clears all on-chip counters. Leaves
1659  * the transmit and receive units disabled and uninitialized.
1660  *****************************************************************************/
1661 static int
1662 e1000_init_hw(struct eth_device *nic)
1663 {
1664         struct e1000_hw *hw = nic->priv;
1665         uint32_t ctrl;
1666         uint32_t i;
1667         int32_t ret_val;
1668         uint16_t pcix_cmd_word;
1669         uint16_t pcix_stat_hi_word;
1670         uint16_t cmd_mmrbc;
1671         uint16_t stat_mmrbc;
1672         uint32_t mta_size;
1673         uint32_t reg_data;
1674         uint32_t ctrl_ext;
1675         DEBUGFUNC();
1676         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1677         if ((hw->mac_type == e1000_ich8lan) &&
1678                 ((hw->revision_id < 3) ||
1679                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1680                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1681                         reg_data = E1000_READ_REG(hw, STATUS);
1682                         reg_data &= ~0x80000000;
1683                         E1000_WRITE_REG(hw, STATUS, reg_data);
1684         }
1685         /* Do not need initialize Identification LED */
1686
1687         /* Set the media type and TBI compatibility */
1688         e1000_set_media_type(hw);
1689
1690         /* Must be called after e1000_set_media_type
1691          * because media_type is used */
1692         e1000_initialize_hardware_bits(hw);
1693
1694         /* Disabling VLAN filtering. */
1695         DEBUGOUT("Initializing the IEEE VLAN\n");
1696         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1697         if (hw->mac_type != e1000_ich8lan) {
1698                 if (hw->mac_type < e1000_82545_rev_3)
1699                         E1000_WRITE_REG(hw, VET, 0);
1700                 e1000_clear_vfta(hw);
1701         }
1702
1703         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1704         if (hw->mac_type == e1000_82542_rev2_0) {
1705                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1706                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1707                                       hw->
1708                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1709                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1710                 E1000_WRITE_FLUSH(hw);
1711                 mdelay(5);
1712         }
1713
1714         /* Setup the receive address. This involves initializing all of the Receive
1715          * Address Registers (RARs 0 - 15).
1716          */
1717         e1000_init_rx_addrs(nic);
1718
1719         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1720         if (hw->mac_type == e1000_82542_rev2_0) {
1721                 E1000_WRITE_REG(hw, RCTL, 0);
1722                 E1000_WRITE_FLUSH(hw);
1723                 mdelay(1);
1724                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1725         }
1726
1727         /* Zero out the Multicast HASH table */
1728         DEBUGOUT("Zeroing the MTA\n");
1729         mta_size = E1000_MC_TBL_SIZE;
1730         if (hw->mac_type == e1000_ich8lan)
1731                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1732         for (i = 0; i < mta_size; i++) {
1733                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1734                 /* use write flush to prevent Memory Write Block (MWB) from
1735                  * occuring when accessing our register space */
1736                 E1000_WRITE_FLUSH(hw);
1737         }
1738 #if 0
1739         /* Set the PCI priority bit correctly in the CTRL register.  This
1740          * determines if the adapter gives priority to receives, or if it
1741          * gives equal priority to transmits and receives.  Valid only on
1742          * 82542 and 82543 silicon.
1743          */
1744         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1745                 ctrl = E1000_READ_REG(hw, CTRL);
1746                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1747         }
1748 #endif
1749         switch (hw->mac_type) {
1750         case e1000_82545_rev_3:
1751         case e1000_82546_rev_3:
1752         case e1000_igb:
1753                 break;
1754         default:
1755         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1756         if (hw->bus_type == e1000_bus_type_pcix) {
1757                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1758                                      &pcix_cmd_word);
1759                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1760                                      &pcix_stat_hi_word);
1761                 cmd_mmrbc =
1762                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1763                     PCIX_COMMAND_MMRBC_SHIFT;
1764                 stat_mmrbc =
1765                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1766                     PCIX_STATUS_HI_MMRBC_SHIFT;
1767                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1768                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1769                 if (cmd_mmrbc > stat_mmrbc) {
1770                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1771                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1772                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1773                                               pcix_cmd_word);
1774                 }
1775         }
1776                 break;
1777         }
1778
1779         /* More time needed for PHY to initialize */
1780         if (hw->mac_type == e1000_ich8lan)
1781                 mdelay(15);
1782         if (hw->mac_type == e1000_igb)
1783                 mdelay(15);
1784
1785         /* Call a subroutine to configure the link and setup flow control. */
1786         ret_val = e1000_setup_link(nic);
1787
1788         /* Set the transmit descriptor write-back policy */
1789         if (hw->mac_type > e1000_82544) {
1790                 ctrl = E1000_READ_REG(hw, TXDCTL);
1791                 ctrl =
1792                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1793                     E1000_TXDCTL_FULL_TX_DESC_WB;
1794                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1795         }
1796
1797         /* Set the receive descriptor write back policy */
1798         if (hw->mac_type >= e1000_82571) {
1799                 ctrl = E1000_READ_REG(hw, RXDCTL);
1800                 ctrl =
1801                     (ctrl & ~E1000_RXDCTL_WTHRESH) |
1802                     E1000_RXDCTL_FULL_RX_DESC_WB;
1803                 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1804         }
1805
1806         switch (hw->mac_type) {
1807         default:
1808                 break;
1809         case e1000_80003es2lan:
1810                 /* Enable retransmit on late collisions */
1811                 reg_data = E1000_READ_REG(hw, TCTL);
1812                 reg_data |= E1000_TCTL_RTLC;
1813                 E1000_WRITE_REG(hw, TCTL, reg_data);
1814
1815                 /* Configure Gigabit Carry Extend Padding */
1816                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1817                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1818                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1819                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1820
1821                 /* Configure Transmit Inter-Packet Gap */
1822                 reg_data = E1000_READ_REG(hw, TIPG);
1823                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1824                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1825                 E1000_WRITE_REG(hw, TIPG, reg_data);
1826
1827                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1828                 reg_data &= ~0x00100000;
1829                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1830                 /* Fall through */
1831         case e1000_82571:
1832         case e1000_82572:
1833         case e1000_ich8lan:
1834                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1835                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1836                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1837                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1838                 break;
1839         case e1000_82573:
1840         case e1000_82574:
1841                 reg_data = E1000_READ_REG(hw, GCR);
1842                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1843                 E1000_WRITE_REG(hw, GCR, reg_data);
1844         case e1000_igb:
1845                 break;
1846         }
1847
1848 #if 0
1849         /* Clear all of the statistics registers (clear on read).  It is
1850          * important that we do this after we have tried to establish link
1851          * because the symbol error count will increment wildly if there
1852          * is no link.
1853          */
1854         e1000_clear_hw_cntrs(hw);
1855
1856         /* ICH8 No-snoop bits are opposite polarity.
1857          * Set to snoop by default after reset. */
1858         if (hw->mac_type == e1000_ich8lan)
1859                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1860 #endif
1861
1862         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1863                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1864                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1865                 /* Relaxed ordering must be disabled to avoid a parity
1866                  * error crash in a PCI slot. */
1867                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1868                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1869         }
1870
1871         return ret_val;
1872 }
1873
1874 /******************************************************************************
1875  * Configures flow control and link settings.
1876  *
1877  * hw - Struct containing variables accessed by shared code
1878  *
1879  * Determines which flow control settings to use. Calls the apropriate media-
1880  * specific link configuration function. Configures the flow control settings.
1881  * Assuming the adapter has a valid link partner, a valid link should be
1882  * established. Assumes the hardware has previously been reset and the
1883  * transmitter and receiver are not enabled.
1884  *****************************************************************************/
1885 static int
1886 e1000_setup_link(struct eth_device *nic)
1887 {
1888         struct e1000_hw *hw = nic->priv;
1889         int32_t ret_val;
1890 #ifndef CONFIG_E1000_NO_NVM
1891         uint32_t ctrl_ext;
1892         uint16_t eeprom_data;
1893 #endif
1894
1895         DEBUGFUNC();
1896
1897         /* In the case of the phy reset being blocked, we already have a link.
1898          * We do not have to set it up again. */
1899         if (e1000_check_phy_reset_block(hw))
1900                 return E1000_SUCCESS;
1901
1902 #ifndef CONFIG_E1000_NO_NVM
1903         /* Read and store word 0x0F of the EEPROM. This word contains bits
1904          * that determine the hardware's default PAUSE (flow control) mode,
1905          * a bit that determines whether the HW defaults to enabling or
1906          * disabling auto-negotiation, and the direction of the
1907          * SW defined pins. If there is no SW over-ride of the flow
1908          * control setting, then the variable hw->fc will
1909          * be initialized based on a value in the EEPROM.
1910          */
1911         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1912                                 &eeprom_data) < 0) {
1913                 DEBUGOUT("EEPROM Read Error\n");
1914                 return -E1000_ERR_EEPROM;
1915         }
1916 #endif
1917         if (hw->fc == e1000_fc_default) {
1918                 switch (hw->mac_type) {
1919                 case e1000_ich8lan:
1920                 case e1000_82573:
1921                 case e1000_82574:
1922                 case e1000_igb:
1923                         hw->fc = e1000_fc_full;
1924                         break;
1925                 default:
1926 #ifndef CONFIG_E1000_NO_NVM
1927                         ret_val = e1000_read_eeprom(hw,
1928                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1929                         if (ret_val) {
1930                                 DEBUGOUT("EEPROM Read Error\n");
1931                                 return -E1000_ERR_EEPROM;
1932                         }
1933                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1934                                 hw->fc = e1000_fc_none;
1935                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1936                                     EEPROM_WORD0F_ASM_DIR)
1937                                 hw->fc = e1000_fc_tx_pause;
1938                         else
1939 #endif
1940                                 hw->fc = e1000_fc_full;
1941                         break;
1942                 }
1943         }
1944
1945         /* We want to save off the original Flow Control configuration just
1946          * in case we get disconnected and then reconnected into a different
1947          * hub or switch with different Flow Control capabilities.
1948          */
1949         if (hw->mac_type == e1000_82542_rev2_0)
1950                 hw->fc &= (~e1000_fc_tx_pause);
1951
1952         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1953                 hw->fc &= (~e1000_fc_rx_pause);
1954
1955         hw->original_fc = hw->fc;
1956
1957         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1958
1959 #ifndef CONFIG_E1000_NO_NVM
1960         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1961          * polarity value for the SW controlled pins, and setup the
1962          * Extended Device Control reg with that info.
1963          * This is needed because one of the SW controlled pins is used for
1964          * signal detection.  So this should be done before e1000_setup_pcs_link()
1965          * or e1000_phy_setup() is called.
1966          */
1967         if (hw->mac_type == e1000_82543) {
1968                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1969                             SWDPIO__EXT_SHIFT);
1970                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1971         }
1972 #endif
1973
1974         /* Call the necessary subroutine to configure the link. */
1975         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1976             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1977         if (ret_val < 0) {
1978                 return ret_val;
1979         }
1980
1981         /* Initialize the flow control address, type, and PAUSE timer
1982          * registers to their default values.  This is done even if flow
1983          * control is disabled, because it does not hurt anything to
1984          * initialize these registers.
1985          */
1986         DEBUGOUT("Initializing the Flow Control address, type"
1987                         "and timer regs\n");
1988
1989         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1990         if (hw->mac_type != e1000_ich8lan) {
1991                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1992                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1993                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1994         }
1995
1996         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1997
1998         /* Set the flow control receive threshold registers.  Normally,
1999          * these registers will be set to a default threshold that may be
2000          * adjusted later by the driver's runtime code.  However, if the
2001          * ability to transmit pause frames in not enabled, then these
2002          * registers will be set to 0.
2003          */
2004         if (!(hw->fc & e1000_fc_tx_pause)) {
2005                 E1000_WRITE_REG(hw, FCRTL, 0);
2006                 E1000_WRITE_REG(hw, FCRTH, 0);
2007         } else {
2008                 /* We need to set up the Receive Threshold high and low water marks
2009                  * as well as (optionally) enabling the transmission of XON frames.
2010                  */
2011                 if (hw->fc_send_xon) {
2012                         E1000_WRITE_REG(hw, FCRTL,
2013                                         (hw->fc_low_water | E1000_FCRTL_XONE));
2014                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2015                 } else {
2016                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2017                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2018                 }
2019         }
2020         return ret_val;
2021 }
2022
2023 /******************************************************************************
2024  * Sets up link for a fiber based adapter
2025  *
2026  * hw - Struct containing variables accessed by shared code
2027  *
2028  * Manipulates Physical Coding Sublayer functions in order to configure
2029  * link. Assumes the hardware has been previously reset and the transmitter
2030  * and receiver are not enabled.
2031  *****************************************************************************/
2032 static int
2033 e1000_setup_fiber_link(struct eth_device *nic)
2034 {
2035         struct e1000_hw *hw = nic->priv;
2036         uint32_t ctrl;
2037         uint32_t status;
2038         uint32_t txcw = 0;
2039         uint32_t i;
2040         uint32_t signal;
2041         int32_t ret_val;
2042
2043         DEBUGFUNC();
2044         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2045          * set when the optics detect a signal. On older adapters, it will be
2046          * cleared when there is a signal
2047          */
2048         ctrl = E1000_READ_REG(hw, CTRL);
2049         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2050                 signal = E1000_CTRL_SWDPIN1;
2051         else
2052                 signal = 0;
2053
2054         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
2055                ctrl);
2056         /* Take the link out of reset */
2057         ctrl &= ~(E1000_CTRL_LRST);
2058
2059         e1000_config_collision_dist(hw);
2060
2061         /* Check for a software override of the flow control settings, and setup
2062          * the device accordingly.  If auto-negotiation is enabled, then software
2063          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2064          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2065          * auto-negotiation is disabled, then software will have to manually
2066          * configure the two flow control enable bits in the CTRL register.
2067          *
2068          * The possible values of the "fc" parameter are:
2069          *      0:  Flow control is completely disabled
2070          *      1:  Rx flow control is enabled (we can receive pause frames, but
2071          *          not send pause frames).
2072          *      2:  Tx flow control is enabled (we can send pause frames but we do
2073          *          not support receiving pause frames).
2074          *      3:  Both Rx and TX flow control (symmetric) are enabled.
2075          */
2076         switch (hw->fc) {
2077         case e1000_fc_none:
2078                 /* Flow control is completely disabled by a software over-ride. */
2079                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2080                 break;
2081         case e1000_fc_rx_pause:
2082                 /* RX Flow control is enabled and TX Flow control is disabled by a
2083                  * software over-ride. Since there really isn't a way to advertise
2084                  * that we are capable of RX Pause ONLY, we will advertise that we
2085                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2086                  *  disable the adapter's ability to send PAUSE frames.
2087                  */
2088                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2089                 break;
2090         case e1000_fc_tx_pause:
2091                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2092                  * software over-ride.
2093                  */
2094                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2095                 break;
2096         case e1000_fc_full:
2097                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2098                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2099                 break;
2100         default:
2101                 DEBUGOUT("Flow control param set incorrectly\n");
2102                 return -E1000_ERR_CONFIG;
2103                 break;
2104         }
2105
2106         /* Since auto-negotiation is enabled, take the link out of reset (the link
2107          * will be in reset, because we previously reset the chip). This will
2108          * restart auto-negotiation.  If auto-neogtiation is successful then the
2109          * link-up status bit will be set and the flow control enable bits (RFCE
2110          * and TFCE) will be set according to their negotiated value.
2111          */
2112         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2113
2114         E1000_WRITE_REG(hw, TXCW, txcw);
2115         E1000_WRITE_REG(hw, CTRL, ctrl);
2116         E1000_WRITE_FLUSH(hw);
2117
2118         hw->txcw = txcw;
2119         mdelay(1);
2120
2121         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2122          * indication in the Device Status Register.  Time-out if a link isn't
2123          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2124          * less than 500 milliseconds even if the other end is doing it in SW).
2125          */
2126         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2127                 DEBUGOUT("Looking for Link\n");
2128                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2129                         mdelay(10);
2130                         status = E1000_READ_REG(hw, STATUS);
2131                         if (status & E1000_STATUS_LU)
2132                                 break;
2133                 }
2134                 if (i == (LINK_UP_TIMEOUT / 10)) {
2135                         /* AutoNeg failed to achieve a link, so we'll call
2136                          * e1000_check_for_link. This routine will force the link up if we
2137                          * detect a signal. This will allow us to communicate with
2138                          * non-autonegotiating link partners.
2139                          */
2140                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2141                         hw->autoneg_failed = 1;
2142                         ret_val = e1000_check_for_link(nic);
2143                         if (ret_val < 0) {
2144                                 DEBUGOUT("Error while checking for link\n");
2145                                 return ret_val;
2146                         }
2147                         hw->autoneg_failed = 0;
2148                 } else {
2149                         hw->autoneg_failed = 0;
2150                         DEBUGOUT("Valid Link Found\n");
2151                 }
2152         } else {
2153                 DEBUGOUT("No Signal Detected\n");
2154                 return -E1000_ERR_NOLINK;
2155         }
2156         return 0;
2157 }
2158
2159 /******************************************************************************
2160 * Make sure we have a valid PHY and change PHY mode before link setup.
2161 *
2162 * hw - Struct containing variables accessed by shared code
2163 ******************************************************************************/
2164 static int32_t
2165 e1000_copper_link_preconfig(struct e1000_hw *hw)
2166 {
2167         uint32_t ctrl;
2168         int32_t ret_val;
2169         uint16_t phy_data;
2170
2171         DEBUGFUNC();
2172
2173         ctrl = E1000_READ_REG(hw, CTRL);
2174         /* With 82543, we need to force speed and duplex on the MAC equal to what
2175          * the PHY speed and duplex configuration is. In addition, we need to
2176          * perform a hardware reset on the PHY to take it out of reset.
2177          */
2178         if (hw->mac_type > e1000_82543) {
2179                 ctrl |= E1000_CTRL_SLU;
2180                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2181                 E1000_WRITE_REG(hw, CTRL, ctrl);
2182         } else {
2183                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2184                                 | E1000_CTRL_SLU);
2185                 E1000_WRITE_REG(hw, CTRL, ctrl);
2186                 ret_val = e1000_phy_hw_reset(hw);
2187                 if (ret_val)
2188                         return ret_val;
2189         }
2190
2191         /* Make sure we have a valid PHY */
2192         ret_val = e1000_detect_gig_phy(hw);
2193         if (ret_val) {
2194                 DEBUGOUT("Error, did not detect valid phy.\n");
2195                 return ret_val;
2196         }
2197         DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2198
2199         /* Set PHY to class A mode (if necessary) */
2200         ret_val = e1000_set_phy_mode(hw);
2201         if (ret_val)
2202                 return ret_val;
2203         if ((hw->mac_type == e1000_82545_rev_3) ||
2204                 (hw->mac_type == e1000_82546_rev_3)) {
2205                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2206                                 &phy_data);
2207                 phy_data |= 0x00000008;
2208                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2209                                 phy_data);
2210         }
2211
2212         if (hw->mac_type <= e1000_82543 ||
2213                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2214                 hw->mac_type == e1000_82541_rev_2
2215                 || hw->mac_type == e1000_82547_rev_2)
2216                         hw->phy_reset_disable = false;
2217
2218         return E1000_SUCCESS;
2219 }
2220
2221 /*****************************************************************************
2222  *
2223  * This function sets the lplu state according to the active flag.  When
2224  * activating lplu this function also disables smart speed and vise versa.
2225  * lplu will not be activated unless the device autonegotiation advertisment
2226  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2227  * hw: Struct containing variables accessed by shared code
2228  * active - true to enable lplu false to disable lplu.
2229  *
2230  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2231  *            E1000_SUCCESS at any other case.
2232  *
2233  ****************************************************************************/
2234
2235 static int32_t
2236 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2237 {
2238         uint32_t phy_ctrl = 0;
2239         int32_t ret_val;
2240         uint16_t phy_data;
2241         DEBUGFUNC();
2242
2243         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2244             && hw->phy_type != e1000_phy_igp_3)
2245                 return E1000_SUCCESS;
2246
2247         /* During driver activity LPLU should not be used or it will attain link
2248          * from the lowest speeds starting from 10Mbps. The capability is used
2249          * for Dx transitions and states */
2250         if (hw->mac_type == e1000_82541_rev_2
2251                         || hw->mac_type == e1000_82547_rev_2) {
2252                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2253                                 &phy_data);
2254                 if (ret_val)
2255                         return ret_val;
2256         } else if (hw->mac_type == e1000_ich8lan) {
2257                 /* MAC writes into PHY register based on the state transition
2258                  * and start auto-negotiation. SW driver can overwrite the
2259                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2260                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2261         } else {
2262                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2263                                 &phy_data);
2264                 if (ret_val)
2265                         return ret_val;
2266         }
2267
2268         if (!active) {
2269                 if (hw->mac_type == e1000_82541_rev_2 ||
2270                         hw->mac_type == e1000_82547_rev_2) {
2271                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2272                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2273                                         phy_data);
2274                         if (ret_val)
2275                                 return ret_val;
2276                 } else {
2277                         if (hw->mac_type == e1000_ich8lan) {
2278                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2279                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2280                         } else {
2281                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2282                                 ret_val = e1000_write_phy_reg(hw,
2283                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2284                                 if (ret_val)
2285                                         return ret_val;
2286                         }
2287                 }
2288
2289         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2290          * Dx states where the power conservation is most important.  During
2291          * driver activity we should enable SmartSpeed, so performance is
2292          * maintained. */
2293                 if (hw->smart_speed == e1000_smart_speed_on) {
2294                         ret_val = e1000_read_phy_reg(hw,
2295                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2296                         if (ret_val)
2297                                 return ret_val;
2298
2299                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2300                         ret_val = e1000_write_phy_reg(hw,
2301                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2302                         if (ret_val)
2303                                 return ret_val;
2304                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2305                         ret_val = e1000_read_phy_reg(hw,
2306                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2307                         if (ret_val)
2308                                 return ret_val;
2309
2310                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2311                         ret_val = e1000_write_phy_reg(hw,
2312                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2313                         if (ret_val)
2314                                 return ret_val;
2315                 }
2316
2317         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2318                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2319                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2320
2321                 if (hw->mac_type == e1000_82541_rev_2 ||
2322                     hw->mac_type == e1000_82547_rev_2) {
2323                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2324                         ret_val = e1000_write_phy_reg(hw,
2325                                         IGP01E1000_GMII_FIFO, phy_data);
2326                         if (ret_val)
2327                                 return ret_val;
2328                 } else {
2329                         if (hw->mac_type == e1000_ich8lan) {
2330                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2331                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2332                         } else {
2333                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2334                                 ret_val = e1000_write_phy_reg(hw,
2335                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2336                                 if (ret_val)
2337                                         return ret_val;
2338                         }
2339                 }
2340
2341                 /* When LPLU is enabled we should disable SmartSpeed */
2342                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2343                                 &phy_data);
2344                 if (ret_val)
2345                         return ret_val;
2346
2347                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2348                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2349                                 phy_data);
2350                 if (ret_val)
2351                         return ret_val;
2352         }
2353         return E1000_SUCCESS;
2354 }
2355
2356 /*****************************************************************************
2357  *
2358  * This function sets the lplu d0 state according to the active flag.  When
2359  * activating lplu this function also disables smart speed and vise versa.
2360  * lplu will not be activated unless the device autonegotiation advertisment
2361  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2362  * hw: Struct containing variables accessed by shared code
2363  * active - true to enable lplu false to disable lplu.
2364  *
2365  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2366  *            E1000_SUCCESS at any other case.
2367  *
2368  ****************************************************************************/
2369
2370 static int32_t
2371 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2372 {
2373         uint32_t phy_ctrl = 0;
2374         int32_t ret_val;
2375         uint16_t phy_data;
2376         DEBUGFUNC();
2377
2378         if (hw->mac_type <= e1000_82547_rev_2)
2379                 return E1000_SUCCESS;
2380
2381         if (hw->mac_type == e1000_ich8lan) {
2382                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2383         } else if (hw->mac_type == e1000_igb) {
2384                 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2385         } else {
2386                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2387                                 &phy_data);
2388                 if (ret_val)
2389                         return ret_val;
2390         }
2391
2392         if (!active) {
2393                 if (hw->mac_type == e1000_ich8lan) {
2394                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2395                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2396                 } else if (hw->mac_type == e1000_igb) {
2397                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2398                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2399                 } else {
2400                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2401                         ret_val = e1000_write_phy_reg(hw,
2402                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2403                         if (ret_val)
2404                                 return ret_val;
2405                 }
2406
2407                 if (hw->mac_type == e1000_igb)
2408                         return E1000_SUCCESS;
2409
2410         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2411          * Dx states where the power conservation is most important.  During
2412          * driver activity we should enable SmartSpeed, so performance is
2413          * maintained. */
2414                 if (hw->smart_speed == e1000_smart_speed_on) {
2415                         ret_val = e1000_read_phy_reg(hw,
2416                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2417                         if (ret_val)
2418                                 return ret_val;
2419
2420                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2421                         ret_val = e1000_write_phy_reg(hw,
2422                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2423                         if (ret_val)
2424                                 return ret_val;
2425                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2426                         ret_val = e1000_read_phy_reg(hw,
2427                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2428                         if (ret_val)
2429                                 return ret_val;
2430
2431                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2432                         ret_val = e1000_write_phy_reg(hw,
2433                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2434                         if (ret_val)
2435                                 return ret_val;
2436                 }
2437
2438
2439         } else {
2440
2441                 if (hw->mac_type == e1000_ich8lan) {
2442                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2443                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2444                 } else if (hw->mac_type == e1000_igb) {
2445                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2446                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2447                 } else {
2448                         phy_data |= IGP02E1000_PM_D0_LPLU;
2449                         ret_val = e1000_write_phy_reg(hw,
2450                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2451                         if (ret_val)
2452                                 return ret_val;
2453                 }
2454
2455                 if (hw->mac_type == e1000_igb)
2456                         return E1000_SUCCESS;
2457
2458                 /* When LPLU is enabled we should disable SmartSpeed */
2459                 ret_val = e1000_read_phy_reg(hw,
2460                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2461                 if (ret_val)
2462                         return ret_val;
2463
2464                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2465                 ret_val = e1000_write_phy_reg(hw,
2466                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2467                 if (ret_val)
2468                         return ret_val;
2469
2470         }
2471         return E1000_SUCCESS;
2472 }
2473
2474 /********************************************************************
2475 * Copper link setup for e1000_phy_igp series.
2476 *
2477 * hw - Struct containing variables accessed by shared code
2478 *********************************************************************/
2479 static int32_t
2480 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2481 {
2482         uint32_t led_ctrl;
2483         int32_t ret_val;
2484         uint16_t phy_data;
2485
2486         DEBUGFUNC();
2487
2488         if (hw->phy_reset_disable)
2489                 return E1000_SUCCESS;
2490
2491         ret_val = e1000_phy_reset(hw);
2492         if (ret_val) {
2493                 DEBUGOUT("Error Resetting the PHY\n");
2494                 return ret_val;
2495         }
2496
2497         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2498         mdelay(15);
2499         if (hw->mac_type != e1000_ich8lan) {
2500                 /* Configure activity LED after PHY reset */
2501                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2502                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2503                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2504                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2505         }
2506
2507         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2508         if (hw->phy_type == e1000_phy_igp) {
2509                 /* disable lplu d3 during driver init */
2510                 ret_val = e1000_set_d3_lplu_state(hw, false);
2511                 if (ret_val) {
2512                         DEBUGOUT("Error Disabling LPLU D3\n");
2513                         return ret_val;
2514                 }
2515         }
2516
2517         /* disable lplu d0 during driver init */
2518         ret_val = e1000_set_d0_lplu_state(hw, false);
2519         if (ret_val) {
2520                 DEBUGOUT("Error Disabling LPLU D0\n");
2521                 return ret_val;
2522         }
2523         /* Configure mdi-mdix settings */
2524         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2525         if (ret_val)
2526                 return ret_val;
2527
2528         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2529                 hw->dsp_config_state = e1000_dsp_config_disabled;
2530                 /* Force MDI for earlier revs of the IGP PHY */
2531                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2532                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2533                 hw->mdix = 1;
2534
2535         } else {
2536                 hw->dsp_config_state = e1000_dsp_config_enabled;
2537                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2538
2539                 switch (hw->mdix) {
2540                 case 1:
2541                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2542                         break;
2543                 case 2:
2544                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2545                         break;
2546                 case 0:
2547                 default:
2548                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2549                         break;
2550                 }
2551         }
2552         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2553         if (ret_val)
2554                 return ret_val;
2555
2556         /* set auto-master slave resolution settings */
2557         if (hw->autoneg) {
2558                 e1000_ms_type phy_ms_setting = hw->master_slave;
2559
2560                 if (hw->ffe_config_state == e1000_ffe_config_active)
2561                         hw->ffe_config_state = e1000_ffe_config_enabled;
2562
2563                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2564                         hw->dsp_config_state = e1000_dsp_config_enabled;
2565
2566                 /* when autonegotiation advertisment is only 1000Mbps then we
2567                   * should disable SmartSpeed and enable Auto MasterSlave
2568                   * resolution as hardware default. */
2569                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2570                         /* Disable SmartSpeed */
2571                         ret_val = e1000_read_phy_reg(hw,
2572                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2573                         if (ret_val)
2574                                 return ret_val;
2575                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2576                         ret_val = e1000_write_phy_reg(hw,
2577                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2578                         if (ret_val)
2579                                 return ret_val;
2580                         /* Set auto Master/Slave resolution process */
2581                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2582                                         &phy_data);
2583                         if (ret_val)
2584                                 return ret_val;
2585                         phy_data &= ~CR_1000T_MS_ENABLE;
2586                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2587                                         phy_data);
2588                         if (ret_val)
2589                                 return ret_val;
2590                 }
2591
2592                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2593                 if (ret_val)
2594                         return ret_val;
2595
2596                 /* load defaults for future use */
2597                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2598                                 ((phy_data & CR_1000T_MS_VALUE) ?
2599                                 e1000_ms_force_master :
2600                                 e1000_ms_force_slave) :
2601                                 e1000_ms_auto;
2602
2603                 switch (phy_ms_setting) {
2604                 case e1000_ms_force_master:
2605                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2606                         break;
2607                 case e1000_ms_force_slave:
2608                         phy_data |= CR_1000T_MS_ENABLE;
2609                         phy_data &= ~(CR_1000T_MS_VALUE);
2610                         break;
2611                 case e1000_ms_auto:
2612                         phy_data &= ~CR_1000T_MS_ENABLE;
2613                 default:
2614                         break;
2615                 }
2616                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2617                 if (ret_val)
2618                         return ret_val;
2619         }
2620
2621         return E1000_SUCCESS;
2622 }
2623
2624 /*****************************************************************************
2625  * This function checks the mode of the firmware.
2626  *
2627  * returns  - true when the mode is IAMT or false.
2628  ****************************************************************************/
2629 bool
2630 e1000_check_mng_mode(struct e1000_hw *hw)
2631 {
2632         uint32_t fwsm;
2633         DEBUGFUNC();
2634
2635         fwsm = E1000_READ_REG(hw, FWSM);
2636
2637         if (hw->mac_type == e1000_ich8lan) {
2638                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2639                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2640                         return true;
2641         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2642                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2643                         return true;
2644
2645         return false;
2646 }
2647
2648 static int32_t
2649 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2650 {
2651         uint16_t swfw = E1000_SWFW_PHY0_SM;
2652         uint32_t reg_val;
2653         DEBUGFUNC();
2654
2655         if (e1000_is_second_port(hw))
2656                 swfw = E1000_SWFW_PHY1_SM;
2657
2658         if (e1000_swfw_sync_acquire(hw, swfw))
2659                 return -E1000_ERR_SWFW_SYNC;
2660
2661         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2662                         & E1000_KUMCTRLSTA_OFFSET) | data;
2663         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2664         udelay(2);
2665
2666         return E1000_SUCCESS;
2667 }
2668
2669 static int32_t
2670 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2671 {
2672         uint16_t swfw = E1000_SWFW_PHY0_SM;
2673         uint32_t reg_val;
2674         DEBUGFUNC();
2675
2676         if (e1000_is_second_port(hw))
2677                 swfw = E1000_SWFW_PHY1_SM;
2678
2679         if (e1000_swfw_sync_acquire(hw, swfw)) {
2680                 debug("%s[%i]\n", __func__, __LINE__);
2681                 return -E1000_ERR_SWFW_SYNC;
2682         }
2683
2684         /* Write register address */
2685         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2686                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2687         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2688         udelay(2);
2689
2690         /* Read the data returned */
2691         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2692         *data = (uint16_t)reg_val;
2693
2694         return E1000_SUCCESS;
2695 }
2696
2697 /********************************************************************
2698 * Copper link setup for e1000_phy_gg82563 series.
2699 *
2700 * hw - Struct containing variables accessed by shared code
2701 *********************************************************************/
2702 static int32_t
2703 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2704 {
2705         int32_t ret_val;
2706         uint16_t phy_data;
2707         uint32_t reg_data;
2708
2709         DEBUGFUNC();
2710
2711         if (!hw->phy_reset_disable) {
2712                 /* Enable CRS on TX for half-duplex operation. */
2713                 ret_val = e1000_read_phy_reg(hw,
2714                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2715                 if (ret_val)
2716                         return ret_val;
2717
2718                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2719                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2720                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2721
2722                 ret_val = e1000_write_phy_reg(hw,
2723                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2724                 if (ret_val)
2725                         return ret_val;
2726
2727                 /* Options:
2728                  *   MDI/MDI-X = 0 (default)
2729                  *   0 - Auto for all speeds
2730                  *   1 - MDI mode
2731                  *   2 - MDI-X mode
2732                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2733                  */
2734                 ret_val = e1000_read_phy_reg(hw,
2735                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2736                 if (ret_val)
2737                         return ret_val;
2738
2739                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2740
2741                 switch (hw->mdix) {
2742                 case 1:
2743                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2744                         break;
2745                 case 2:
2746                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2747                         break;
2748                 case 0:
2749                 default:
2750                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2751                         break;
2752                 }
2753
2754                 /* Options:
2755                  *   disable_polarity_correction = 0 (default)
2756                  *       Automatic Correction for Reversed Cable Polarity
2757                  *   0 - Disabled
2758                  *   1 - Enabled
2759                  */
2760                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2761                 ret_val = e1000_write_phy_reg(hw,
2762                                 GG82563_PHY_SPEC_CTRL, phy_data);
2763
2764                 if (ret_val)
2765                         return ret_val;
2766
2767                 /* SW Reset the PHY so all changes take effect */
2768                 ret_val = e1000_phy_reset(hw);
2769                 if (ret_val) {
2770                         DEBUGOUT("Error Resetting the PHY\n");
2771                         return ret_val;
2772                 }
2773         } /* phy_reset_disable */
2774
2775         if (hw->mac_type == e1000_80003es2lan) {
2776                 /* Bypass RX and TX FIFO's */
2777                 ret_val = e1000_write_kmrn_reg(hw,
2778                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2779                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2780                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2781                 if (ret_val)
2782                         return ret_val;
2783
2784                 ret_val = e1000_read_phy_reg(hw,
2785                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2786                 if (ret_val)
2787                         return ret_val;
2788
2789                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2790                 ret_val = e1000_write_phy_reg(hw,
2791                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2792
2793                 if (ret_val)
2794                         return ret_val;
2795
2796                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2797                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2798                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2799
2800                 ret_val = e1000_read_phy_reg(hw,
2801                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2802                 if (ret_val)
2803                         return ret_val;
2804
2805         /* Do not init these registers when the HW is in IAMT mode, since the
2806          * firmware will have already initialized them.  We only initialize
2807          * them if the HW is not in IAMT mode.
2808          */
2809                 if (e1000_check_mng_mode(hw) == false) {
2810                         /* Enable Electrical Idle on the PHY */
2811                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2812                         ret_val = e1000_write_phy_reg(hw,
2813                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2814                         if (ret_val)
2815                                 return ret_val;
2816
2817                         ret_val = e1000_read_phy_reg(hw,
2818                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2819                         if (ret_val)
2820                                 return ret_val;
2821
2822                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2823                         ret_val = e1000_write_phy_reg(hw,
2824                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2825
2826                         if (ret_val)
2827                                 return ret_val;
2828                 }
2829
2830                 /* Workaround: Disable padding in Kumeran interface in the MAC
2831                  * and in the PHY to avoid CRC errors.
2832                  */
2833                 ret_val = e1000_read_phy_reg(hw,
2834                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2835                 if (ret_val)
2836                         return ret_val;
2837                 phy_data |= GG82563_ICR_DIS_PADDING;
2838                 ret_val = e1000_write_phy_reg(hw,
2839                                 GG82563_PHY_INBAND_CTRL, phy_data);
2840                 if (ret_val)
2841                         return ret_val;
2842         }
2843         return E1000_SUCCESS;
2844 }
2845
2846 /********************************************************************
2847 * Copper link setup for e1000_phy_m88 series.
2848 *
2849 * hw - Struct containing variables accessed by shared code
2850 *********************************************************************/
2851 static int32_t
2852 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2853 {
2854         int32_t ret_val;
2855         uint16_t phy_data;
2856
2857         DEBUGFUNC();
2858
2859         if (hw->phy_reset_disable)
2860                 return E1000_SUCCESS;
2861
2862         /* Enable CRS on TX. This must be set for half-duplex operation. */
2863         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2864         if (ret_val)
2865                 return ret_val;
2866
2867         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2868
2869         /* Options:
2870          *   MDI/MDI-X = 0 (default)
2871          *   0 - Auto for all speeds
2872          *   1 - MDI mode
2873          *   2 - MDI-X mode
2874          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2875          */
2876         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2877
2878         switch (hw->mdix) {
2879         case 1:
2880                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2881                 break;
2882         case 2:
2883                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2884                 break;
2885         case 3:
2886                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2887                 break;
2888         case 0:
2889         default:
2890                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2891                 break;
2892         }
2893
2894         /* Options:
2895          *   disable_polarity_correction = 0 (default)
2896          *       Automatic Correction for Reversed Cable Polarity
2897          *   0 - Disabled
2898          *   1 - Enabled
2899          */
2900         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2901         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2902         if (ret_val)
2903                 return ret_val;
2904
2905         if (hw->phy_revision < M88E1011_I_REV_4) {
2906                 /* Force TX_CLK in the Extended PHY Specific Control Register
2907                  * to 25MHz clock.
2908                  */
2909                 ret_val = e1000_read_phy_reg(hw,
2910                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2911                 if (ret_val)
2912                         return ret_val;
2913
2914                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2915
2916                 if ((hw->phy_revision == E1000_REVISION_2) &&
2917                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2918                         /* Vidalia Phy, set the downshift counter to 5x */
2919                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2920                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2921                         ret_val = e1000_write_phy_reg(hw,
2922                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2923                         if (ret_val)
2924                                 return ret_val;
2925                 } else {
2926                         /* Configure Master and Slave downshift values */
2927                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2928                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2929                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2930                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2931                         ret_val = e1000_write_phy_reg(hw,
2932                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2933                         if (ret_val)
2934                                 return ret_val;
2935                 }
2936         }
2937
2938         /* SW Reset the PHY so all changes take effect */
2939         ret_val = e1000_phy_reset(hw);
2940         if (ret_val) {
2941                 DEBUGOUT("Error Resetting the PHY\n");
2942                 return ret_val;
2943         }
2944
2945         return E1000_SUCCESS;
2946 }
2947
2948 /********************************************************************
2949 * Setup auto-negotiation and flow control advertisements,
2950 * and then perform auto-negotiation.
2951 *
2952 * hw - Struct containing variables accessed by shared code
2953 *********************************************************************/
2954 static int32_t
2955 e1000_copper_link_autoneg(struct e1000_hw *hw)
2956 {
2957         int32_t ret_val;
2958         uint16_t phy_data;
2959
2960         DEBUGFUNC();
2961
2962         /* Perform some bounds checking on the hw->autoneg_advertised
2963          * parameter.  If this variable is zero, then set it to the default.
2964          */
2965         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2966
2967         /* If autoneg_advertised is zero, we assume it was not defaulted
2968          * by the calling code so we set to advertise full capability.
2969          */
2970         if (hw->autoneg_advertised == 0)
2971                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2972
2973         /* IFE phy only supports 10/100 */
2974         if (hw->phy_type == e1000_phy_ife)
2975                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2976
2977         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2978         ret_val = e1000_phy_setup_autoneg(hw);
2979         if (ret_val) {
2980                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2981                 return ret_val;
2982         }
2983         DEBUGOUT("Restarting Auto-Neg\n");
2984
2985         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2986          * the Auto Neg Restart bit in the PHY control register.
2987          */
2988         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2989         if (ret_val)
2990                 return ret_val;
2991
2992         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2993         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2994         if (ret_val)
2995                 return ret_val;
2996
2997         /* Does the user want to wait for Auto-Neg to complete here, or
2998          * check at a later time (for example, callback routine).
2999          */
3000         /* If we do not wait for autonegtation to complete I
3001          * do not see a valid link status.
3002          * wait_autoneg_complete = 1 .
3003          */
3004         if (hw->wait_autoneg_complete) {
3005                 ret_val = e1000_wait_autoneg(hw);
3006                 if (ret_val) {
3007                         DEBUGOUT("Error while waiting for autoneg"
3008                                         "to complete\n");
3009                         return ret_val;
3010                 }
3011         }
3012
3013         hw->get_link_status = true;
3014
3015         return E1000_SUCCESS;
3016 }
3017
3018 /******************************************************************************
3019 * Config the MAC and the PHY after link is up.
3020 *   1) Set up the MAC to the current PHY speed/duplex
3021 *      if we are on 82543.  If we
3022 *      are on newer silicon, we only need to configure
3023 *      collision distance in the Transmit Control Register.
3024 *   2) Set up flow control on the MAC to that established with
3025 *      the link partner.
3026 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3027 *
3028 * hw - Struct containing variables accessed by shared code
3029 ******************************************************************************/
3030 static int32_t
3031 e1000_copper_link_postconfig(struct e1000_hw *hw)
3032 {
3033         int32_t ret_val;
3034         DEBUGFUNC();
3035
3036         if (hw->mac_type >= e1000_82544) {
3037                 e1000_config_collision_dist(hw);
3038         } else {
3039                 ret_val = e1000_config_mac_to_phy(hw);
3040                 if (ret_val) {
3041                         DEBUGOUT("Error configuring MAC to PHY settings\n");
3042                         return ret_val;
3043                 }
3044         }
3045         ret_val = e1000_config_fc_after_link_up(hw);
3046         if (ret_val) {
3047                 DEBUGOUT("Error Configuring Flow Control\n");
3048                 return ret_val;
3049         }
3050         return E1000_SUCCESS;
3051 }
3052
3053 /******************************************************************************
3054 * Detects which PHY is present and setup the speed and duplex
3055 *
3056 * hw - Struct containing variables accessed by shared code
3057 ******************************************************************************/
3058 static int
3059 e1000_setup_copper_link(struct eth_device *nic)
3060 {
3061         struct e1000_hw *hw = nic->priv;
3062         int32_t ret_val;
3063         uint16_t i;
3064         uint16_t phy_data;
3065         uint16_t reg_data;
3066
3067         DEBUGFUNC();
3068
3069         switch (hw->mac_type) {
3070         case e1000_80003es2lan:
3071         case e1000_ich8lan:
3072                 /* Set the mac to wait the maximum time between each
3073                  * iteration and increase the max iterations when
3074                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3075                 ret_val = e1000_write_kmrn_reg(hw,
3076                                 GG82563_REG(0x34, 4), 0xFFFF);
3077                 if (ret_val)
3078                         return ret_val;
3079                 ret_val = e1000_read_kmrn_reg(hw,
3080                                 GG82563_REG(0x34, 9), &reg_data);
3081                 if (ret_val)
3082                         return ret_val;
3083                 reg_data |= 0x3F;
3084                 ret_val = e1000_write_kmrn_reg(hw,
3085                                 GG82563_REG(0x34, 9), reg_data);
3086                 if (ret_val)
3087                         return ret_val;
3088         default:
3089                 break;
3090         }
3091
3092         /* Check if it is a valid PHY and set PHY mode if necessary. */
3093         ret_val = e1000_copper_link_preconfig(hw);
3094         if (ret_val)
3095                 return ret_val;
3096         switch (hw->mac_type) {
3097         case e1000_80003es2lan:
3098                 /* Kumeran registers are written-only */
3099                 reg_data =
3100                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3101                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3102                 ret_val = e1000_write_kmrn_reg(hw,
3103                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3104                 if (ret_val)
3105                         return ret_val;
3106                 break;
3107         default:
3108                 break;
3109         }
3110
3111         if (hw->phy_type == e1000_phy_igp ||
3112                 hw->phy_type == e1000_phy_igp_3 ||
3113                 hw->phy_type == e1000_phy_igp_2) {
3114                 ret_val = e1000_copper_link_igp_setup(hw);
3115                 if (ret_val)
3116                         return ret_val;
3117         } else if (hw->phy_type == e1000_phy_m88 ||
3118                 hw->phy_type == e1000_phy_igb) {
3119                 ret_val = e1000_copper_link_mgp_setup(hw);
3120                 if (ret_val)
3121                         return ret_val;
3122         } else if (hw->phy_type == e1000_phy_gg82563) {
3123                 ret_val = e1000_copper_link_ggp_setup(hw);
3124                 if (ret_val)
3125                         return ret_val;
3126         }
3127
3128         /* always auto */
3129         /* Setup autoneg and flow control advertisement
3130           * and perform autonegotiation */
3131         ret_val = e1000_copper_link_autoneg(hw);
3132         if (ret_val)
3133                 return ret_val;
3134
3135         /* Check link status. Wait up to 100 microseconds for link to become
3136          * valid.
3137          */
3138         for (i = 0; i < 10; i++) {
3139                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3140                 if (ret_val)
3141                         return ret_val;
3142                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3143                 if (ret_val)
3144                         return ret_val;
3145
3146                 if (phy_data & MII_SR_LINK_STATUS) {
3147                         /* Config the MAC and PHY after link is up */
3148                         ret_val = e1000_copper_link_postconfig(hw);
3149                         if (ret_val)
3150                                 return ret_val;
3151
3152                         DEBUGOUT("Valid link established!!!\n");
3153                         return E1000_SUCCESS;
3154                 }
3155                 udelay(10);
3156         }
3157
3158         DEBUGOUT("Unable to establish link!!!\n");
3159         return E1000_SUCCESS;
3160 }
3161
3162 /******************************************************************************
3163 * Configures PHY autoneg and flow control advertisement settings
3164 *
3165 * hw - Struct containing variables accessed by shared code
3166 ******************************************************************************/
3167 int32_t
3168 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3169 {
3170         int32_t ret_val;
3171         uint16_t mii_autoneg_adv_reg;
3172         uint16_t mii_1000t_ctrl_reg;
3173
3174         DEBUGFUNC();
3175
3176         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3177         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3178         if (ret_val)
3179                 return ret_val;
3180
3181         if (hw->phy_type != e1000_phy_ife) {
3182                 /* Read the MII 1000Base-T Control Register (Address 9). */
3183                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3184                                 &mii_1000t_ctrl_reg);
3185                 if (ret_val)
3186                         return ret_val;
3187         } else
3188                 mii_1000t_ctrl_reg = 0;
3189
3190         /* Need to parse both autoneg_advertised and fc and set up
3191          * the appropriate PHY registers.  First we will parse for
3192          * autoneg_advertised software override.  Since we can advertise
3193          * a plethora of combinations, we need to check each bit
3194          * individually.
3195          */
3196
3197         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3198          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3199          * the  1000Base-T Control Register (Address 9).
3200          */
3201         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3202         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3203
3204         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3205
3206         /* Do we want to advertise 10 Mb Half Duplex? */
3207         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3208                 DEBUGOUT("Advertise 10mb Half duplex\n");
3209                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3210         }
3211
3212         /* Do we want to advertise 10 Mb Full Duplex? */
3213         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3214                 DEBUGOUT("Advertise 10mb Full duplex\n");
3215                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3216         }
3217
3218         /* Do we want to advertise 100 Mb Half Duplex? */
3219         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3220                 DEBUGOUT("Advertise 100mb Half duplex\n");
3221                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3222         }
3223
3224         /* Do we want to advertise 100 Mb Full Duplex? */
3225         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3226                 DEBUGOUT("Advertise 100mb Full duplex\n");
3227                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3228         }
3229
3230         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3231         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3232                 DEBUGOUT
3233                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3234         }
3235
3236         /* Do we want to advertise 1000 Mb Full Duplex? */
3237         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3238                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3239                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3240         }
3241
3242         /* Check for a software override of the flow control settings, and
3243          * setup the PHY advertisement registers accordingly.  If
3244          * auto-negotiation is enabled, then software will have to set the
3245          * "PAUSE" bits to the correct value in the Auto-Negotiation
3246          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3247          *
3248          * The possible values of the "fc" parameter are:
3249          *      0:  Flow control is completely disabled
3250          *      1:  Rx flow control is enabled (we can receive pause frames
3251          *          but not send pause frames).
3252          *      2:  Tx flow control is enabled (we can send pause frames
3253          *          but we do not support receiving pause frames).
3254          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3255          *  other:  No software override.  The flow control configuration
3256          *          in the EEPROM is used.
3257          */
3258         switch (hw->fc) {
3259         case e1000_fc_none:     /* 0 */
3260                 /* Flow control (RX & TX) is completely disabled by a
3261                  * software over-ride.
3262                  */
3263                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3264                 break;
3265         case e1000_fc_rx_pause: /* 1 */
3266                 /* RX Flow control is enabled, and TX Flow control is
3267                  * disabled, by a software over-ride.
3268                  */
3269                 /* Since there really isn't a way to advertise that we are
3270                  * capable of RX Pause ONLY, we will advertise that we
3271                  * support both symmetric and asymmetric RX PAUSE.  Later
3272                  * (in e1000_config_fc_after_link_up) we will disable the
3273                  *hw's ability to send PAUSE frames.
3274                  */
3275                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3276                 break;
3277         case e1000_fc_tx_pause: /* 2 */
3278                 /* TX Flow control is enabled, and RX Flow control is
3279                  * disabled, by a software over-ride.
3280                  */
3281                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3282                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3283                 break;
3284         case e1000_fc_full:     /* 3 */
3285                 /* Flow control (both RX and TX) is enabled by a software
3286                  * over-ride.
3287                  */
3288                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3289                 break;
3290         default:
3291                 DEBUGOUT("Flow control param set incorrectly\n");
3292                 return -E1000_ERR_CONFIG;
3293         }
3294
3295         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3296         if (ret_val)
3297                 return ret_val;
3298
3299         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3300
3301         if (hw->phy_type != e1000_phy_ife) {
3302                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3303                                 mii_1000t_ctrl_reg);
3304                 if (ret_val)
3305                         return ret_val;
3306         }
3307
3308         return E1000_SUCCESS;
3309 }
3310
3311 /******************************************************************************
3312 * Sets the collision distance in the Transmit Control register
3313 *
3314 * hw - Struct containing variables accessed by shared code
3315 *
3316 * Link should have been established previously. Reads the speed and duplex
3317 * information from the Device Status register.
3318 ******************************************************************************/
3319 static void
3320 e1000_config_collision_dist(struct e1000_hw *hw)
3321 {
3322         uint32_t tctl, coll_dist;
3323
3324         DEBUGFUNC();
3325
3326         if (hw->mac_type < e1000_82543)
3327                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3328         else
3329                 coll_dist = E1000_COLLISION_DISTANCE;
3330
3331         tctl = E1000_READ_REG(hw, TCTL);
3332
3333         tctl &= ~E1000_TCTL_COLD;
3334         tctl |= coll_dist << E1000_COLD_SHIFT;
3335
3336         E1000_WRITE_REG(hw, TCTL, tctl);
3337         E1000_WRITE_FLUSH(hw);
3338 }
3339
3340 /******************************************************************************
3341 * Sets MAC speed and duplex settings to reflect the those in the PHY
3342 *
3343 * hw - Struct containing variables accessed by shared code
3344 * mii_reg - data to write to the MII control register
3345 *
3346 * The contents of the PHY register containing the needed information need to
3347 * be passed in.
3348 ******************************************************************************/
3349 static int
3350 e1000_config_mac_to_phy(struct e1000_hw *hw)
3351 {
3352         uint32_t ctrl;
3353         uint16_t phy_data;
3354
3355         DEBUGFUNC();
3356
3357         /* Read the Device Control Register and set the bits to Force Speed
3358          * and Duplex.
3359          */
3360         ctrl = E1000_READ_REG(hw, CTRL);
3361         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3362         ctrl &= ~(E1000_CTRL_ILOS);
3363         ctrl |= (E1000_CTRL_SPD_SEL);
3364
3365         /* Set up duplex in the Device Control and Transmit Control
3366          * registers depending on negotiated values.
3367          */
3368         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3369                 DEBUGOUT("PHY Read Error\n");
3370                 return -E1000_ERR_PHY;
3371         }
3372         if (phy_data & M88E1000_PSSR_DPLX)
3373                 ctrl |= E1000_CTRL_FD;
3374         else
3375                 ctrl &= ~E1000_CTRL_FD;
3376
3377         e1000_config_collision_dist(hw);
3378
3379         /* Set up speed in the Device Control register depending on
3380          * negotiated values.
3381          */
3382         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3383                 ctrl |= E1000_CTRL_SPD_1000;
3384         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3385                 ctrl |= E1000_CTRL_SPD_100;
3386         /* Write the configured values back to the Device Control Reg. */
3387         E1000_WRITE_REG(hw, CTRL, ctrl);
3388         return 0;
3389 }
3390
3391 /******************************************************************************
3392  * Forces the MAC's flow control settings.
3393  *
3394  * hw - Struct containing variables accessed by shared code
3395  *
3396  * Sets the TFCE and RFCE bits in the device control register to reflect
3397  * the adapter settings. TFCE and RFCE need to be explicitly set by
3398  * software when a Copper PHY is used because autonegotiation is managed
3399  * by the PHY rather than the MAC. Software must also configure these
3400  * bits when link is forced on a fiber connection.
3401  *****************************************************************************/
3402 static int
3403 e1000_force_mac_fc(struct e1000_hw *hw)
3404 {
3405         uint32_t ctrl;
3406
3407         DEBUGFUNC();
3408
3409         /* Get the current configuration of the Device Control Register */
3410         ctrl = E1000_READ_REG(hw, CTRL);
3411
3412         /* Because we didn't get link via the internal auto-negotiation
3413          * mechanism (we either forced link or we got link via PHY
3414          * auto-neg), we have to manually enable/disable transmit an
3415          * receive flow control.
3416          *
3417          * The "Case" statement below enables/disable flow control
3418          * according to the "hw->fc" parameter.
3419          *
3420          * The possible values of the "fc" parameter are:
3421          *      0:  Flow control is completely disabled
3422          *      1:  Rx flow control is enabled (we can receive pause
3423          *          frames but not send pause frames).
3424          *      2:  Tx flow control is enabled (we can send pause frames
3425          *          frames but we do not receive pause frames).
3426          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3427          *  other:  No other values should be possible at this point.
3428          */
3429
3430         switch (hw->fc) {
3431         case e1000_fc_none:
3432                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3433                 break;
3434         case e1000_fc_rx_pause:
3435                 ctrl &= (~E1000_CTRL_TFCE);
3436                 ctrl |= E1000_CTRL_RFCE;
3437                 break;
3438         case e1000_fc_tx_pause:
3439                 ctrl &= (~E1000_CTRL_RFCE);
3440                 ctrl |= E1000_CTRL_TFCE;
3441                 break;
3442         case e1000_fc_full:
3443                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3444                 break;
3445         default:
3446                 DEBUGOUT("Flow control param set incorrectly\n");
3447                 return -E1000_ERR_CONFIG;
3448         }
3449
3450         /* Disable TX Flow Control for 82542 (rev 2.0) */
3451         if (hw->mac_type == e1000_82542_rev2_0)
3452                 ctrl &= (~E1000_CTRL_TFCE);
3453
3454         E1000_WRITE_REG(hw, CTRL, ctrl);
3455         return 0;
3456 }
3457
3458 /******************************************************************************
3459  * Configures flow control settings after link is established
3460  *
3461  * hw - Struct containing variables accessed by shared code
3462  *
3463  * Should be called immediately after a valid link has been established.
3464  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3465  * and autonegotiation is enabled, the MAC flow control settings will be set
3466  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3467  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3468  *****************************************************************************/
3469 static int32_t
3470 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3471 {
3472         int32_t ret_val;
3473         uint16_t mii_status_reg;
3474         uint16_t mii_nway_adv_reg;
3475         uint16_t mii_nway_lp_ability_reg;
3476         uint16_t speed;
3477         uint16_t duplex;
3478
3479         DEBUGFUNC();
3480
3481         /* Check for the case where we have fiber media and auto-neg failed
3482          * so we had to force link.  In this case, we need to force the
3483          * configuration of the MAC to match the "fc" parameter.
3484          */
3485         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3486                 || ((hw->media_type == e1000_media_type_internal_serdes)
3487                 && (hw->autoneg_failed))
3488                 || ((hw->media_type == e1000_media_type_copper)
3489                 && (!hw->autoneg))) {
3490                 ret_val = e1000_force_mac_fc(hw);
3491                 if (ret_val < 0) {
3492                         DEBUGOUT("Error forcing flow control settings\n");
3493                         return ret_val;
3494                 }
3495         }
3496
3497         /* Check for the case where we have copper media and auto-neg is
3498          * enabled.  In this case, we need to check and see if Auto-Neg
3499          * has completed, and if so, how the PHY and link partner has
3500          * flow control configured.
3501          */
3502         if (hw->media_type == e1000_media_type_copper) {
3503                 /* Read the MII Status Register and check to see if AutoNeg
3504                  * has completed.  We read this twice because this reg has
3505                  * some "sticky" (latched) bits.
3506                  */
3507                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3508                         DEBUGOUT("PHY Read Error\n");
3509                         return -E1000_ERR_PHY;
3510                 }
3511                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3512                         DEBUGOUT("PHY Read Error\n");
3513                         return -E1000_ERR_PHY;
3514                 }
3515
3516                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3517                         /* The AutoNeg process has completed, so we now need to
3518                          * read both the Auto Negotiation Advertisement Register
3519                          * (Address 4) and the Auto_Negotiation Base Page Ability
3520                          * Register (Address 5) to determine how flow control was
3521                          * negotiated.
3522                          */
3523                         if (e1000_read_phy_reg
3524                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3525                                 DEBUGOUT("PHY Read Error\n");
3526                                 return -E1000_ERR_PHY;
3527                         }
3528                         if (e1000_read_phy_reg
3529                             (hw, PHY_LP_ABILITY,
3530                              &mii_nway_lp_ability_reg) < 0) {
3531                                 DEBUGOUT("PHY Read Error\n");
3532                                 return -E1000_ERR_PHY;
3533                         }
3534
3535                         /* Two bits in the Auto Negotiation Advertisement Register
3536                          * (Address 4) and two bits in the Auto Negotiation Base
3537                          * Page Ability Register (Address 5) determine flow control
3538                          * for both the PHY and the link partner.  The following
3539                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3540                          * 1999, describes these PAUSE resolution bits and how flow
3541                          * control is determined based upon these settings.
3542                          * NOTE:  DC = Don't Care
3543                          *
3544                          *   LOCAL DEVICE  |   LINK PARTNER
3545                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3546                          *-------|---------|-------|---------|--------------------
3547                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3548                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3549                          *   0   |    1    |   1   |    0    | e1000_fc_none
3550                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3551                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3552                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3553                          *   1   |    1    |   0   |    0    | e1000_fc_none
3554                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3555                          *
3556                          */
3557                         /* Are both PAUSE bits set to 1?  If so, this implies
3558                          * Symmetric Flow Control is enabled at both ends.  The
3559                          * ASM_DIR bits are irrelevant per the spec.
3560                          *
3561                          * For Symmetric Flow Control:
3562                          *
3563                          *   LOCAL DEVICE  |   LINK PARTNER
3564                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3565                          *-------|---------|-------|---------|--------------------
3566                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3567                          *
3568                          */
3569                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3570                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3571                                 /* Now we need to check if the user selected RX ONLY
3572                                  * of pause frames.  In this case, we had to advertise
3573                                  * FULL flow control because we could not advertise RX
3574                                  * ONLY. Hence, we must now check to see if we need to
3575                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3576                                  */
3577                                 if (hw->original_fc == e1000_fc_full) {
3578                                         hw->fc = e1000_fc_full;
3579                                         DEBUGOUT("Flow Control = FULL.\r\n");
3580                                 } else {
3581                                         hw->fc = e1000_fc_rx_pause;
3582                                         DEBUGOUT
3583                                             ("Flow Control = RX PAUSE frames only.\r\n");
3584                                 }
3585                         }
3586                         /* For receiving PAUSE frames ONLY.
3587                          *
3588                          *   LOCAL DEVICE  |   LINK PARTNER
3589                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3590                          *-------|---------|-------|---------|--------------------
3591                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3592                          *
3593                          */
3594                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3595                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3596                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3597                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3598                         {
3599                                 hw->fc = e1000_fc_tx_pause;
3600                                 DEBUGOUT
3601                                     ("Flow Control = TX PAUSE frames only.\r\n");
3602                         }
3603                         /* For transmitting PAUSE frames ONLY.
3604                          *
3605                          *   LOCAL DEVICE  |   LINK PARTNER
3606                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3607                          *-------|---------|-------|---------|--------------------
3608                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3609                          *
3610                          */
3611                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3612                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3613                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3614                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3615                         {
3616                                 hw->fc = e1000_fc_rx_pause;
3617                                 DEBUGOUT
3618                                     ("Flow Control = RX PAUSE frames only.\r\n");
3619                         }
3620                         /* Per the IEEE spec, at this point flow control should be
3621                          * disabled.  However, we want to consider that we could
3622                          * be connected to a legacy switch that doesn't advertise
3623                          * desired flow control, but can be forced on the link
3624                          * partner.  So if we advertised no flow control, that is
3625                          * what we will resolve to.  If we advertised some kind of
3626                          * receive capability (Rx Pause Only or Full Flow Control)
3627                          * and the link partner advertised none, we will configure
3628                          * ourselves to enable Rx Flow Control only.  We can do
3629                          * this safely for two reasons:  If the link partner really
3630                          * didn't want flow control enabled, and we enable Rx, no
3631                          * harm done since we won't be receiving any PAUSE frames
3632                          * anyway.  If the intent on the link partner was to have
3633                          * flow control enabled, then by us enabling RX only, we
3634                          * can at least receive pause frames and process them.
3635                          * This is a good idea because in most cases, since we are
3636                          * predominantly a server NIC, more times than not we will
3637                          * be asked to delay transmission of packets than asking
3638                          * our link partner to pause transmission of frames.
3639                          */
3640                         else if (hw->original_fc == e1000_fc_none ||
3641                                  hw->original_fc == e1000_fc_tx_pause) {
3642                                 hw->fc = e1000_fc_none;
3643                                 DEBUGOUT("Flow Control = NONE.\r\n");
3644                         } else {
3645                                 hw->fc = e1000_fc_rx_pause;
3646                                 DEBUGOUT
3647                                     ("Flow Control = RX PAUSE frames only.\r\n");
3648                         }
3649
3650                         /* Now we need to do one last check...  If we auto-
3651                          * negotiated to HALF DUPLEX, flow control should not be
3652                          * enabled per IEEE 802.3 spec.
3653                          */
3654                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3655
3656                         if (duplex == HALF_DUPLEX)
3657                                 hw->fc = e1000_fc_none;
3658
3659                         /* Now we call a subroutine to actually force the MAC
3660                          * controller to use the correct flow control settings.
3661                          */
3662                         ret_val = e1000_force_mac_fc(hw);
3663                         if (ret_val < 0) {
3664                                 DEBUGOUT
3665                                     ("Error forcing flow control settings\n");
3666                                 return ret_val;
3667                         }
3668                 } else {
3669                         DEBUGOUT
3670                             ("Copper PHY and Auto Neg has not completed.\r\n");
3671                 }
3672         }
3673         return E1000_SUCCESS;
3674 }
3675
3676 /******************************************************************************
3677  * Checks to see if the link status of the hardware has changed.
3678  *
3679  * hw - Struct containing variables accessed by shared code
3680  *
3681  * Called by any function that needs to check the link status of the adapter.
3682  *****************************************************************************/
3683 static int
3684 e1000_check_for_link(struct eth_device *nic)
3685 {
3686         struct e1000_hw *hw = nic->priv;
3687         uint32_t rxcw;
3688         uint32_t ctrl;
3689         uint32_t status;
3690         uint32_t rctl;
3691         uint32_t signal;
3692         int32_t ret_val;
3693         uint16_t phy_data;
3694         uint16_t lp_capability;
3695
3696         DEBUGFUNC();
3697
3698         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3699          * set when the optics detect a signal. On older adapters, it will be
3700          * cleared when there is a signal
3701          */
3702         ctrl = E1000_READ_REG(hw, CTRL);
3703         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3704                 signal = E1000_CTRL_SWDPIN1;
3705         else
3706                 signal = 0;
3707
3708         status = E1000_READ_REG(hw, STATUS);
3709         rxcw = E1000_READ_REG(hw, RXCW);
3710         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3711
3712         /* If we have a copper PHY then we only want to go out to the PHY
3713          * registers to see if Auto-Neg has completed and/or if our link
3714          * status has changed.  The get_link_status flag will be set if we
3715          * receive a Link Status Change interrupt or we have Rx Sequence
3716          * Errors.
3717          */
3718         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3719                 /* First we want to see if the MII Status Register reports
3720                  * link.  If so, then we want to get the current speed/duplex
3721                  * of the PHY.
3722                  * Read the register twice since the link bit is sticky.
3723                  */
3724                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3725                         DEBUGOUT("PHY Read Error\n");
3726                         return -E1000_ERR_PHY;
3727                 }
3728                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3729                         DEBUGOUT("PHY Read Error\n");
3730                         return -E1000_ERR_PHY;
3731                 }
3732
3733                 if (phy_data & MII_SR_LINK_STATUS) {
3734                         hw->get_link_status = false;
3735                 } else {
3736                         /* No link detected */
3737                         return -E1000_ERR_NOLINK;
3738                 }
3739
3740                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3741                  * have Si on board that is 82544 or newer, Auto
3742                  * Speed Detection takes care of MAC speed/duplex
3743                  * configuration.  So we only need to configure Collision
3744                  * Distance in the MAC.  Otherwise, we need to force
3745                  * speed/duplex on the MAC to the current PHY speed/duplex
3746                  * settings.
3747                  */
3748                 if (hw->mac_type >= e1000_82544)
3749                         e1000_config_collision_dist(hw);
3750                 else {
3751                         ret_val = e1000_config_mac_to_phy(hw);
3752                         if (ret_val < 0) {
3753                                 DEBUGOUT
3754                                     ("Error configuring MAC to PHY settings\n");
3755                                 return ret_val;
3756                         }
3757                 }
3758
3759                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3760                  * need to restore the desired flow control settings because we may
3761                  * have had to re-autoneg with a different link partner.
3762                  */
3763                 ret_val = e1000_config_fc_after_link_up(hw);
3764                 if (ret_val < 0) {
3765                         DEBUGOUT("Error configuring flow control\n");
3766                         return ret_val;
3767                 }
3768
3769                 /* At this point we know that we are on copper and we have
3770                  * auto-negotiated link.  These are conditions for checking the link
3771                  * parter capability register.  We use the link partner capability to
3772                  * determine if TBI Compatibility needs to be turned on or off.  If
3773                  * the link partner advertises any speed in addition to Gigabit, then
3774                  * we assume that they are GMII-based, and TBI compatibility is not
3775                  * needed. If no other speeds are advertised, we assume the link
3776                  * partner is TBI-based, and we turn on TBI Compatibility.
3777                  */
3778                 if (hw->tbi_compatibility_en) {
3779                         if (e1000_read_phy_reg
3780                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3781                                 DEBUGOUT("PHY Read Error\n");
3782                                 return -E1000_ERR_PHY;
3783                         }
3784                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3785                                              NWAY_LPAR_10T_FD_CAPS |
3786                                              NWAY_LPAR_100TX_HD_CAPS |
3787                                              NWAY_LPAR_100TX_FD_CAPS |
3788                                              NWAY_LPAR_100T4_CAPS)) {
3789                                 /* If our link partner advertises anything in addition to
3790                                  * gigabit, we do not need to enable TBI compatibility.
3791                                  */
3792                                 if (hw->tbi_compatibility_on) {
3793                                         /* If we previously were in the mode, turn it off. */
3794                                         rctl = E1000_READ_REG(hw, RCTL);
3795                                         rctl &= ~E1000_RCTL_SBP;
3796                                         E1000_WRITE_REG(hw, RCTL, rctl);
3797                                         hw->tbi_compatibility_on = false;
3798                                 }
3799                         } else {
3800                                 /* If TBI compatibility is was previously off, turn it on. For
3801                                  * compatibility with a TBI link partner, we will store bad
3802                                  * packets. Some frames have an additional byte on the end and
3803                                  * will look like CRC errors to to the hardware.
3804                                  */
3805                                 if (!hw->tbi_compatibility_on) {
3806                                         hw->tbi_compatibility_on = true;
3807                                         rctl = E1000_READ_REG(hw, RCTL);
3808                                         rctl |= E1000_RCTL_SBP;
3809                                         E1000_WRITE_REG(hw, RCTL, rctl);
3810                                 }
3811                         }
3812                 }
3813         }
3814         /* If we don't have link (auto-negotiation failed or link partner cannot
3815          * auto-negotiate), the cable is plugged in (we have signal), and our
3816          * link partner is not trying to auto-negotiate with us (we are receiving
3817          * idles or data), we need to force link up. We also need to give
3818          * auto-negotiation time to complete, in case the cable was just plugged
3819          * in. The autoneg_failed flag does this.
3820          */
3821         else if ((hw->media_type == e1000_media_type_fiber) &&
3822                  (!(status & E1000_STATUS_LU)) &&
3823                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3824                  (!(rxcw & E1000_RXCW_C))) {
3825                 if (hw->autoneg_failed == 0) {
3826                         hw->autoneg_failed = 1;
3827                         return 0;
3828                 }
3829                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3830
3831                 /* Disable auto-negotiation in the TXCW register */
3832                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3833
3834                 /* Force link-up and also force full-duplex. */
3835                 ctrl = E1000_READ_REG(hw, CTRL);
3836                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3837                 E1000_WRITE_REG(hw, CTRL, ctrl);
3838
3839                 /* Configure Flow Control after forcing link up. */
3840                 ret_val = e1000_config_fc_after_link_up(hw);
3841                 if (ret_val < 0) {
3842                         DEBUGOUT("Error configuring flow control\n");
3843                         return ret_val;
3844                 }
3845         }
3846         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3847          * auto-negotiation in the TXCW register and disable forced link in the
3848          * Device Control register in an attempt to auto-negotiate with our link
3849          * partner.
3850          */
3851         else if ((hw->media_type == e1000_media_type_fiber) &&
3852                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3853                 DEBUGOUT
3854                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3855                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3856                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3857         }
3858         return 0;
3859 }
3860
3861 /******************************************************************************
3862 * Configure the MAC-to-PHY interface for 10/100Mbps
3863 *
3864 * hw - Struct containing variables accessed by shared code
3865 ******************************************************************************/
3866 static int32_t
3867 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3868 {
3869         int32_t ret_val = E1000_SUCCESS;
3870         uint32_t tipg;
3871         uint16_t reg_data;
3872
3873         DEBUGFUNC();
3874
3875         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3876         ret_val = e1000_write_kmrn_reg(hw,
3877                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3878         if (ret_val)
3879                 return ret_val;
3880
3881         /* Configure Transmit Inter-Packet Gap */
3882         tipg = E1000_READ_REG(hw, TIPG);
3883         tipg &= ~E1000_TIPG_IPGT_MASK;
3884         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3885         E1000_WRITE_REG(hw, TIPG, tipg);
3886
3887         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3888
3889         if (ret_val)
3890                 return ret_val;
3891
3892         if (duplex == HALF_DUPLEX)
3893                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3894         else
3895                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3896
3897         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3898
3899         return ret_val;
3900 }
3901
3902 static int32_t
3903 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3904 {
3905         int32_t ret_val = E1000_SUCCESS;
3906         uint16_t reg_data;
3907         uint32_t tipg;
3908
3909         DEBUGFUNC();
3910
3911         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3912         ret_val = e1000_write_kmrn_reg(hw,
3913                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3914         if (ret_val)
3915                 return ret_val;
3916
3917         /* Configure Transmit Inter-Packet Gap */
3918         tipg = E1000_READ_REG(hw, TIPG);
3919         tipg &= ~E1000_TIPG_IPGT_MASK;
3920         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3921         E1000_WRITE_REG(hw, TIPG, tipg);
3922
3923         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3924
3925         if (ret_val)
3926                 return ret_val;
3927
3928         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3929         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3930
3931         return ret_val;
3932 }
3933
3934 /******************************************************************************
3935  * Detects the current speed and duplex settings of the hardware.
3936  *
3937  * hw - Struct containing variables accessed by shared code
3938  * speed - Speed of the connection
3939  * duplex - Duplex setting of the connection
3940  *****************************************************************************/
3941 static int
3942 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3943                 uint16_t *duplex)
3944 {
3945         uint32_t status;
3946         int32_t ret_val;
3947         uint16_t phy_data;
3948
3949         DEBUGFUNC();
3950
3951         if (hw->mac_type >= e1000_82543) {
3952                 status = E1000_READ_REG(hw, STATUS);
3953                 if (status & E1000_STATUS_SPEED_1000) {
3954                         *speed = SPEED_1000;
3955                         DEBUGOUT("1000 Mbs, ");
3956                 } else if (status & E1000_STATUS_SPEED_100) {
3957                         *speed = SPEED_100;
3958                         DEBUGOUT("100 Mbs, ");
3959                 } else {
3960                         *speed = SPEED_10;
3961                         DEBUGOUT("10 Mbs, ");
3962                 }
3963
3964                 if (status & E1000_STATUS_FD) {
3965                         *duplex = FULL_DUPLEX;
3966                         DEBUGOUT("Full Duplex\r\n");
3967                 } else {
3968                         *duplex = HALF_DUPLEX;
3969                         DEBUGOUT(" Half Duplex\r\n");
3970                 }
3971         } else {
3972                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3973                 *speed = SPEED_1000;
3974                 *duplex = FULL_DUPLEX;
3975         }
3976
3977         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3978          * even if it is operating at half duplex.  Here we set the duplex
3979          * settings to match the duplex in the link partner's capabilities.
3980          */
3981         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3982                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3983                 if (ret_val)
3984                         return ret_val;
3985
3986                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3987                         *duplex = HALF_DUPLEX;
3988                 else {
3989                         ret_val = e1000_read_phy_reg(hw,
3990                                         PHY_LP_ABILITY, &phy_data);
3991                         if (ret_val)
3992                                 return ret_val;
3993                         if ((*speed == SPEED_100 &&
3994                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3995                                 || (*speed == SPEED_10
3996                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3997                                 *duplex = HALF_DUPLEX;
3998                 }
3999         }
4000
4001         if ((hw->mac_type == e1000_80003es2lan) &&
4002                 (hw->media_type == e1000_media_type_copper)) {
4003                 if (*speed == SPEED_1000)
4004                         ret_val = e1000_configure_kmrn_for_1000(hw);
4005                 else
4006                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4007                 if (ret_val)
4008                         return ret_val;
4009         }
4010         return E1000_SUCCESS;
4011 }
4012
4013 /******************************************************************************
4014 * Blocks until autoneg completes or times out (~4.5 seconds)
4015 *
4016 * hw - Struct containing variables accessed by shared code
4017 ******************************************************************************/
4018 static int
4019 e1000_wait_autoneg(struct e1000_hw *hw)
4020 {
4021         uint16_t i;
4022         uint16_t phy_data;
4023
4024         DEBUGFUNC();
4025         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4026
4027         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4028         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4029                 /* Read the MII Status Register and wait for Auto-Neg
4030                  * Complete bit to be set.
4031                  */
4032                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4033                         DEBUGOUT("PHY Read Error\n");
4034                         return -E1000_ERR_PHY;
4035                 }
4036                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4037                         DEBUGOUT("PHY Read Error\n");
4038                         return -E1000_ERR_PHY;
4039                 }
4040                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4041                         DEBUGOUT("Auto-Neg complete.\n");
4042                         return 0;
4043                 }
4044                 mdelay(100);
4045         }
4046         DEBUGOUT("Auto-Neg timedout.\n");
4047         return -E1000_ERR_TIMEOUT;
4048 }
4049
4050 /******************************************************************************
4051 * Raises the Management Data Clock
4052 *
4053 * hw - Struct containing variables accessed by shared code
4054 * ctrl - Device control register's current value
4055 ******************************************************************************/
4056 static void
4057 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4058 {
4059         /* Raise the clock input to the Management Data Clock (by setting the MDC
4060          * bit), and then delay 2 microseconds.
4061          */
4062         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4063         E1000_WRITE_FLUSH(hw);
4064         udelay(2);
4065 }
4066
4067 /******************************************************************************
4068 * Lowers the Management Data Clock
4069 *
4070 * hw - Struct containing variables accessed by shared code
4071 * ctrl - Device control register's current value
4072 ******************************************************************************/
4073 static void
4074 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4075 {
4076         /* Lower the clock input to the Management Data Clock (by clearing the MDC
4077          * bit), and then delay 2 microseconds.
4078          */
4079         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4080         E1000_WRITE_FLUSH(hw);
4081         udelay(2);
4082 }
4083
4084 /******************************************************************************
4085 * Shifts data bits out to the PHY
4086 *
4087 * hw - Struct containing variables accessed by shared code
4088 * data - Data to send out to the PHY
4089 * count - Number of bits to shift out
4090 *
4091 * Bits are shifted out in MSB to LSB order.
4092 ******************************************************************************/
4093 static void
4094 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4095 {
4096         uint32_t ctrl;
4097         uint32_t mask;
4098
4099         /* We need to shift "count" number of bits out to the PHY. So, the value
4100          * in the "data" parameter will be shifted out to the PHY one bit at a
4101          * time. In order to do this, "data" must be broken down into bits.
4102          */
4103         mask = 0x01;
4104         mask <<= (count - 1);
4105
4106         ctrl = E1000_READ_REG(hw, CTRL);
4107
4108         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4109         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4110
4111         while (mask) {
4112                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4113                  * then raising and lowering the Management Data Clock. A "0" is
4114                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4115                  * raising and lowering the clock.
4116                  */
4117                 if (data & mask)
4118                         ctrl |= E1000_CTRL_MDIO;
4119                 else
4120                         ctrl &= ~E1000_CTRL_MDIO;
4121
4122                 E1000_WRITE_REG(hw, CTRL, ctrl);
4123                 E1000_WRITE_FLUSH(hw);
4124
4125                 udelay(2);
4126
4127                 e1000_raise_mdi_clk(hw, &ctrl);
4128                 e1000_lower_mdi_clk(hw, &ctrl);
4129
4130                 mask = mask >> 1;
4131         }
4132 }
4133
4134 /******************************************************************************
4135 * Shifts data bits in from the PHY
4136 *
4137 * hw - Struct containing variables accessed by shared code
4138 *
4139 * Bits are shifted in in MSB to LSB order.
4140 ******************************************************************************/
4141 static uint16_t
4142 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4143 {
4144         uint32_t ctrl;
4145         uint16_t data = 0;
4146         uint8_t i;
4147
4148         /* In order to read a register from the PHY, we need to shift in a total
4149          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4150          * to avoid contention on the MDIO pin when a read operation is performed.
4151          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4152          * by raising the input to the Management Data Clock (setting the MDC bit),
4153          * and then reading the value of the MDIO bit.
4154          */
4155         ctrl = E1000_READ_REG(hw, CTRL);
4156
4157         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4158         ctrl &= ~E1000_CTRL_MDIO_DIR;
4159         ctrl &= ~E1000_CTRL_MDIO;
4160
4161         E1000_WRITE_REG(hw, CTRL, ctrl);
4162         E1000_WRITE_FLUSH(hw);
4163
4164         /* Raise and Lower the clock before reading in the data. This accounts for
4165          * the turnaround bits. The first clock occurred when we clocked out the
4166          * last bit of the Register Address.
4167          */
4168         e1000_raise_mdi_clk(hw, &ctrl);
4169         e1000_lower_mdi_clk(hw, &ctrl);
4170
4171         for (data = 0, i = 0; i < 16; i++) {
4172                 data = data << 1;
4173                 e1000_raise_mdi_clk(hw, &ctrl);
4174                 ctrl = E1000_READ_REG(hw, CTRL);
4175                 /* Check to see if we shifted in a "1". */
4176                 if (ctrl & E1000_CTRL_MDIO)
4177                         data |= 1;
4178                 e1000_lower_mdi_clk(hw, &ctrl);
4179         }
4180
4181         e1000_raise_mdi_clk(hw, &ctrl);
4182         e1000_lower_mdi_clk(hw, &ctrl);
4183
4184         return data;
4185 }
4186
4187 /*****************************************************************************
4188 * Reads the value from a PHY register
4189 *
4190 * hw - Struct containing variables accessed by shared code
4191 * reg_addr - address of the PHY register to read
4192 ******************************************************************************/
4193 static int
4194 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4195 {
4196         uint32_t i;
4197         uint32_t mdic = 0;
4198         const uint32_t phy_addr = 1;
4199
4200         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4201                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4202                 return -E1000_ERR_PARAM;
4203         }
4204
4205         if (hw->mac_type > e1000_82543) {
4206                 /* Set up Op-code, Phy Address, and register address in the MDI
4207                  * Control register.  The MAC will take care of interfacing with the
4208                  * PHY to retrieve the desired data.
4209                  */
4210                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4211                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4212                         (E1000_MDIC_OP_READ));
4213
4214                 E1000_WRITE_REG(hw, MDIC, mdic);
4215
4216                 /* Poll the ready bit to see if the MDI read completed */
4217                 for (i = 0; i < 64; i++) {
4218                         udelay(10);
4219                         mdic = E1000_READ_REG(hw, MDIC);
4220                         if (mdic & E1000_MDIC_READY)
4221                                 break;
4222                 }
4223                 if (!(mdic & E1000_MDIC_READY)) {
4224                         DEBUGOUT("MDI Read did not complete\n");
4225                         return -E1000_ERR_PHY;
4226                 }
4227                 if (mdic & E1000_MDIC_ERROR) {
4228                         DEBUGOUT("MDI Error\n");
4229                         return -E1000_ERR_PHY;
4230                 }
4231                 *phy_data = (uint16_t) mdic;
4232         } else {
4233                 /* We must first send a preamble through the MDIO pin to signal the
4234                  * beginning of an MII instruction.  This is done by sending 32
4235                  * consecutive "1" bits.
4236                  */
4237                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4238
4239                 /* Now combine the next few fields that are required for a read
4240                  * operation.  We use this method instead of calling the
4241                  * e1000_shift_out_mdi_bits routine five different times. The format of
4242                  * a MII read instruction consists of a shift out of 14 bits and is
4243                  * defined as follows:
4244                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4245                  * followed by a shift in of 18 bits.  This first two bits shifted in
4246                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4247                  * READ operation is performed.  These two bits are thrown away
4248                  * followed by a shift in of 16 bits which contains the desired data.
4249                  */
4250                 mdic = ((reg_addr) | (phy_addr << 5) |
4251                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4252
4253                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4254
4255                 /* Now that we've shifted out the read command to the MII, we need to
4256                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4257                  * register address.
4258                  */
4259                 *phy_data = e1000_shift_in_mdi_bits(hw);
4260         }
4261         return 0;
4262 }
4263
4264 /******************************************************************************
4265 * Writes a value to a PHY register
4266 *
4267 * hw - Struct containing variables accessed by shared code
4268 * reg_addr - address of the PHY register to write
4269 * data - data to write to the PHY
4270 ******************************************************************************/
4271 static int
4272 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4273 {
4274         uint32_t i;
4275         uint32_t mdic = 0;
4276         const uint32_t phy_addr = 1;
4277
4278         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4279                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4280                 return -E1000_ERR_PARAM;
4281         }
4282
4283         if (hw->mac_type > e1000_82543) {
4284                 /* Set up Op-code, Phy Address, register address, and data intended
4285                  * for the PHY register in the MDI Control register.  The MAC will take
4286                  * care of interfacing with the PHY to send the desired data.
4287                  */
4288                 mdic = (((uint32_t) phy_data) |
4289                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4290                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4291                         (E1000_MDIC_OP_WRITE));
4292
4293                 E1000_WRITE_REG(hw, MDIC, mdic);
4294
4295                 /* Poll the ready bit to see if the MDI read completed */
4296                 for (i = 0; i < 64; i++) {
4297                         udelay(10);
4298                         mdic = E1000_READ_REG(hw, MDIC);
4299                         if (mdic & E1000_MDIC_READY)
4300                                 break;
4301                 }
4302                 if (!(mdic & E1000_MDIC_READY)) {
4303                         DEBUGOUT("MDI Write did not complete\n");
4304                         return -E1000_ERR_PHY;
4305                 }
4306         } else {
4307                 /* We'll need to use the SW defined pins to shift the write command
4308                  * out to the PHY. We first send a preamble to the PHY to signal the
4309                  * beginning of the MII instruction.  This is done by sending 32
4310                  * consecutive "1" bits.
4311                  */
4312                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4313
4314                 /* Now combine the remaining required fields that will indicate a
4315                  * write operation. We use this method instead of calling the
4316                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4317                  * format of a MII write instruction is as follows:
4318                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4319                  */
4320                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4321                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4322                 mdic <<= 16;
4323                 mdic |= (uint32_t) phy_data;
4324
4325                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4326         }
4327         return 0;
4328 }
4329
4330 /******************************************************************************
4331  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4332  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4333  * the caller to figure out how to deal with it.
4334  *
4335  * hw - Struct containing variables accessed by shared code
4336  *
4337  * returns: - E1000_BLK_PHY_RESET
4338  *            E1000_SUCCESS
4339  *
4340  *****************************************************************************/
4341 int32_t
4342 e1000_check_phy_reset_block(struct e1000_hw *hw)
4343 {
4344         uint32_t manc = 0;
4345         uint32_t fwsm = 0;
4346
4347         if (hw->mac_type == e1000_ich8lan) {
4348                 fwsm = E1000_READ_REG(hw, FWSM);
4349                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4350                                                 : E1000_BLK_PHY_RESET;
4351         }
4352
4353         if (hw->mac_type > e1000_82547_rev_2)
4354                 manc = E1000_READ_REG(hw, MANC);
4355         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4356                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4357 }
4358
4359 /***************************************************************************
4360  * Checks if the PHY configuration is done
4361  *
4362  * hw: Struct containing variables accessed by shared code
4363  *
4364  * returns: - E1000_ERR_RESET if fail to reset MAC
4365  *            E1000_SUCCESS at any other case.
4366  *
4367  ***************************************************************************/
4368 static int32_t
4369 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4370 {
4371         int32_t timeout = PHY_CFG_TIMEOUT;
4372         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4373
4374         DEBUGFUNC();
4375
4376         switch (hw->mac_type) {
4377         default:
4378                 mdelay(10);
4379                 break;
4380
4381         case e1000_80003es2lan:
4382                 /* Separate *_CFG_DONE_* bit for each port */
4383                 if (e1000_is_second_port(hw))
4384                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4385                 /* Fall Through */
4386
4387         case e1000_82571:
4388         case e1000_82572:
4389         case e1000_igb:
4390                 while (timeout) {
4391                         if (hw->mac_type == e1000_igb) {
4392                                 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4393                                         break;
4394                         } else {
4395                                 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4396                                         break;
4397                         }
4398                         mdelay(1);
4399                         timeout--;
4400                 }
4401                 if (!timeout) {
4402                         DEBUGOUT("MNG configuration cycle has not "
4403                                         "completed.\n");
4404                         return -E1000_ERR_RESET;
4405                 }
4406                 break;
4407         }
4408
4409         return E1000_SUCCESS;
4410 }
4411
4412 /******************************************************************************
4413 * Returns the PHY to the power-on reset state
4414 *
4415 * hw - Struct containing variables accessed by shared code
4416 ******************************************************************************/
4417 int32_t
4418 e1000_phy_hw_reset(struct e1000_hw *hw)
4419 {
4420         uint16_t swfw = E1000_SWFW_PHY0_SM;
4421         uint32_t ctrl, ctrl_ext;
4422         uint32_t led_ctrl;
4423         int32_t ret_val;
4424
4425         DEBUGFUNC();
4426
4427         /* In the case of the phy reset being blocked, it's not an error, we
4428          * simply return success without performing the reset. */
4429         ret_val = e1000_check_phy_reset_block(hw);
4430         if (ret_val)
4431                 return E1000_SUCCESS;
4432
4433         DEBUGOUT("Resetting Phy...\n");
4434
4435         if (hw->mac_type > e1000_82543) {
4436                 if (e1000_is_second_port(hw))
4437                         swfw = E1000_SWFW_PHY1_SM;
4438
4439                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4440                         DEBUGOUT("Unable to acquire swfw sync\n");
4441                         return -E1000_ERR_SWFW_SYNC;
4442                 }
4443
4444                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4445                  * bit. Then, take it out of reset.
4446                  */
4447                 ctrl = E1000_READ_REG(hw, CTRL);
4448                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4449                 E1000_WRITE_FLUSH(hw);
4450
4451                 if (hw->mac_type < e1000_82571)
4452                         udelay(10);
4453                 else
4454                         udelay(100);
4455
4456                 E1000_WRITE_REG(hw, CTRL, ctrl);
4457                 E1000_WRITE_FLUSH(hw);
4458
4459                 if (hw->mac_type >= e1000_82571)
4460                         mdelay(10);
4461         } else {
4462                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4463                  * bit to put the PHY into reset. Then, take it out of reset.
4464                  */
4465                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4466                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4467                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4468                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4469                 E1000_WRITE_FLUSH(hw);
4470                 mdelay(10);
4471                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4472                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4473                 E1000_WRITE_FLUSH(hw);
4474         }
4475         udelay(150);
4476
4477         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4478                 /* Configure activity LED after PHY reset */
4479                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4480                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4481                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4482                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4483         }
4484
4485         e1000_swfw_sync_release(hw, swfw);
4486
4487         /* Wait for FW to finish PHY configuration. */
4488         ret_val = e1000_get_phy_cfg_done(hw);
4489         if (ret_val != E1000_SUCCESS)
4490                 return ret_val;
4491
4492         return ret_val;
4493 }
4494
4495 /******************************************************************************
4496  * IGP phy init script - initializes the GbE PHY
4497  *
4498  * hw - Struct containing variables accessed by shared code
4499  *****************************************************************************/
4500 static void
4501 e1000_phy_init_script(struct e1000_hw *hw)
4502 {
4503         uint32_t ret_val;
4504         uint16_t phy_saved_data;
4505         DEBUGFUNC();
4506
4507         if (hw->phy_init_script) {
4508                 mdelay(20);
4509
4510                 /* Save off the current value of register 0x2F5B to be
4511                  * restored at the end of this routine. */
4512                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4513
4514                 /* Disabled the PHY transmitter */
4515                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4516
4517                 mdelay(20);
4518
4519                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4520
4521                 mdelay(5);
4522
4523                 switch (hw->mac_type) {
4524                 case e1000_82541:
4525                 case e1000_82547:
4526                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4527
4528                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4529
4530                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4531
4532                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4533
4534                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4535
4536                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4537
4538                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4539
4540                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4541
4542                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4543                         break;
4544
4545                 case e1000_82541_rev_2:
4546                 case e1000_82547_rev_2:
4547                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4548                         break;
4549                 default:
4550                         break;
4551                 }
4552
4553                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4554
4555                 mdelay(20);
4556
4557                 /* Now enable the transmitter */
4558                 if (!ret_val)
4559                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4560
4561                 if (hw->mac_type == e1000_82547) {
4562                         uint16_t fused, fine, coarse;
4563
4564                         /* Move to analog registers page */
4565                         e1000_read_phy_reg(hw,
4566                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4567
4568                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4569                                 e1000_read_phy_reg(hw,
4570                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4571
4572                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4573                                 coarse = fused
4574                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4575
4576                                 if (coarse >
4577                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4578                                         coarse -=
4579                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4580                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4581                                 } else if (coarse
4582                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4583                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4584
4585                                 fused = (fused
4586                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4587                                         (fine
4588                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4589                                         (coarse
4590                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4591
4592                                 e1000_write_phy_reg(hw,
4593                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4594                                 e1000_write_phy_reg(hw,
4595                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4596                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4597                         }
4598                 }
4599         }
4600 }
4601
4602 /******************************************************************************
4603 * Resets the PHY
4604 *
4605 * hw - Struct containing variables accessed by shared code
4606 *
4607 * Sets bit 15 of the MII Control register
4608 ******************************************************************************/
4609 int32_t
4610 e1000_phy_reset(struct e1000_hw *hw)
4611 {
4612         int32_t ret_val;
4613         uint16_t phy_data;
4614
4615         DEBUGFUNC();
4616
4617         /* In the case of the phy reset being blocked, it's not an error, we
4618          * simply return success without performing the reset. */
4619         ret_val = e1000_check_phy_reset_block(hw);
4620         if (ret_val)
4621                 return E1000_SUCCESS;
4622
4623         switch (hw->phy_type) {
4624         case e1000_phy_igp:
4625         case e1000_phy_igp_2:
4626         case e1000_phy_igp_3:
4627         case e1000_phy_ife:
4628         case e1000_phy_igb:
4629                 ret_val = e1000_phy_hw_reset(hw);
4630                 if (ret_val)
4631                         return ret_val;
4632                 break;
4633         default:
4634                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4635                 if (ret_val)
4636                         return ret_val;
4637
4638                 phy_data |= MII_CR_RESET;
4639                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4640                 if (ret_val)
4641                         return ret_val;
4642
4643                 udelay(1);
4644                 break;
4645         }
4646
4647         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4648                 e1000_phy_init_script(hw);
4649
4650         return E1000_SUCCESS;
4651 }
4652
4653 static int e1000_set_phy_type (struct e1000_hw *hw)
4654 {
4655         DEBUGFUNC ();
4656
4657         if (hw->mac_type == e1000_undefined)
4658                 return -E1000_ERR_PHY_TYPE;
4659
4660         switch (hw->phy_id) {
4661         case M88E1000_E_PHY_ID:
4662         case M88E1000_I_PHY_ID:
4663         case M88E1011_I_PHY_ID:
4664         case M88E1111_I_PHY_ID:
4665                 hw->phy_type = e1000_phy_m88;
4666                 break;
4667         case IGP01E1000_I_PHY_ID:
4668                 if (hw->mac_type == e1000_82541 ||
4669                         hw->mac_type == e1000_82541_rev_2 ||
4670                         hw->mac_type == e1000_82547 ||
4671                         hw->mac_type == e1000_82547_rev_2) {
4672                         hw->phy_type = e1000_phy_igp;
4673                         break;
4674                 }
4675         case IGP03E1000_E_PHY_ID:
4676                 hw->phy_type = e1000_phy_igp_3;
4677                 break;
4678         case IFE_E_PHY_ID:
4679         case IFE_PLUS_E_PHY_ID:
4680         case IFE_C_E_PHY_ID:
4681                 hw->phy_type = e1000_phy_ife;
4682                 break;
4683         case GG82563_E_PHY_ID:
4684                 if (hw->mac_type == e1000_80003es2lan) {
4685                         hw->phy_type = e1000_phy_gg82563;
4686                         break;
4687                 }
4688         case BME1000_E_PHY_ID:
4689                 hw->phy_type = e1000_phy_bm;
4690                 break;
4691         case I210_I_PHY_ID:
4692                 hw->phy_type = e1000_phy_igb;
4693                 break;
4694                 /* Fall Through */
4695         default:
4696                 /* Should never have loaded on this device */
4697                 hw->phy_type = e1000_phy_undefined;
4698                 return -E1000_ERR_PHY_TYPE;
4699         }
4700
4701         return E1000_SUCCESS;
4702 }
4703
4704 /******************************************************************************
4705 * Probes the expected PHY address for known PHY IDs
4706 *
4707 * hw - Struct containing variables accessed by shared code
4708 ******************************************************************************/
4709 static int32_t
4710 e1000_detect_gig_phy(struct e1000_hw *hw)
4711 {
4712         int32_t phy_init_status, ret_val;
4713         uint16_t phy_id_high, phy_id_low;
4714         bool match = false;
4715
4716         DEBUGFUNC();
4717
4718         /* The 82571 firmware may still be configuring the PHY.  In this
4719          * case, we cannot access the PHY until the configuration is done.  So
4720          * we explicitly set the PHY values. */
4721         if (hw->mac_type == e1000_82571 ||
4722                 hw->mac_type == e1000_82572) {
4723                 hw->phy_id = IGP01E1000_I_PHY_ID;
4724                 hw->phy_type = e1000_phy_igp_2;
4725                 return E1000_SUCCESS;
4726         }
4727
4728         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4729          * work- around that forces PHY page 0 to be set or the reads fail.
4730          * The rest of the code in this routine uses e1000_read_phy_reg to
4731          * read the PHY ID.  So for ESB-2 we need to have this set so our
4732          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4733          * the routines below will figure this out as well. */
4734         if (hw->mac_type == e1000_80003es2lan)
4735                 hw->phy_type = e1000_phy_gg82563;
4736
4737         /* Read the PHY ID Registers to identify which PHY is onboard. */
4738         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4739         if (ret_val)
4740                 return ret_val;
4741
4742         hw->phy_id = (uint32_t) (phy_id_high << 16);
4743         udelay(20);
4744         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4745         if (ret_val)
4746                 return ret_val;
4747
4748         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4749         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4750
4751         switch (hw->mac_type) {
4752         case e1000_82543:
4753                 if (hw->phy_id == M88E1000_E_PHY_ID)
4754                         match = true;
4755                 break;
4756         case e1000_82544:
4757                 if (hw->phy_id == M88E1000_I_PHY_ID)
4758                         match = true;
4759                 break;
4760         case e1000_82540:
4761         case e1000_82545:
4762         case e1000_82545_rev_3:
4763         case e1000_82546:
4764         case e1000_82546_rev_3:
4765                 if (hw->phy_id == M88E1011_I_PHY_ID)
4766                         match = true;
4767                 break;
4768         case e1000_82541:
4769         case e1000_82541_rev_2:
4770         case e1000_82547:
4771         case e1000_82547_rev_2:
4772                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4773                         match = true;
4774
4775                 break;
4776         case e1000_82573:
4777                 if (hw->phy_id == M88E1111_I_PHY_ID)
4778                         match = true;
4779                 break;
4780         case e1000_82574:
4781                 if (hw->phy_id == BME1000_E_PHY_ID)
4782                         match = true;
4783                 break;
4784         case e1000_80003es2lan:
4785                 if (hw->phy_id == GG82563_E_PHY_ID)
4786                         match = true;
4787                 break;
4788         case e1000_ich8lan:
4789                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4790                         match = true;
4791                 if (hw->phy_id == IFE_E_PHY_ID)
4792                         match = true;
4793                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4794                         match = true;
4795                 if (hw->phy_id == IFE_C_E_PHY_ID)
4796                         match = true;
4797                 break;
4798         case e1000_igb:
4799                 if (hw->phy_id == I210_I_PHY_ID)
4800                         match = true;
4801                 break;
4802         default:
4803                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4804                 return -E1000_ERR_CONFIG;
4805         }
4806
4807         phy_init_status = e1000_set_phy_type(hw);
4808
4809         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4810                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4811                 return 0;
4812         }
4813         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4814         return -E1000_ERR_PHY;
4815 }
4816
4817 /*****************************************************************************
4818  * Set media type and TBI compatibility.
4819  *
4820  * hw - Struct containing variables accessed by shared code
4821  * **************************************************************************/
4822 void
4823 e1000_set_media_type(struct e1000_hw *hw)
4824 {
4825         uint32_t status;
4826
4827         DEBUGFUNC();
4828
4829         if (hw->mac_type != e1000_82543) {
4830                 /* tbi_compatibility is only valid on 82543 */
4831                 hw->tbi_compatibility_en = false;
4832         }
4833
4834         switch (hw->device_id) {
4835         case E1000_DEV_ID_82545GM_SERDES:
4836         case E1000_DEV_ID_82546GB_SERDES:
4837         case E1000_DEV_ID_82571EB_SERDES:
4838         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4839         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4840         case E1000_DEV_ID_82572EI_SERDES:
4841         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4842                 hw->media_type = e1000_media_type_internal_serdes;
4843                 break;
4844         default:
4845                 switch (hw->mac_type) {
4846                 case e1000_82542_rev2_0:
4847                 case e1000_82542_rev2_1:
4848                         hw->media_type = e1000_media_type_fiber;
4849                         break;
4850                 case e1000_ich8lan:
4851                 case e1000_82573:
4852                 case e1000_82574:
4853                 case e1000_igb:
4854                         /* The STATUS_TBIMODE bit is reserved or reused
4855                          * for the this device.
4856                          */
4857                         hw->media_type = e1000_media_type_copper;
4858                         break;
4859                 default:
4860                         status = E1000_READ_REG(hw, STATUS);
4861                         if (status & E1000_STATUS_TBIMODE) {
4862                                 hw->media_type = e1000_media_type_fiber;
4863                                 /* tbi_compatibility not valid on fiber */
4864                                 hw->tbi_compatibility_en = false;
4865                         } else {
4866                                 hw->media_type = e1000_media_type_copper;
4867                         }
4868                         break;
4869                 }
4870         }
4871 }
4872
4873 /**
4874  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4875  *
4876  * e1000_sw_init initializes the Adapter private data structure.
4877  * Fields are initialized based on PCI device information and
4878  * OS network device settings (MTU size).
4879  **/
4880
4881 static int
4882 e1000_sw_init(struct eth_device *nic)
4883 {
4884         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4885         int result;
4886
4887         /* PCI config space info */
4888         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4889         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4890         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4891                              &hw->subsystem_vendor_id);
4892         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4893
4894         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4895         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4896
4897         /* identify the MAC */
4898         result = e1000_set_mac_type(hw);
4899         if (result) {
4900                 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4901                 return result;
4902         }
4903
4904         switch (hw->mac_type) {
4905         default:
4906                 break;
4907         case e1000_82541:
4908         case e1000_82547:
4909         case e1000_82541_rev_2:
4910         case e1000_82547_rev_2:
4911                 hw->phy_init_script = 1;
4912                 break;
4913         }
4914
4915         /* flow control settings */
4916         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4917         hw->fc_low_water = E1000_FC_LOW_THRESH;
4918         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4919         hw->fc_send_xon = 1;
4920
4921         /* Media type - copper or fiber */
4922         hw->tbi_compatibility_en = true;
4923         e1000_set_media_type(hw);
4924
4925         if (hw->mac_type >= e1000_82543) {
4926                 uint32_t status = E1000_READ_REG(hw, STATUS);
4927
4928                 if (status & E1000_STATUS_TBIMODE) {
4929                         DEBUGOUT("fiber interface\n");
4930                         hw->media_type = e1000_media_type_fiber;
4931                 } else {
4932                         DEBUGOUT("copper interface\n");
4933                         hw->media_type = e1000_media_type_copper;
4934                 }
4935         } else {
4936                 hw->media_type = e1000_media_type_fiber;
4937         }
4938
4939         hw->wait_autoneg_complete = true;
4940         if (hw->mac_type < e1000_82543)
4941                 hw->report_tx_early = 0;
4942         else
4943                 hw->report_tx_early = 1;
4944
4945         return E1000_SUCCESS;
4946 }
4947
4948 void
4949 fill_rx(struct e1000_hw *hw)
4950 {
4951         struct e1000_rx_desc *rd;
4952         unsigned long flush_start, flush_end;
4953
4954         rx_last = rx_tail;
4955         rd = rx_base + rx_tail;
4956         rx_tail = (rx_tail + 1) % 8;
4957         memset(rd, 0, 16);
4958         rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4959
4960         /*
4961          * Make sure there are no stale data in WB over this area, which
4962          * might get written into the memory while the e1000 also writes
4963          * into the same memory area.
4964          */
4965         invalidate_dcache_range((unsigned long)packet,
4966                                 (unsigned long)packet + 4096);
4967         /* Dump the DMA descriptor into RAM. */
4968         flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4969         flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4970         flush_dcache_range(flush_start, flush_end);
4971
4972         E1000_WRITE_REG(hw, RDT, rx_tail);
4973 }
4974
4975 /**
4976  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4977  * @adapter: board private structure
4978  *
4979  * Configure the Tx unit of the MAC after a reset.
4980  **/
4981
4982 static void
4983 e1000_configure_tx(struct e1000_hw *hw)
4984 {
4985         unsigned long tctl;
4986         unsigned long tipg, tarc;
4987         uint32_t ipgr1, ipgr2;
4988
4989         E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base);
4990         E1000_WRITE_REG(hw, TDBAH, 0);
4991
4992         E1000_WRITE_REG(hw, TDLEN, 128);
4993
4994         /* Setup the HW Tx Head and Tail descriptor pointers */
4995         E1000_WRITE_REG(hw, TDH, 0);
4996         E1000_WRITE_REG(hw, TDT, 0);
4997         tx_tail = 0;
4998
4999         /* Set the default values for the Tx Inter Packet Gap timer */
5000         if (hw->mac_type <= e1000_82547_rev_2 &&
5001             (hw->media_type == e1000_media_type_fiber ||
5002              hw->media_type == e1000_media_type_internal_serdes))
5003                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5004         else
5005                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5006
5007         /* Set the default values for the Tx Inter Packet Gap timer */
5008         switch (hw->mac_type) {
5009         case e1000_82542_rev2_0:
5010         case e1000_82542_rev2_1:
5011                 tipg = DEFAULT_82542_TIPG_IPGT;
5012                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5013                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5014                 break;
5015         case e1000_80003es2lan:
5016                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5017                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5018                 break;
5019         default:
5020                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5021                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5022                 break;
5023         }
5024         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5025         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5026         E1000_WRITE_REG(hw, TIPG, tipg);
5027         /* Program the Transmit Control Register */
5028         tctl = E1000_READ_REG(hw, TCTL);
5029         tctl &= ~E1000_TCTL_CT;
5030         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5031             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5032
5033         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5034                 tarc = E1000_READ_REG(hw, TARC0);
5035                 /* set the speed mode bit, we'll clear it if we're not at
5036                  * gigabit link later */
5037                 /* git bit can be set to 1*/
5038         } else if (hw->mac_type == e1000_80003es2lan) {
5039                 tarc = E1000_READ_REG(hw, TARC0);
5040                 tarc |= 1;
5041                 E1000_WRITE_REG(hw, TARC0, tarc);
5042                 tarc = E1000_READ_REG(hw, TARC1);
5043                 tarc |= 1;
5044                 E1000_WRITE_REG(hw, TARC1, tarc);
5045         }
5046
5047
5048         e1000_config_collision_dist(hw);
5049         /* Setup Transmit Descriptor Settings for eop descriptor */
5050         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5051
5052         /* Need to set up RS bit */
5053         if (hw->mac_type < e1000_82543)
5054                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5055         else
5056                 hw->txd_cmd |= E1000_TXD_CMD_RS;
5057
5058
5059         if (hw->mac_type == e1000_igb) {
5060                 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5061
5062                 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5063                 reg_txdctl |= 1 << 25;
5064                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5065                 mdelay(20);
5066         }
5067
5068
5069
5070         E1000_WRITE_REG(hw, TCTL, tctl);
5071
5072
5073 }
5074
5075 /**
5076  * e1000_setup_rctl - configure the receive control register
5077  * @adapter: Board private structure
5078  **/
5079 static void
5080 e1000_setup_rctl(struct e1000_hw *hw)
5081 {
5082         uint32_t rctl;
5083
5084         rctl = E1000_READ_REG(hw, RCTL);
5085
5086         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5087
5088         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5089                 | E1000_RCTL_RDMTS_HALF;        /* |
5090                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5091
5092         if (hw->tbi_compatibility_on == 1)
5093                 rctl |= E1000_RCTL_SBP;
5094         else
5095                 rctl &= ~E1000_RCTL_SBP;
5096
5097         rctl &= ~(E1000_RCTL_SZ_4096);
5098                 rctl |= E1000_RCTL_SZ_2048;
5099                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5100         E1000_WRITE_REG(hw, RCTL, rctl);
5101 }
5102
5103 /**
5104  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5105  * @adapter: board private structure
5106  *
5107  * Configure the Rx unit of the MAC after a reset.
5108  **/
5109 static void
5110 e1000_configure_rx(struct e1000_hw *hw)
5111 {
5112         unsigned long rctl, ctrl_ext;
5113         rx_tail = 0;
5114         /* make sure receives are disabled while setting up the descriptors */
5115         rctl = E1000_READ_REG(hw, RCTL);
5116         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5117         if (hw->mac_type >= e1000_82540) {
5118                 /* Set the interrupt throttling rate.  Value is calculated
5119                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5120 #define MAX_INTS_PER_SEC        8000
5121 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
5122                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5123         }
5124
5125         if (hw->mac_type >= e1000_82571) {
5126                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5127                 /* Reset delay timers after every interrupt */
5128                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5129                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5130                 E1000_WRITE_FLUSH(hw);
5131         }
5132         /* Setup the Base and Length of the Rx Descriptor Ring */
5133         E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base);
5134         E1000_WRITE_REG(hw, RDBAH, 0);
5135
5136         E1000_WRITE_REG(hw, RDLEN, 128);
5137
5138         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5139         E1000_WRITE_REG(hw, RDH, 0);
5140         E1000_WRITE_REG(hw, RDT, 0);
5141         /* Enable Receives */
5142
5143         if (hw->mac_type == e1000_igb) {
5144
5145                 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5146                 reg_rxdctl |= 1 << 25;
5147                 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5148                 mdelay(20);
5149         }
5150
5151         E1000_WRITE_REG(hw, RCTL, rctl);
5152
5153         fill_rx(hw);
5154 }
5155
5156 /**************************************************************************
5157 POLL - Wait for a frame
5158 ***************************************************************************/
5159 static int
5160 e1000_poll(struct eth_device *nic)
5161 {
5162         struct e1000_hw *hw = nic->priv;
5163         struct e1000_rx_desc *rd;
5164         unsigned long inval_start, inval_end;
5165         uint32_t len;
5166
5167         /* return true if there's an ethernet packet ready to read */
5168         rd = rx_base + rx_last;
5169
5170         /* Re-load the descriptor from RAM. */
5171         inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5172         inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5173         invalidate_dcache_range(inval_start, inval_end);
5174
5175         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5176                 return 0;
5177         /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5178         /* Packet received, make sure the data are re-loaded from RAM. */
5179         len = le32_to_cpu(rd->length);
5180         invalidate_dcache_range((unsigned long)packet,
5181                                 (unsigned long)packet +
5182                                 roundup(len, ARCH_DMA_MINALIGN));
5183         net_process_received_packet((uchar *)packet, len);
5184         fill_rx(hw);
5185         return 1;
5186 }
5187
5188 /**************************************************************************
5189 TRANSMIT - Transmit a frame
5190 ***************************************************************************/
5191 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5192 {
5193         void *nv_packet = (void *)txpacket;
5194         struct e1000_hw *hw = nic->priv;
5195         struct e1000_tx_desc *txp;
5196         int i = 0;
5197         unsigned long flush_start, flush_end;
5198
5199         txp = tx_base + tx_tail;
5200         tx_tail = (tx_tail + 1) % 8;
5201
5202         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5203         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5204         txp->upper.data = 0;
5205
5206         /* Dump the packet into RAM so e1000 can pick them. */
5207         flush_dcache_range((unsigned long)nv_packet,
5208                            (unsigned long)nv_packet +
5209                            roundup(length, ARCH_DMA_MINALIGN));
5210         /* Dump the descriptor into RAM as well. */
5211         flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5212         flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5213         flush_dcache_range(flush_start, flush_end);
5214
5215         E1000_WRITE_REG(hw, TDT, tx_tail);
5216
5217         E1000_WRITE_FLUSH(hw);
5218         while (1) {
5219                 invalidate_dcache_range(flush_start, flush_end);
5220                 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5221                         break;
5222                 if (i++ > TOUT_LOOP) {
5223                         DEBUGOUT("e1000: tx timeout\n");
5224                         return 0;
5225                 }
5226                 udelay(10);     /* give the nic a chance to write to the register */
5227         }
5228         return 1;
5229 }
5230
5231 /*reset function*/
5232 static inline int
5233 e1000_reset(struct eth_device *nic)
5234 {
5235         struct e1000_hw *hw = nic->priv;
5236
5237         e1000_reset_hw(hw);
5238         if (hw->mac_type >= e1000_82544) {
5239                 E1000_WRITE_REG(hw, WUC, 0);
5240         }
5241         return e1000_init_hw(nic);
5242 }
5243
5244 /**************************************************************************
5245 DISABLE - Turn off ethernet interface
5246 ***************************************************************************/
5247 static void
5248 e1000_disable(struct eth_device *nic)
5249 {
5250         struct e1000_hw *hw = nic->priv;
5251
5252         /* Turn off the ethernet interface */
5253         E1000_WRITE_REG(hw, RCTL, 0);
5254         E1000_WRITE_REG(hw, TCTL, 0);
5255
5256         /* Clear the transmit ring */
5257         E1000_WRITE_REG(hw, TDH, 0);
5258         E1000_WRITE_REG(hw, TDT, 0);
5259
5260         /* Clear the receive ring */
5261         E1000_WRITE_REG(hw, RDH, 0);
5262         E1000_WRITE_REG(hw, RDT, 0);
5263
5264         /* put the card in its initial state */
5265 #if 0
5266         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5267 #endif
5268         mdelay(10);
5269
5270 }
5271
5272 /**************************************************************************
5273 INIT - set up ethernet interface(s)
5274 ***************************************************************************/
5275 static int
5276 e1000_init(struct eth_device *nic, bd_t * bis)
5277 {
5278         struct e1000_hw *hw = nic->priv;
5279         int ret_val = 0;
5280
5281         ret_val = e1000_reset(nic);
5282         if (ret_val < 0) {
5283                 if ((ret_val == -E1000_ERR_NOLINK) ||
5284                     (ret_val == -E1000_ERR_TIMEOUT)) {
5285                         E1000_ERR(hw->nic, "Valid Link not detected\n");
5286                 } else {
5287                         E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5288                 }
5289                 return 0;
5290         }
5291         e1000_configure_tx(hw);
5292         e1000_setup_rctl(hw);
5293         e1000_configure_rx(hw);
5294         return 1;
5295 }
5296
5297 /******************************************************************************
5298  * Gets the current PCI bus type of hardware
5299  *
5300  * hw - Struct containing variables accessed by shared code
5301  *****************************************************************************/
5302 void e1000_get_bus_type(struct e1000_hw *hw)
5303 {
5304         uint32_t status;
5305
5306         switch (hw->mac_type) {
5307         case e1000_82542_rev2_0:
5308         case e1000_82542_rev2_1:
5309                 hw->bus_type = e1000_bus_type_pci;
5310                 break;
5311         case e1000_82571:
5312         case e1000_82572:
5313         case e1000_82573:
5314         case e1000_82574:
5315         case e1000_80003es2lan:
5316         case e1000_ich8lan:
5317         case e1000_igb:
5318                 hw->bus_type = e1000_bus_type_pci_express;
5319                 break;
5320         default:
5321                 status = E1000_READ_REG(hw, STATUS);
5322                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5323                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5324                 break;
5325         }
5326 }
5327
5328 /* A list of all registered e1000 devices */
5329 static LIST_HEAD(e1000_hw_list);
5330
5331 /**************************************************************************
5332 PROBE - Look for an adapter, this routine's visible to the outside
5333 You should omit the last argument struct pci_device * for a non-PCI NIC
5334 ***************************************************************************/
5335 int
5336 e1000_initialize(bd_t * bis)
5337 {
5338         unsigned int i;
5339         pci_dev_t devno;
5340
5341         DEBUGFUNC();
5342
5343         /* Find and probe all the matching PCI devices */
5344         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5345                 u32 val;
5346
5347                 /*
5348                  * These will never get freed due to errors, this allows us to
5349                  * perform SPI EEPROM programming from U-boot, for example.
5350                  */
5351                 struct eth_device *nic = malloc(sizeof(*nic));
5352                 struct e1000_hw *hw = malloc(sizeof(*hw));
5353                 if (!nic || !hw) {
5354                         printf("e1000#%u: Out of Memory!\n", i);
5355                         free(nic);
5356                         free(hw);
5357                         continue;
5358                 }
5359
5360                 /* Make sure all of the fields are initially zeroed */
5361                 memset(nic, 0, sizeof(*nic));
5362                 memset(hw, 0, sizeof(*hw));
5363
5364                 /* Assign the passed-in values */
5365                 hw->cardnum = i;
5366                 hw->pdev = devno;
5367                 hw->nic = nic;
5368                 nic->priv = hw;
5369
5370                 /* Generate a card name */
5371                 sprintf(nic->name, "e1000#%u", hw->cardnum);
5372
5373                 /* Print a debug message with the IO base address */
5374                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5375                 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5376
5377                 /* Try to enable I/O accesses and bus-mastering */
5378                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5379                 pci_write_config_dword(devno, PCI_COMMAND, val);
5380
5381                 /* Make sure it worked */
5382                 pci_read_config_dword(devno, PCI_COMMAND, &val);
5383                 if (!(val & PCI_COMMAND_MEMORY)) {
5384                         E1000_ERR(nic, "Can't enable I/O memory\n");
5385                         continue;
5386                 }
5387                 if (!(val & PCI_COMMAND_MASTER)) {
5388                         E1000_ERR(nic, "Can't enable bus-mastering\n");
5389                         continue;
5390                 }
5391
5392                 /* Are these variables needed? */
5393                 hw->fc = e1000_fc_default;
5394                 hw->original_fc = e1000_fc_default;
5395                 hw->autoneg_failed = 0;
5396                 hw->autoneg = 1;
5397                 hw->get_link_status = true;
5398 #ifndef CONFIG_E1000_NO_NVM
5399                 hw->eeprom_semaphore_present = true;
5400 #endif
5401                 hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5402                                                         PCI_REGION_MEM);
5403                 hw->mac_type = e1000_undefined;
5404
5405                 /* MAC and Phy settings */
5406                 if (e1000_sw_init(nic) < 0) {
5407                         E1000_ERR(nic, "Software init failed\n");
5408                         continue;
5409                 }
5410                 if (e1000_check_phy_reset_block(hw))
5411                         E1000_ERR(nic, "PHY Reset is blocked!\n");
5412
5413                 /* Basic init was OK, reset the hardware and allow SPI access */
5414                 e1000_reset_hw(hw);
5415                 list_add_tail(&hw->list_node, &e1000_hw_list);
5416
5417 #ifndef CONFIG_E1000_NO_NVM
5418                 /* Validate the EEPROM and get chipset information */
5419 #if !defined(CONFIG_MVBC_1G)
5420                 if (e1000_init_eeprom_params(hw)) {
5421                         E1000_ERR(nic, "EEPROM is invalid!\n");
5422                         continue;
5423                 }
5424                 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5425                     e1000_validate_eeprom_checksum(hw))
5426                         continue;
5427 #endif
5428                 e1000_read_mac_addr(nic);
5429 #endif
5430                 e1000_get_bus_type(hw);
5431
5432 #ifndef CONFIG_E1000_NO_NVM
5433                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5434                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5435                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5436 #else
5437                 memset(nic->enetaddr, 0, 6);
5438                 printf("e1000: no NVM\n");
5439 #endif
5440
5441                 /* Set up the function pointers and register the device */
5442                 nic->init = e1000_init;
5443                 nic->recv = e1000_poll;
5444                 nic->send = e1000_transmit;
5445                 nic->halt = e1000_disable;
5446                 eth_register(nic);
5447         }
5448
5449         return i;
5450 }
5451
5452 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5453 {
5454         struct e1000_hw *hw;
5455
5456         list_for_each_entry(hw, &e1000_hw_list, list_node)
5457                 if (hw->cardnum == cardnum)
5458                         return hw;
5459
5460         return NULL;
5461 }
5462
5463 #ifdef CONFIG_CMD_E1000
5464 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5465                 int argc, char * const argv[])
5466 {
5467         struct e1000_hw *hw;
5468
5469         if (argc < 3) {
5470                 cmd_usage(cmdtp);
5471                 return 1;
5472         }
5473
5474         /* Make sure we can find the requested e1000 card */
5475         hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5476         if (!hw) {
5477                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5478                 return 1;
5479         }
5480
5481         if (!strcmp(argv[2], "print-mac-address")) {
5482                 unsigned char *mac = hw->nic->enetaddr;
5483                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5484                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5485                 return 0;
5486         }
5487
5488 #ifdef CONFIG_E1000_SPI
5489         /* Handle the "SPI" subcommand */
5490         if (!strcmp(argv[2], "spi"))
5491                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5492 #endif
5493
5494         cmd_usage(cmdtp);
5495         return 1;
5496 }
5497
5498 U_BOOT_CMD(
5499         e1000, 7, 0, do_e1000,
5500         "Intel e1000 controller management",
5501         /*  */"<card#> print-mac-address\n"
5502 #ifdef CONFIG_E1000_SPI
5503         "e1000 <card#> spi show [<offset> [<length>]]\n"
5504         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5505         "e1000 <card#> spi program <addr> <offset> <length>\n"
5506         "e1000 <card#> spi checksum [update]\n"
5507 #endif
5508         "       - Manage the Intel E1000 PCI device"
5509 );
5510 #endif /* not CONFIG_CMD_E1000 */