drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms of the GNU General Public License as published by the Free
  14   Software Foundation; either version 2 of the License, or (at your option)
  15   any later version.
  16
  17   This program is distributed in the hope that it will be useful, but WITHOUT
  18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20   more details.
  21
  22   You should have received a copy of the GNU General Public License along with
  23   this program; if not, write to the Free Software Foundation, Inc., 59
  24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25
  26   The full GNU General Public License is included in this distribution in the
  27   file called LICENSE.
  28
  29   Contact Information:
  30   Linux NICS <linux.nics@intel.com>
  31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32
  33 *******************************************************************************/
  34 /*
  35  *  Copyright (C) Archway Digital Solutions.
  36  *
  37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  38  *  2/9/2002
  39  *
  40  *  Copyright (C) Linux Networx.
  41  *  Massive upgrade to work with the new intel gigabit NICs.
  42  *  <ebiederman at lnxi dot com>
  43  */
  44
  45 #include "e1000.h"
  46
  47 #define TOUT_LOOP   100000
  48
  49 #undef  virt_to_bus
  50 #define virt_to_bus(x)  ((unsigned long)x)
  51 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  52 #define mdelay(n)       udelay((n)*1000)
  53
  54 #define E1000_DEFAULT_PBA    0x000a0026
  55
  56 /* NIC specific static variables go here */
  57
  58 static char tx_pool[128 + 16];
  59 static char rx_pool[128 + 16];
  60 static char packet[2096];
  61
  62 static struct e1000_tx_desc *tx_base;
  63 static struct e1000_rx_desc *rx_base;
  64
  65 static int tx_tail;
  66 static int rx_tail, rx_last;
  67
  68 static struct pci_device_id supported[] = {
  69         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  72         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  85         /* E1000 PCIe card */
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  87         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
 103         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
 104         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
 105         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
 106         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
 107         {}
 108 };
 109
 110 /* Function forward declarations */
 111 static int e1000_setup_link(struct eth_device *nic);
 112 static int e1000_setup_fiber_link(struct eth_device *nic);
 113 static int e1000_setup_copper_link(struct eth_device *nic);
 114 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 115 static void e1000_config_collision_dist(struct e1000_hw *hw);
 116 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 117 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 118 static int e1000_check_for_link(struct eth_device *nic);
 119 static int e1000_wait_autoneg(struct e1000_hw *hw);
 120 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 121                                        uint16_t * duplex);
 122 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 123                               uint16_t * phy_data);
 124 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 125                                uint16_t phy_data);
 126 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 127 static int e1000_phy_reset(struct e1000_hw *hw);
 128 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 129 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 130                 uint16_t words,
 131                 uint16_t *data);
 132 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 133 static void e1000_set_media_type(struct e1000_hw *hw);
 134
 135 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 136 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 137 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
 138 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
 139 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
 140                         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
 141 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
 142         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
 143 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
 144
 145 #ifndef CONFIG_AP1000 /* remove for warnings */
 146 /******************************************************************************
 147  * Raises the EEPROM's clock input.
 148  *
 149  * hw - Struct containing variables accessed by shared code
 150  * eecd - EECD's current value
 151  *****************************************************************************/
 152 static void
 153 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 154 {
 155         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 156          * wait 50 microseconds.
 157          */
 158         *eecd = *eecd | E1000_EECD_SK;
 159         E1000_WRITE_REG(hw, EECD, *eecd);
 160         E1000_WRITE_FLUSH(hw);
 161         udelay(50);
 162 }
 163
 164 /******************************************************************************
 165  * Lowers the EEPROM's clock input.
 166  *
 167  * hw - Struct containing variables accessed by shared code
 168  * eecd - EECD's current value
 169  *****************************************************************************/
 170 static void
 171 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 172 {
 173         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 174          * wait 50 microseconds.
 175          */
 176         *eecd = *eecd & ~E1000_EECD_SK;
 177         E1000_WRITE_REG(hw, EECD, *eecd);
 178         E1000_WRITE_FLUSH(hw);
 179         udelay(50);
 180 }
 181
 182 /******************************************************************************
 183  * Shift data bits out to the EEPROM.
 184  *
 185  * hw - Struct containing variables accessed by shared code
 186  * data - data to send to the EEPROM
 187  * count - number of bits to shift out
 188  *****************************************************************************/
 189 static void
 190 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 191 {
 192         uint32_t eecd;
 193         uint32_t mask;
 194
 195         /* We need to shift "count" bits out to the EEPROM. So, value in the
 196          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 197          * In order to do this, "data" must be broken down into bits.
 198          */
 199         mask = 0x01 << (count - 1);
 200         eecd = E1000_READ_REG(hw, EECD);
 201         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 202         do {
 203                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 204                  * and then raising and then lowering the clock (the SK bit controls
 205                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 206                  * by setting "DI" to "0" and then raising and then lowering the clock.
 207                  */
 208                 eecd &= ~E1000_EECD_DI;
 209
 210                 if (data & mask)
 211                         eecd |= E1000_EECD_DI;
 212
 213                 E1000_WRITE_REG(hw, EECD, eecd);
 214                 E1000_WRITE_FLUSH(hw);
 215
 216                 udelay(50);
 217
 218                 e1000_raise_ee_clk(hw, &eecd);
 219                 e1000_lower_ee_clk(hw, &eecd);
 220
 221                 mask = mask >> 1;
 222
 223         } while (mask);
 224
 225         /* We leave the "DI" bit set to "0" when we leave this routine. */
 226         eecd &= ~E1000_EECD_DI;
 227         E1000_WRITE_REG(hw, EECD, eecd);
 228 }
 229
 230 /******************************************************************************
 231  * Shift data bits in from the EEPROM
 232  *
 233  * hw - Struct containing variables accessed by shared code
 234  *****************************************************************************/
 235 static uint16_t
 236 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 237 {
 238         uint32_t eecd;
 239         uint32_t i;
 240         uint16_t data;
 241
 242         /* In order to read a register from the EEPROM, we need to shift 'count'
 243          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 244          * input to the EEPROM (setting the SK bit), and then reading the
 245          * value of the "DO" bit.  During this "shifting in" process the
 246          * "DI" bit should always be clear.
 247          */
 248
 249         eecd = E1000_READ_REG(hw, EECD);
 250
 251         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 252         data = 0;
 253
 254         for (i = 0; i < count; i++) {
 255                 data = data << 1;
 256                 e1000_raise_ee_clk(hw, &eecd);
 257
 258                 eecd = E1000_READ_REG(hw, EECD);
 259
 260                 eecd &= ~(E1000_EECD_DI);
 261                 if (eecd & E1000_EECD_DO)
 262                         data |= 1;
 263
 264                 e1000_lower_ee_clk(hw, &eecd);
 265         }
 266
 267         return data;
 268 }
 269
 270 /******************************************************************************
 271  * Returns EEPROM to a "standby" state
 272  *
 273  * hw - Struct containing variables accessed by shared code
 274  *****************************************************************************/
 275 static void
 276 e1000_standby_eeprom(struct e1000_hw *hw)
 277 {
 278         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 279         uint32_t eecd;
 280
 281         eecd = E1000_READ_REG(hw, EECD);
 282
 283         if (eeprom->type == e1000_eeprom_microwire) {
 284                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 285                 E1000_WRITE_REG(hw, EECD, eecd);
 286                 E1000_WRITE_FLUSH(hw);
 287                 udelay(eeprom->delay_usec);
 288
 289                 /* Clock high */
 290                 eecd |= E1000_EECD_SK;
 291                 E1000_WRITE_REG(hw, EECD, eecd);
 292                 E1000_WRITE_FLUSH(hw);
 293                 udelay(eeprom->delay_usec);
 294
 295                 /* Select EEPROM */
 296                 eecd |= E1000_EECD_CS;
 297                 E1000_WRITE_REG(hw, EECD, eecd);
 298                 E1000_WRITE_FLUSH(hw);
 299                 udelay(eeprom->delay_usec);
 300
 301                 /* Clock low */
 302                 eecd &= ~E1000_EECD_SK;
 303                 E1000_WRITE_REG(hw, EECD, eecd);
 304                 E1000_WRITE_FLUSH(hw);
 305                 udelay(eeprom->delay_usec);
 306         } else if (eeprom->type == e1000_eeprom_spi) {
 307                 /* Toggle CS to flush commands */
 308                 eecd |= E1000_EECD_CS;
 309                 E1000_WRITE_REG(hw, EECD, eecd);
 310                 E1000_WRITE_FLUSH(hw);
 311                 udelay(eeprom->delay_usec);
 312                 eecd &= ~E1000_EECD_CS;
 313                 E1000_WRITE_REG(hw, EECD, eecd);
 314                 E1000_WRITE_FLUSH(hw);
 315                 udelay(eeprom->delay_usec);
 316         }
 317 }
 318
 319 /***************************************************************************
 320 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 321 *
 322 * hw - Struct containing variables accessed by shared code
 323 ****************************************************************************/
 324 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 325 {
 326         uint32_t eecd = 0;
 327
 328         DEBUGFUNC();
 329
 330         if (hw->mac_type == e1000_ich8lan)
 331                 return FALSE;
 332
 333         if (hw->mac_type == e1000_82573) {
 334                 eecd = E1000_READ_REG(hw, EECD);
 335
 336                 /* Isolate bits 15 & 16 */
 337                 eecd = ((eecd >> 15) & 0x03);
 338
 339                 /* If both bits are set, device is Flash type */
 340                 if (eecd == 0x03)
 341                         return FALSE;
 342         }
 343         return TRUE;
 344 }
 345
 346 /******************************************************************************
 347  * Prepares EEPROM for access
 348  *
 349  * hw - Struct containing variables accessed by shared code
 350  *
 351  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 352  * function should be called before issuing a command to the EEPROM.
 353  *****************************************************************************/
 354 static int32_t
 355 e1000_acquire_eeprom(struct e1000_hw *hw)
 356 {
 357         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 358         uint32_t eecd, i = 0;
 359
 360         DEBUGOUT();
 361
 362         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 363                 return -E1000_ERR_SWFW_SYNC;
 364         eecd = E1000_READ_REG(hw, EECD);
 365
 366         if (hw->mac_type != e1000_82573) {
 367                 /* Request EEPROM Access */
 368                 if (hw->mac_type > e1000_82544) {
 369                         eecd |= E1000_EECD_REQ;
 370                         E1000_WRITE_REG(hw, EECD, eecd);
 371                         eecd = E1000_READ_REG(hw, EECD);
 372                         while ((!(eecd & E1000_EECD_GNT)) &&
 373                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 374                                 i++;
 375                                 udelay(5);
 376                                 eecd = E1000_READ_REG(hw, EECD);
 377                         }
 378                         if (!(eecd & E1000_EECD_GNT)) {
 379                                 eecd &= ~E1000_EECD_REQ;
 380                                 E1000_WRITE_REG(hw, EECD, eecd);
 381                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 382                                 return -E1000_ERR_EEPROM;
 383                         }
 384                 }
 385         }
 386
 387         /* Setup EEPROM for Read/Write */
 388
 389         if (eeprom->type == e1000_eeprom_microwire) {
 390                 /* Clear SK and DI */
 391                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 392                 E1000_WRITE_REG(hw, EECD, eecd);
 393
 394                 /* Set CS */
 395                 eecd |= E1000_EECD_CS;
 396                 E1000_WRITE_REG(hw, EECD, eecd);
 397         } else if (eeprom->type == e1000_eeprom_spi) {
 398                 /* Clear SK and CS */
 399                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 400                 E1000_WRITE_REG(hw, EECD, eecd);
 401                 udelay(1);
 402         }
 403
 404         return E1000_SUCCESS;
 405 }
 406
 407 /******************************************************************************
 408  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 409  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 410  * registers must be mapped, or this will crash.
 411  *
 412  * hw - Struct containing variables accessed by shared code
 413  *****************************************************************************/
 414 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 415 {
 416         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 417         uint32_t eecd = E1000_READ_REG(hw, EECD);
 418         int32_t ret_val = E1000_SUCCESS;
 419         uint16_t eeprom_size;
 420
 421         DEBUGOUT();
 422
 423         switch (hw->mac_type) {
 424         case e1000_82542_rev2_0:
 425         case e1000_82542_rev2_1:
 426         case e1000_82543:
 427         case e1000_82544:
 428                 eeprom->type = e1000_eeprom_microwire;
 429                 eeprom->word_size = 64;
 430                 eeprom->opcode_bits = 3;
 431                 eeprom->address_bits = 6;
 432                 eeprom->delay_usec = 50;
 433                 eeprom->use_eerd = FALSE;
 434                 eeprom->use_eewr = FALSE;
 435         break;
 436         case e1000_82540:
 437         case e1000_82545:
 438         case e1000_82545_rev_3:
 439         case e1000_82546:
 440         case e1000_82546_rev_3:
 441                 eeprom->type = e1000_eeprom_microwire;
 442                 eeprom->opcode_bits = 3;
 443                 eeprom->delay_usec = 50;
 444                 if (eecd & E1000_EECD_SIZE) {
 445                         eeprom->word_size = 256;
 446                         eeprom->address_bits = 8;
 447                 } else {
 448                         eeprom->word_size = 64;
 449                         eeprom->address_bits = 6;
 450                 }
 451                 eeprom->use_eerd = FALSE;
 452                 eeprom->use_eewr = FALSE;
 453                 break;
 454         case e1000_82541:
 455         case e1000_82541_rev_2:
 456         case e1000_82547:
 457         case e1000_82547_rev_2:
 458                 if (eecd & E1000_EECD_TYPE) {
 459                         eeprom->type = e1000_eeprom_spi;
 460                         eeprom->opcode_bits = 8;
 461                         eeprom->delay_usec = 1;
 462                         if (eecd & E1000_EECD_ADDR_BITS) {
 463                                 eeprom->page_size = 32;
 464                                 eeprom->address_bits = 16;
 465                         } else {
 466                                 eeprom->page_size = 8;
 467                                 eeprom->address_bits = 8;
 468                         }
 469                 } else {
 470                         eeprom->type = e1000_eeprom_microwire;
 471                         eeprom->opcode_bits = 3;
 472                         eeprom->delay_usec = 50;
 473                         if (eecd & E1000_EECD_ADDR_BITS) {
 474                                 eeprom->word_size = 256;
 475                                 eeprom->address_bits = 8;
 476                         } else {
 477                                 eeprom->word_size = 64;
 478                                 eeprom->address_bits = 6;
 479                         }
 480                 }
 481                 eeprom->use_eerd = FALSE;
 482                 eeprom->use_eewr = FALSE;
 483                 break;
 484         case e1000_82571:
 485         case e1000_82572:
 486                 eeprom->type = e1000_eeprom_spi;
 487                 eeprom->opcode_bits = 8;
 488                 eeprom->delay_usec = 1;
 489                 if (eecd & E1000_EECD_ADDR_BITS) {
 490                         eeprom->page_size = 32;
 491                         eeprom->address_bits = 16;
 492                 } else {
 493                         eeprom->page_size = 8;
 494                         eeprom->address_bits = 8;
 495                 }
 496                 eeprom->use_eerd = FALSE;
 497                 eeprom->use_eewr = FALSE;
 498                 break;
 499         case e1000_82573:
 500                 eeprom->type = e1000_eeprom_spi;
 501                 eeprom->opcode_bits = 8;
 502                 eeprom->delay_usec = 1;
 503                 if (eecd & E1000_EECD_ADDR_BITS) {
 504                         eeprom->page_size = 32;
 505                         eeprom->address_bits = 16;
 506                 } else {
 507                         eeprom->page_size = 8;
 508                         eeprom->address_bits = 8;
 509                 }
 510                 eeprom->use_eerd = TRUE;
 511                 eeprom->use_eewr = TRUE;
 512                 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
 513                         eeprom->type = e1000_eeprom_flash;
 514                         eeprom->word_size = 2048;
 515
 516                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 517                  * Flash update issue on parts which use a FLASH for NVM. */
 518                         eecd &= ~E1000_EECD_AUPDEN;
 519                         E1000_WRITE_REG(hw, EECD, eecd);
 520                 }
 521                 break;
 522         case e1000_80003es2lan:
 523                 eeprom->type = e1000_eeprom_spi;
 524                 eeprom->opcode_bits = 8;
 525                 eeprom->delay_usec = 1;
 526                 if (eecd & E1000_EECD_ADDR_BITS) {
 527                         eeprom->page_size = 32;
 528                         eeprom->address_bits = 16;
 529                 } else {
 530                         eeprom->page_size = 8;
 531                         eeprom->address_bits = 8;
 532                 }
 533                 eeprom->use_eerd = TRUE;
 534                 eeprom->use_eewr = FALSE;
 535                 break;
 536
 537         /* ich8lan does not support currently. if needed, please
 538          * add corresponding code and functions.
 539          */
 540 #if 0
 541         case e1000_ich8lan:
 542                 {
 543                 int32_t  i = 0;
 544
 545                 eeprom->type = e1000_eeprom_ich8;
 546                 eeprom->use_eerd = FALSE;
 547                 eeprom->use_eewr = FALSE;
 548                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 549                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 550                                 ICH_FLASH_GFPREG);
 551                 /* Zero the shadow RAM structure. But don't load it from NVM
 552                  * so as to save time for driver init */
 553                 if (hw->eeprom_shadow_ram != NULL) {
 554                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 555                                 hw->eeprom_shadow_ram[i].modified = FALSE;
 556                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 557                         }
 558                 }
 559
 560                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 561                                 ICH_FLASH_SECTOR_SIZE;
 562
 563                 hw->flash_bank_size = ((flash_size >> 16)
 564                                 & ICH_GFPREG_BASE_MASK) + 1;
 565                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 566
 567                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 568
 569                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 570                 break;
 571                 }
 572 #endif
 573         default:
 574                 break;
 575         }
 576
 577         if (eeprom->type == e1000_eeprom_spi) {
 578                 /* eeprom_size will be an enum [0..8] that maps
 579                  * to eeprom sizes 128B to
 580                  * 32KB (incremented by powers of 2).
 581                  */
 582                 if (hw->mac_type <= e1000_82547_rev_2) {
 583                         /* Set to default value for initial eeprom read. */
 584                         eeprom->word_size = 64;
 585                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 586                                         &eeprom_size);
 587                         if (ret_val)
 588                                 return ret_val;
 589                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 590                                 >> EEPROM_SIZE_SHIFT;
 591                         /* 256B eeprom size was not supported in earlier
 592                          * hardware, so we bump eeprom_size up one to
 593                          * ensure that "1" (which maps to 256B) is never
 594                          * the result used in the shifting logic below. */
 595                         if (eeprom_size)
 596                                 eeprom_size++;
 597                 } else {
 598                         eeprom_size = (uint16_t)((eecd &
 599                                 E1000_EECD_SIZE_EX_MASK) >>
 600                                 E1000_EECD_SIZE_EX_SHIFT);
 601                 }
 602
 603                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 604         }
 605         return ret_val;
 606 }
 607
 608 /******************************************************************************
 609  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 610  *
 611  * hw - Struct containing variables accessed by shared code
 612  *****************************************************************************/
 613 static int32_t
 614 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 615 {
 616         uint32_t attempts = 100000;
 617         uint32_t i, reg = 0;
 618         int32_t done = E1000_ERR_EEPROM;
 619
 620         for (i = 0; i < attempts; i++) {
 621                 if (eerd == E1000_EEPROM_POLL_READ)
 622                         reg = E1000_READ_REG(hw, EERD);
 623                 else
 624                         reg = E1000_READ_REG(hw, EEWR);
 625
 626                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 627                         done = E1000_SUCCESS;
 628                         break;
 629                 }
 630                 udelay(5);
 631         }
 632
 633         return done;
 634 }
 635
 636 /******************************************************************************
 637  * Reads a 16 bit word from the EEPROM using the EERD register.
 638  *
 639  * hw - Struct containing variables accessed by shared code
 640  * offset - offset of  word in the EEPROM to read
 641  * data - word read from the EEPROM
 642  * words - number of words to read
 643  *****************************************************************************/
 644 static int32_t
 645 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 646                         uint16_t offset,
 647                         uint16_t words,
 648                         uint16_t *data)
 649 {
 650         uint32_t i, eerd = 0;
 651         int32_t error = 0;
 652
 653         for (i = 0; i < words; i++) {
 654                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 655                         E1000_EEPROM_RW_REG_START;
 656
 657                 E1000_WRITE_REG(hw, EERD, eerd);
 658                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 659
 660                 if (error)
 661                         break;
 662                 data[i] = (E1000_READ_REG(hw, EERD) >>
 663                                 E1000_EEPROM_RW_REG_DATA);
 664
 665         }
 666
 667         return error;
 668 }
 669
 670 static void
 671 e1000_release_eeprom(struct e1000_hw *hw)
 672 {
 673         uint32_t eecd;
 674
 675         DEBUGFUNC();
 676
 677         eecd = E1000_READ_REG(hw, EECD);
 678
 679         if (hw->eeprom.type == e1000_eeprom_spi) {
 680                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 681                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 682
 683                 E1000_WRITE_REG(hw, EECD, eecd);
 684
 685                 udelay(hw->eeprom.delay_usec);
 686         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 687                 /* cleanup eeprom */
 688
 689                 /* CS on Microwire is active-high */
 690                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 691
 692                 E1000_WRITE_REG(hw, EECD, eecd);
 693
 694                 /* Rising edge of clock */
 695                 eecd |= E1000_EECD_SK;
 696                 E1000_WRITE_REG(hw, EECD, eecd);
 697                 E1000_WRITE_FLUSH(hw);
 698                 udelay(hw->eeprom.delay_usec);
 699
 700                 /* Falling edge of clock */
 701                 eecd &= ~E1000_EECD_SK;
 702                 E1000_WRITE_REG(hw, EECD, eecd);
 703                 E1000_WRITE_FLUSH(hw);
 704                 udelay(hw->eeprom.delay_usec);
 705         }
 706
 707         /* Stop requesting EEPROM access */
 708         if (hw->mac_type > e1000_82544) {
 709                 eecd &= ~E1000_EECD_REQ;
 710                 E1000_WRITE_REG(hw, EECD, eecd);
 711         }
 712 }
 713 /******************************************************************************
 714  * Reads a 16 bit word from the EEPROM.
 715  *
 716  * hw - Struct containing variables accessed by shared code
 717  *****************************************************************************/
 718 static int32_t
 719 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 720 {
 721         uint16_t retry_count = 0;
 722         uint8_t spi_stat_reg;
 723
 724         DEBUGFUNC();
 725
 726         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 727          * EEPROM will signal that the command has been completed by clearing
 728          * bit 0 of the internal status register.  If it's not cleared within
 729          * 5 milliseconds, then error out.
 730          */
 731         retry_count = 0;
 732         do {
 733                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 734                         hw->eeprom.opcode_bits);
 735                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 736                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 737                         break;
 738
 739                 udelay(5);
 740                 retry_count += 5;
 741
 742                 e1000_standby_eeprom(hw);
 743         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 744
 745         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 746          * only 0-5mSec on 5V devices)
 747          */
 748         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 749                 DEBUGOUT("SPI EEPROM Status error\n");
 750                 return -E1000_ERR_EEPROM;
 751         }
 752
 753         return E1000_SUCCESS;
 754 }
 755
 756 /******************************************************************************
 757  * Reads a 16 bit word from the EEPROM.
 758  *
 759  * hw - Struct containing variables accessed by shared code
 760  * offset - offset of  word in the EEPROM to read
 761  * data - word read from the EEPROM
 762  *****************************************************************************/
 763 static int32_t
 764 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 765                 uint16_t words, uint16_t *data)
 766 {
 767         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 768         uint32_t i = 0;
 769
 770         DEBUGFUNC();
 771
 772         /* If eeprom is not yet detected, do so now */
 773         if (eeprom->word_size == 0)
 774                 e1000_init_eeprom_params(hw);
 775
 776         /* A check for invalid values:  offset too large, too many words,
 777          * and not enough words.
 778          */
 779         if ((offset >= eeprom->word_size) ||
 780                 (words > eeprom->word_size - offset) ||
 781                 (words == 0)) {
 782                 DEBUGOUT("\"words\" parameter out of bounds."
 783                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 784                 return -E1000_ERR_EEPROM;
 785         }
 786
 787         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 788          * directly. In this case, we need to acquire the EEPROM so that
 789          * FW or other port software does not interrupt.
 790          */
 791         if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
 792                 hw->eeprom.use_eerd == FALSE) {
 793
 794                 /* Prepare the EEPROM for bit-bang reading */
 795                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 796                         return -E1000_ERR_EEPROM;
 797         }
 798
 799         /* Eerd register EEPROM access requires no eeprom aquire/release */
 800         if (eeprom->use_eerd == TRUE)
 801                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 802
 803         /* ich8lan does not support currently. if needed, please
 804          * add corresponding code and functions.
 805          */
 806 #if 0
 807         /* ICH EEPROM access is done via the ICH flash controller */
 808         if (eeprom->type == e1000_eeprom_ich8)
 809                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 810 #endif
 811         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 812          * acquired the EEPROM at this point, so any returns should relase it */
 813         if (eeprom->type == e1000_eeprom_spi) {
 814                 uint16_t word_in;
 815                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 816
 817                 if (e1000_spi_eeprom_ready(hw)) {
 818                         e1000_release_eeprom(hw);
 819                         return -E1000_ERR_EEPROM;
 820                 }
 821
 822                 e1000_standby_eeprom(hw);
 823
 824                 /* Some SPI eeproms use the 8th address bit embedded in
 825                  * the opcode */
 826                 if ((eeprom->address_bits == 8) && (offset >= 128))
 827                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 828
 829                 /* Send the READ command (opcode + addr)  */
 830                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 831                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 832                                 eeprom->address_bits);
 833
 834                 /* Read the data.  The address of the eeprom internally
 835                  * increments with each byte (spi) being read, saving on the
 836                  * overhead of eeprom setup and tear-down.  The address
 837                  * counter will roll over if reading beyond the size of
 838                  * the eeprom, thus allowing the entire memory to be read
 839                  * starting from any offset. */
 840                 for (i = 0; i < words; i++) {
 841                         word_in = e1000_shift_in_ee_bits(hw, 16);
 842                         data[i] = (word_in >> 8) | (word_in << 8);
 843                 }
 844         } else if (eeprom->type == e1000_eeprom_microwire) {
 845                 for (i = 0; i < words; i++) {
 846                         /* Send the READ command (opcode + addr)  */
 847                         e1000_shift_out_ee_bits(hw,
 848                                 EEPROM_READ_OPCODE_MICROWIRE,
 849                                 eeprom->opcode_bits);
 850                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 851                                 eeprom->address_bits);
 852
 853                         /* Read the data.  For microwire, each word requires
 854                          * the overhead of eeprom setup and tear-down. */
 855                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 856                         e1000_standby_eeprom(hw);
 857                 }
 858         }
 859
 860         /* End this read operation */
 861         e1000_release_eeprom(hw);
 862
 863         return E1000_SUCCESS;
 864 }
 865
 866 /******************************************************************************
 867  * Verifies that the EEPROM has a valid checksum
 868  *
 869  * hw - Struct containing variables accessed by shared code
 870  *
 871  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 872  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 873  * valid.
 874  *****************************************************************************/
 875 static int
 876 e1000_validate_eeprom_checksum(struct eth_device *nic)
 877 {
 878         struct e1000_hw *hw = nic->priv;
 879         uint16_t checksum = 0;
 880         uint16_t i, eeprom_data;
 881
 882         DEBUGFUNC();
 883
 884         for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
 885                 if (e1000_read_eeprom(hw, i, 1,  &eeprom_data) < 0) {
 886                         DEBUGOUT("EEPROM Read Error\n");
 887                         return -E1000_ERR_EEPROM;
 888                 }
 889                 checksum += eeprom_data;
 890         }
 891
 892         if (checksum == (uint16_t) EEPROM_SUM) {
 893                 return 0;
 894         } else {
 895                 DEBUGOUT("EEPROM Checksum Invalid\n");
 896                 return -E1000_ERR_EEPROM;
 897         }
 898 }
 899 #endif /* #ifndef CONFIG_AP1000 */
 900
 901 /***************************************************************************
 902  *
 903  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 904  *
 905  * hw: Struct containing variables accessed by shared code
 906  *
 907  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 908  *            E1000_SUCCESS at any other case.
 909  *
 910  ***************************************************************************/
 911 static int32_t
 912 e1000_get_software_semaphore(struct e1000_hw *hw)
 913 {
 914          int32_t timeout = hw->eeprom.word_size + 1;
 915          uint32_t swsm;
 916
 917         DEBUGFUNC();
 918
 919         if (hw->mac_type != e1000_80003es2lan)
 920                 return E1000_SUCCESS;
 921
 922         while (timeout) {
 923                 swsm = E1000_READ_REG(hw, SWSM);
 924                 /* If SMBI bit cleared, it is now set and we hold
 925                  * the semaphore */
 926                 if (!(swsm & E1000_SWSM_SMBI))
 927                         break;
 928                 mdelay(1);
 929                 timeout--;
 930         }
 931
 932         if (!timeout) {
 933                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 934                 return -E1000_ERR_RESET;
 935         }
 936
 937         return E1000_SUCCESS;
 938 }
 939
 940 /***************************************************************************
 941  * This function clears HW semaphore bits.
 942  *
 943  * hw: Struct containing variables accessed by shared code
 944  *
 945  * returns: - None.
 946  *
 947  ***************************************************************************/
 948 static void
 949 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 950 {
 951          uint32_t swsm;
 952
 953         DEBUGFUNC();
 954
 955         if (!hw->eeprom_semaphore_present)
 956                 return;
 957
 958         swsm = E1000_READ_REG(hw, SWSM);
 959         if (hw->mac_type == e1000_80003es2lan) {
 960                 /* Release both semaphores. */
 961                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 962         } else
 963                 swsm &= ~(E1000_SWSM_SWESMBI);
 964         E1000_WRITE_REG(hw, SWSM, swsm);
 965 }
 966
 967 /***************************************************************************
 968  *
 969  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
 970  * adapter or Eeprom access.
 971  *
 972  * hw: Struct containing variables accessed by shared code
 973  *
 974  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
 975  *            E1000_SUCCESS at any other case.
 976  *
 977  ***************************************************************************/
 978 static int32_t
 979 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
 980 {
 981         int32_t timeout;
 982         uint32_t swsm;
 983
 984         DEBUGFUNC();
 985
 986         if (!hw->eeprom_semaphore_present)
 987                 return E1000_SUCCESS;
 988
 989         if (hw->mac_type == e1000_80003es2lan) {
 990                 /* Get the SW semaphore. */
 991                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
 992                         return -E1000_ERR_EEPROM;
 993         }
 994
 995         /* Get the FW semaphore. */
 996         timeout = hw->eeprom.word_size + 1;
 997         while (timeout) {
 998                 swsm = E1000_READ_REG(hw, SWSM);
 999                 swsm |= E1000_SWSM_SWESMBI;
1000                 E1000_WRITE_REG(hw, SWSM, swsm);
1001                 /* if we managed to set the bit we got the semaphore. */
1002                 swsm = E1000_READ_REG(hw, SWSM);
1003                 if (swsm & E1000_SWSM_SWESMBI)
1004                         break;
1005
1006                 udelay(50);
1007                 timeout--;
1008         }
1009
1010         if (!timeout) {
1011                 /* Release semaphores */
1012                 e1000_put_hw_eeprom_semaphore(hw);
1013                 DEBUGOUT("Driver can't access the Eeprom - "
1014                                 "SWESMBI bit is set.\n");
1015                 return -E1000_ERR_EEPROM;
1016         }
1017
1018         return E1000_SUCCESS;
1019 }
1020
1021 static int32_t
1022 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1023 {
1024         uint32_t swfw_sync = 0;
1025         uint32_t swmask = mask;
1026         uint32_t fwmask = mask << 16;
1027         int32_t timeout = 200;
1028
1029         DEBUGFUNC();
1030         while (timeout) {
1031                 if (e1000_get_hw_eeprom_semaphore(hw))
1032                         return -E1000_ERR_SWFW_SYNC;
1033
1034                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1035                 if (!(swfw_sync & (fwmask | swmask)))
1036                         break;
1037
1038                 /* firmware currently using resource (fwmask) */
1039                 /* or other software thread currently using resource (swmask) */
1040                 e1000_put_hw_eeprom_semaphore(hw);
1041                 mdelay(5);
1042                 timeout--;
1043         }
1044
1045         if (!timeout) {
1046                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1047                 return -E1000_ERR_SWFW_SYNC;
1048         }
1049
1050         swfw_sync |= swmask;
1051         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1052
1053         e1000_put_hw_eeprom_semaphore(hw);
1054         return E1000_SUCCESS;
1055 }
1056
1057 /******************************************************************************
1058  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1059  * second function of dual function devices
1060  *
1061  * nic - Struct containing variables accessed by shared code
1062  *****************************************************************************/
1063 static int
1064 e1000_read_mac_addr(struct eth_device *nic)
1065 {
1066 #ifndef CONFIG_AP1000
1067         struct e1000_hw *hw = nic->priv;
1068         uint16_t offset;
1069         uint16_t eeprom_data;
1070         int i;
1071
1072         DEBUGFUNC();
1073
1074         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1075                 offset = i >> 1;
1076                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1077                         DEBUGOUT("EEPROM Read Error\n");
1078                         return -E1000_ERR_EEPROM;
1079                 }
1080                 nic->enetaddr[i] = eeprom_data & 0xff;
1081                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1082         }
1083         if ((hw->mac_type == e1000_82546) &&
1084             (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
1085                 /* Invert the last bit if this is the second device */
1086                 nic->enetaddr[5] += 1;
1087         }
1088 #ifdef CONFIG_E1000_FALLBACK_MAC
1089         if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
1090                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1091
1092                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1093         }
1094 #endif
1095 #else
1096         /*
1097          * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1098          * environment variables.  Currently this does not support the addition
1099          * of a PMC e1000 card, which is certainly a possibility, so this should
1100          * be updated to properly use the env variable only for the onboard e1000
1101          */
1102
1103         int ii;
1104         char *s, *e;
1105
1106         DEBUGFUNC();
1107
1108         s = getenv ("ethaddr");
1109         if (s == NULL) {
1110                 return -E1000_ERR_EEPROM;
1111         } else {
1112                 for(ii = 0; ii < 6; ii++) {
1113                         nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1114                         if (s){
1115                                 s = (*e) ? e + 1 : e;
1116                         }
1117                 }
1118         }
1119 #endif
1120         return 0;
1121 }
1122
1123 /******************************************************************************
1124  * Initializes receive address filters.
1125  *
1126  * hw - Struct containing variables accessed by shared code
1127  *
1128  * Places the MAC address in receive address register 0 and clears the rest
1129  * of the receive addresss registers. Clears the multicast table. Assumes
1130  * the receiver is in reset when the routine is called.
1131  *****************************************************************************/
1132 static void
1133 e1000_init_rx_addrs(struct eth_device *nic)
1134 {
1135         struct e1000_hw *hw = nic->priv;
1136         uint32_t i;
1137         uint32_t addr_low;
1138         uint32_t addr_high;
1139
1140         DEBUGFUNC();
1141
1142         /* Setup the receive address. */
1143         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1144         addr_low = (nic->enetaddr[0] |
1145                     (nic->enetaddr[1] << 8) |
1146                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1147
1148         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1149
1150         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1151         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1152
1153         /* Zero out the other 15 receive addresses. */
1154         DEBUGOUT("Clearing RAR[1-15]\n");
1155         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1156                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1157                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1158         }
1159 }
1160
1161 /******************************************************************************
1162  * Clears the VLAN filer table
1163  *
1164  * hw - Struct containing variables accessed by shared code
1165  *****************************************************************************/
1166 static void
1167 e1000_clear_vfta(struct e1000_hw *hw)
1168 {
1169         uint32_t offset;
1170
1171         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1172                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1173 }
1174
1175 /******************************************************************************
1176  * Set the mac type member in the hw struct.
1177  *
1178  * hw - Struct containing variables accessed by shared code
1179  *****************************************************************************/
1180 int32_t
1181 e1000_set_mac_type(struct e1000_hw *hw)
1182 {
1183         DEBUGFUNC();
1184
1185         switch (hw->device_id) {
1186         case E1000_DEV_ID_82542:
1187                 switch (hw->revision_id) {
1188                 case E1000_82542_2_0_REV_ID:
1189                         hw->mac_type = e1000_82542_rev2_0;
1190                         break;
1191                 case E1000_82542_2_1_REV_ID:
1192                         hw->mac_type = e1000_82542_rev2_1;
1193                         break;
1194                 default:
1195                         /* Invalid 82542 revision ID */
1196                         return -E1000_ERR_MAC_TYPE;
1197                 }
1198                 break;
1199         case E1000_DEV_ID_82543GC_FIBER:
1200         case E1000_DEV_ID_82543GC_COPPER:
1201                 hw->mac_type = e1000_82543;
1202                 break;
1203         case E1000_DEV_ID_82544EI_COPPER:
1204         case E1000_DEV_ID_82544EI_FIBER:
1205         case E1000_DEV_ID_82544GC_COPPER:
1206         case E1000_DEV_ID_82544GC_LOM:
1207                 hw->mac_type = e1000_82544;
1208                 break;
1209         case E1000_DEV_ID_82540EM:
1210         case E1000_DEV_ID_82540EM_LOM:
1211         case E1000_DEV_ID_82540EP:
1212         case E1000_DEV_ID_82540EP_LOM:
1213         case E1000_DEV_ID_82540EP_LP:
1214                 hw->mac_type = e1000_82540;
1215                 break;
1216         case E1000_DEV_ID_82545EM_COPPER:
1217         case E1000_DEV_ID_82545EM_FIBER:
1218                 hw->mac_type = e1000_82545;
1219                 break;
1220         case E1000_DEV_ID_82545GM_COPPER:
1221         case E1000_DEV_ID_82545GM_FIBER:
1222         case E1000_DEV_ID_82545GM_SERDES:
1223                 hw->mac_type = e1000_82545_rev_3;
1224                 break;
1225         case E1000_DEV_ID_82546EB_COPPER:
1226         case E1000_DEV_ID_82546EB_FIBER:
1227         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1228                 hw->mac_type = e1000_82546;
1229                 break;
1230         case E1000_DEV_ID_82546GB_COPPER:
1231         case E1000_DEV_ID_82546GB_FIBER:
1232         case E1000_DEV_ID_82546GB_SERDES:
1233         case E1000_DEV_ID_82546GB_PCIE:
1234         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1235         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1236                 hw->mac_type = e1000_82546_rev_3;
1237                 break;
1238         case E1000_DEV_ID_82541EI:
1239         case E1000_DEV_ID_82541EI_MOBILE:
1240         case E1000_DEV_ID_82541ER_LOM:
1241                 hw->mac_type = e1000_82541;
1242                 break;
1243         case E1000_DEV_ID_82541ER:
1244         case E1000_DEV_ID_82541GI:
1245         case E1000_DEV_ID_82541GI_LF:
1246         case E1000_DEV_ID_82541GI_MOBILE:
1247                 hw->mac_type = e1000_82541_rev_2;
1248                 break;
1249         case E1000_DEV_ID_82547EI:
1250         case E1000_DEV_ID_82547EI_MOBILE:
1251                 hw->mac_type = e1000_82547;
1252                 break;
1253         case E1000_DEV_ID_82547GI:
1254                 hw->mac_type = e1000_82547_rev_2;
1255                 break;
1256         case E1000_DEV_ID_82571EB_COPPER:
1257         case E1000_DEV_ID_82571EB_FIBER:
1258         case E1000_DEV_ID_82571EB_SERDES:
1259         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1260         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1261         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1262         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1263         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1264         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1265                 hw->mac_type = e1000_82571;
1266                 break;
1267         case E1000_DEV_ID_82572EI_COPPER:
1268         case E1000_DEV_ID_82572EI_FIBER:
1269         case E1000_DEV_ID_82572EI_SERDES:
1270         case E1000_DEV_ID_82572EI:
1271                 hw->mac_type = e1000_82572;
1272                 break;
1273         case E1000_DEV_ID_82573E:
1274         case E1000_DEV_ID_82573E_IAMT:
1275         case E1000_DEV_ID_82573L:
1276                 hw->mac_type = e1000_82573;
1277                 break;
1278         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1279         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1280         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1281         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1282                 hw->mac_type = e1000_80003es2lan;
1283                 break;
1284         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1285         case E1000_DEV_ID_ICH8_IGP_AMT:
1286         case E1000_DEV_ID_ICH8_IGP_C:
1287         case E1000_DEV_ID_ICH8_IFE:
1288         case E1000_DEV_ID_ICH8_IFE_GT:
1289         case E1000_DEV_ID_ICH8_IFE_G:
1290         case E1000_DEV_ID_ICH8_IGP_M:
1291                 hw->mac_type = e1000_ich8lan;
1292                 break;
1293         default:
1294                 /* Should never have loaded on this device */
1295                 return -E1000_ERR_MAC_TYPE;
1296         }
1297         return E1000_SUCCESS;
1298 }
1299
1300 /******************************************************************************
1301  * Reset the transmit and receive units; mask and clear all interrupts.
1302  *
1303  * hw - Struct containing variables accessed by shared code
1304  *****************************************************************************/
1305 void
1306 e1000_reset_hw(struct e1000_hw *hw)
1307 {
1308         uint32_t ctrl;
1309         uint32_t ctrl_ext;
1310         uint32_t icr;
1311         uint32_t manc;
1312
1313         DEBUGFUNC();
1314
1315         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1316         if (hw->mac_type == e1000_82542_rev2_0) {
1317                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1318                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1319                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1320         }
1321
1322         /* Clear interrupt mask to stop board from generating interrupts */
1323         DEBUGOUT("Masking off all interrupts\n");
1324         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1325
1326         /* Disable the Transmit and Receive units.  Then delay to allow
1327          * any pending transactions to complete before we hit the MAC with
1328          * the global reset.
1329          */
1330         E1000_WRITE_REG(hw, RCTL, 0);
1331         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1332         E1000_WRITE_FLUSH(hw);
1333
1334         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1335         hw->tbi_compatibility_on = FALSE;
1336
1337         /* Delay to allow any outstanding PCI transactions to complete before
1338          * resetting the device
1339          */
1340         mdelay(10);
1341
1342         /* Issue a global reset to the MAC.  This will reset the chip's
1343          * transmit, receive, DMA, and link units.  It will not effect
1344          * the current PCI configuration.  The global reset bit is self-
1345          * clearing, and should clear within a microsecond.
1346          */
1347         DEBUGOUT("Issuing a global reset to MAC\n");
1348         ctrl = E1000_READ_REG(hw, CTRL);
1349
1350         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1351
1352         /* Force a reload from the EEPROM if necessary */
1353         if (hw->mac_type < e1000_82540) {
1354                 /* Wait for reset to complete */
1355                 udelay(10);
1356                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1357                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1358                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1359                 E1000_WRITE_FLUSH(hw);
1360                 /* Wait for EEPROM reload */
1361                 mdelay(2);
1362         } else {
1363                 /* Wait for EEPROM reload (it happens automatically) */
1364                 mdelay(4);
1365                 /* Dissable HW ARPs on ASF enabled adapters */
1366                 manc = E1000_READ_REG(hw, MANC);
1367                 manc &= ~(E1000_MANC_ARP_EN);
1368                 E1000_WRITE_REG(hw, MANC, manc);
1369         }
1370
1371         /* Clear interrupt mask to stop board from generating interrupts */
1372         DEBUGOUT("Masking off all interrupts\n");
1373         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1374
1375         /* Clear any pending interrupt events. */
1376         icr = E1000_READ_REG(hw, ICR);
1377
1378         /* If MWI was previously enabled, reenable it. */
1379         if (hw->mac_type == e1000_82542_rev2_0) {
1380                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1381         }
1382         E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
1383 }
1384
1385 /******************************************************************************
1386  *
1387  * Initialize a number of hardware-dependent bits
1388  *
1389  * hw: Struct containing variables accessed by shared code
1390  *
1391  * This function contains hardware limitation workarounds for PCI-E adapters
1392  *
1393  *****************************************************************************/
1394 static void
1395 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1396 {
1397         if ((hw->mac_type >= e1000_82571) &&
1398                         (!hw->initialize_hw_bits_disable)) {
1399                 /* Settings common to all PCI-express silicon */
1400                 uint32_t reg_ctrl, reg_ctrl_ext;
1401                 uint32_t reg_tarc0, reg_tarc1;
1402                 uint32_t reg_tctl;
1403                 uint32_t reg_txdctl, reg_txdctl1;
1404
1405                 /* link autonegotiation/sync workarounds */
1406                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1407                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1408
1409                 /* Enable not-done TX descriptor counting */
1410                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1411                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1412                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1413
1414                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1415                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1416                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1417
1418                 switch (hw->mac_type) {
1419                 case e1000_82571:
1420                 case e1000_82572:
1421                         /* Clear PHY TX compatible mode bits */
1422                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1423                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1424
1425                         /* link autonegotiation/sync workarounds */
1426                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1427
1428                         /* TX ring control fixes */
1429                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1430
1431                         /* Multiple read bit is reversed polarity */
1432                         reg_tctl = E1000_READ_REG(hw, TCTL);
1433                         if (reg_tctl & E1000_TCTL_MULR)
1434                                 reg_tarc1 &= ~(1 << 28);
1435                         else
1436                                 reg_tarc1 |= (1 << 28);
1437
1438                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1439                         break;
1440                 case e1000_82573:
1441                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1442                         reg_ctrl_ext &= ~(1 << 23);
1443                         reg_ctrl_ext |= (1 << 22);
1444
1445                         /* TX byte count fix */
1446                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1447                         reg_ctrl &= ~(1 << 29);
1448
1449                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1450                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1451                         break;
1452                 case e1000_80003es2lan:
1453         /* improve small packet performace for fiber/serdes */
1454                         if ((hw->media_type == e1000_media_type_fiber)
1455                         || (hw->media_type ==
1456                                 e1000_media_type_internal_serdes)) {
1457                                 reg_tarc0 &= ~(1 << 20);
1458                         }
1459
1460                 /* Multiple read bit is reversed polarity */
1461                         reg_tctl = E1000_READ_REG(hw, TCTL);
1462                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1463                         if (reg_tctl & E1000_TCTL_MULR)
1464                                 reg_tarc1 &= ~(1 << 28);
1465                         else
1466                                 reg_tarc1 |= (1 << 28);
1467
1468                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1469                         break;
1470                 case e1000_ich8lan:
1471                         /* Reduce concurrent DMA requests to 3 from 4 */
1472                         if ((hw->revision_id < 3) ||
1473                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1474                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1475                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1476
1477                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1478                         reg_ctrl_ext |= (1 << 22);
1479                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1480
1481                         /* workaround TX hang with TSO=on */
1482                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1483
1484                         /* Multiple read bit is reversed polarity */
1485                         reg_tctl = E1000_READ_REG(hw, TCTL);
1486                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1487                         if (reg_tctl & E1000_TCTL_MULR)
1488                                 reg_tarc1 &= ~(1 << 28);
1489                         else
1490                                 reg_tarc1 |= (1 << 28);
1491
1492                         /* workaround TX hang with TSO=on */
1493                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1494
1495                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1496                         break;
1497                 default:
1498                         break;
1499                 }
1500
1501                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1502         }
1503 }
1504
1505 /******************************************************************************
1506  * Performs basic configuration of the adapter.
1507  *
1508  * hw - Struct containing variables accessed by shared code
1509  *
1510  * Assumes that the controller has previously been reset and is in a
1511  * post-reset uninitialized state. Initializes the receive address registers,
1512  * multicast table, and VLAN filter table. Calls routines to setup link
1513  * configuration and flow control settings. Clears all on-chip counters. Leaves
1514  * the transmit and receive units disabled and uninitialized.
1515  *****************************************************************************/
1516 static int
1517 e1000_init_hw(struct eth_device *nic)
1518 {
1519         struct e1000_hw *hw = nic->priv;
1520         uint32_t ctrl;
1521         uint32_t i;
1522         int32_t ret_val;
1523         uint16_t pcix_cmd_word;
1524         uint16_t pcix_stat_hi_word;
1525         uint16_t cmd_mmrbc;
1526         uint16_t stat_mmrbc;
1527         uint32_t mta_size;
1528         uint32_t reg_data;
1529         uint32_t ctrl_ext;
1530         DEBUGFUNC();
1531         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1532         if ((hw->mac_type == e1000_ich8lan) &&
1533                 ((hw->revision_id < 3) ||
1534                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1535                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1536                         reg_data = E1000_READ_REG(hw, STATUS);
1537                         reg_data &= ~0x80000000;
1538                         E1000_WRITE_REG(hw, STATUS, reg_data);
1539         }
1540         /* Do not need initialize Identification LED */
1541
1542         /* Set the media type and TBI compatibility */
1543         e1000_set_media_type(hw);
1544
1545         /* Must be called after e1000_set_media_type
1546          * because media_type is used */
1547         e1000_initialize_hardware_bits(hw);
1548
1549         /* Disabling VLAN filtering. */
1550         DEBUGOUT("Initializing the IEEE VLAN\n");
1551         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1552         if (hw->mac_type != e1000_ich8lan) {
1553                 if (hw->mac_type < e1000_82545_rev_3)
1554                         E1000_WRITE_REG(hw, VET, 0);
1555                 e1000_clear_vfta(hw);
1556         }
1557
1558         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1559         if (hw->mac_type == e1000_82542_rev2_0) {
1560                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1561                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1562                                       hw->
1563                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1564                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1565                 E1000_WRITE_FLUSH(hw);
1566                 mdelay(5);
1567         }
1568
1569         /* Setup the receive address. This involves initializing all of the Receive
1570          * Address Registers (RARs 0 - 15).
1571          */
1572         e1000_init_rx_addrs(nic);
1573
1574         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1575         if (hw->mac_type == e1000_82542_rev2_0) {
1576                 E1000_WRITE_REG(hw, RCTL, 0);
1577                 E1000_WRITE_FLUSH(hw);
1578                 mdelay(1);
1579                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1580         }
1581
1582         /* Zero out the Multicast HASH table */
1583         DEBUGOUT("Zeroing the MTA\n");
1584         mta_size = E1000_MC_TBL_SIZE;
1585         if (hw->mac_type == e1000_ich8lan)
1586                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1587         for (i = 0; i < mta_size; i++) {
1588                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1589                 /* use write flush to prevent Memory Write Block (MWB) from
1590                  * occuring when accessing our register space */
1591                 E1000_WRITE_FLUSH(hw);
1592         }
1593 #if 0
1594         /* Set the PCI priority bit correctly in the CTRL register.  This
1595          * determines if the adapter gives priority to receives, or if it
1596          * gives equal priority to transmits and receives.  Valid only on
1597          * 82542 and 82543 silicon.
1598          */
1599         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1600                 ctrl = E1000_READ_REG(hw, CTRL);
1601                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1602         }
1603 #endif
1604         switch (hw->mac_type) {
1605         case e1000_82545_rev_3:
1606         case e1000_82546_rev_3:
1607                 break;
1608         default:
1609         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1610         if (hw->bus_type == e1000_bus_type_pcix) {
1611                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1612                                      &pcix_cmd_word);
1613                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1614                                      &pcix_stat_hi_word);
1615                 cmd_mmrbc =
1616                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1617                     PCIX_COMMAND_MMRBC_SHIFT;
1618                 stat_mmrbc =
1619                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1620                     PCIX_STATUS_HI_MMRBC_SHIFT;
1621                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1622                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1623                 if (cmd_mmrbc > stat_mmrbc) {
1624                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1625                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1626                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1627                                               pcix_cmd_word);
1628                 }
1629         }
1630                 break;
1631         }
1632
1633         /* More time needed for PHY to initialize */
1634         if (hw->mac_type == e1000_ich8lan)
1635                 mdelay(15);
1636
1637         /* Call a subroutine to configure the link and setup flow control. */
1638         ret_val = e1000_setup_link(nic);
1639
1640         /* Set the transmit descriptor write-back policy */
1641         if (hw->mac_type > e1000_82544) {
1642                 ctrl = E1000_READ_REG(hw, TXDCTL);
1643                 ctrl =
1644                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1645                     E1000_TXDCTL_FULL_TX_DESC_WB;
1646                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1647         }
1648
1649         switch (hw->mac_type) {
1650         default:
1651                 break;
1652         case e1000_80003es2lan:
1653                 /* Enable retransmit on late collisions */
1654                 reg_data = E1000_READ_REG(hw, TCTL);
1655                 reg_data |= E1000_TCTL_RTLC;
1656                 E1000_WRITE_REG(hw, TCTL, reg_data);
1657
1658                 /* Configure Gigabit Carry Extend Padding */
1659                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1660                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1661                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1662                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1663
1664                 /* Configure Transmit Inter-Packet Gap */
1665                 reg_data = E1000_READ_REG(hw, TIPG);
1666                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1667                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1668                 E1000_WRITE_REG(hw, TIPG, reg_data);
1669
1670                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1671                 reg_data &= ~0x00100000;
1672                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1673                 /* Fall through */
1674         case e1000_82571:
1675         case e1000_82572:
1676         case e1000_ich8lan:
1677                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1678                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1679                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1680                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1681                 break;
1682         }
1683
1684         if (hw->mac_type == e1000_82573) {
1685                 uint32_t gcr = E1000_READ_REG(hw, GCR);
1686                 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1687                 E1000_WRITE_REG(hw, GCR, gcr);
1688         }
1689
1690 #if 0
1691         /* Clear all of the statistics registers (clear on read).  It is
1692          * important that we do this after we have tried to establish link
1693          * because the symbol error count will increment wildly if there
1694          * is no link.
1695          */
1696         e1000_clear_hw_cntrs(hw);
1697
1698         /* ICH8 No-snoop bits are opposite polarity.
1699          * Set to snoop by default after reset. */
1700         if (hw->mac_type == e1000_ich8lan)
1701                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1702 #endif
1703
1704         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1705                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1706                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1707                 /* Relaxed ordering must be disabled to avoid a parity
1708                  * error crash in a PCI slot. */
1709                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1710                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1711         }
1712
1713         return ret_val;
1714 }
1715
1716 /******************************************************************************
1717  * Configures flow control and link settings.
1718  *
1719  * hw - Struct containing variables accessed by shared code
1720  *
1721  * Determines which flow control settings to use. Calls the apropriate media-
1722  * specific link configuration function. Configures the flow control settings.
1723  * Assuming the adapter has a valid link partner, a valid link should be
1724  * established. Assumes the hardware has previously been reset and the
1725  * transmitter and receiver are not enabled.
1726  *****************************************************************************/
1727 static int
1728 e1000_setup_link(struct eth_device *nic)
1729 {
1730         struct e1000_hw *hw = nic->priv;
1731         uint32_t ctrl_ext;
1732         int32_t ret_val;
1733         uint16_t eeprom_data;
1734
1735         DEBUGFUNC();
1736
1737         /* In the case of the phy reset being blocked, we already have a link.
1738          * We do not have to set it up again. */
1739         if (e1000_check_phy_reset_block(hw))
1740                 return E1000_SUCCESS;
1741
1742 #ifndef CONFIG_AP1000
1743         /* Read and store word 0x0F of the EEPROM. This word contains bits
1744          * that determine the hardware's default PAUSE (flow control) mode,
1745          * a bit that determines whether the HW defaults to enabling or
1746          * disabling auto-negotiation, and the direction of the
1747          * SW defined pins. If there is no SW over-ride of the flow
1748          * control setting, then the variable hw->fc will
1749          * be initialized based on a value in the EEPROM.
1750          */
1751         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1752                                 &eeprom_data) < 0) {
1753                 DEBUGOUT("EEPROM Read Error\n");
1754                 return -E1000_ERR_EEPROM;
1755         }
1756 #else
1757         /* we have to hardcode the proper value for our hardware. */
1758         /* this value is for the 82540EM pci card used for prototyping, and it works. */
1759         eeprom_data = 0xb220;
1760 #endif
1761
1762         if (hw->fc == e1000_fc_default) {
1763                 switch (hw->mac_type) {
1764                 case e1000_ich8lan:
1765                 case e1000_82573:
1766                         hw->fc = e1000_fc_full;
1767                         break;
1768                 default:
1769 #ifndef CONFIG_AP1000
1770                         ret_val = e1000_read_eeprom(hw,
1771                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1772                         if (ret_val) {
1773                                 DEBUGOUT("EEPROM Read Error\n");
1774                                 return -E1000_ERR_EEPROM;
1775                         }
1776 #else
1777                         eeprom_data = 0xb220;
1778 #endif
1779                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1780                                 hw->fc = e1000_fc_none;
1781                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1782                                     EEPROM_WORD0F_ASM_DIR)
1783                                 hw->fc = e1000_fc_tx_pause;
1784                         else
1785                                 hw->fc = e1000_fc_full;
1786                         break;
1787                 }
1788         }
1789
1790         /* We want to save off the original Flow Control configuration just
1791          * in case we get disconnected and then reconnected into a different
1792          * hub or switch with different Flow Control capabilities.
1793          */
1794         if (hw->mac_type == e1000_82542_rev2_0)
1795                 hw->fc &= (~e1000_fc_tx_pause);
1796
1797         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1798                 hw->fc &= (~e1000_fc_rx_pause);
1799
1800         hw->original_fc = hw->fc;
1801
1802         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1803
1804         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1805          * polarity value for the SW controlled pins, and setup the
1806          * Extended Device Control reg with that info.
1807          * This is needed because one of the SW controlled pins is used for
1808          * signal detection.  So this should be done before e1000_setup_pcs_link()
1809          * or e1000_phy_setup() is called.
1810          */
1811         if (hw->mac_type == e1000_82543) {
1812                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1813                             SWDPIO__EXT_SHIFT);
1814                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1815         }
1816
1817         /* Call the necessary subroutine to configure the link. */
1818         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1819             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1820         if (ret_val < 0) {
1821                 return ret_val;
1822         }
1823
1824         /* Initialize the flow control address, type, and PAUSE timer
1825          * registers to their default values.  This is done even if flow
1826          * control is disabled, because it does not hurt anything to
1827          * initialize these registers.
1828          */
1829         DEBUGOUT("Initializing the Flow Control address, type"
1830                         "and timer regs\n");
1831
1832         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1833         if (hw->mac_type != e1000_ich8lan) {
1834                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1835                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1836                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1837         }
1838
1839         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1840
1841         /* Set the flow control receive threshold registers.  Normally,
1842          * these registers will be set to a default threshold that may be
1843          * adjusted later by the driver's runtime code.  However, if the
1844          * ability to transmit pause frames in not enabled, then these
1845          * registers will be set to 0.
1846          */
1847         if (!(hw->fc & e1000_fc_tx_pause)) {
1848                 E1000_WRITE_REG(hw, FCRTL, 0);
1849                 E1000_WRITE_REG(hw, FCRTH, 0);
1850         } else {
1851                 /* We need to set up the Receive Threshold high and low water marks
1852                  * as well as (optionally) enabling the transmission of XON frames.
1853                  */
1854                 if (hw->fc_send_xon) {
1855                         E1000_WRITE_REG(hw, FCRTL,
1856                                         (hw->fc_low_water | E1000_FCRTL_XONE));
1857                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1858                 } else {
1859                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1860                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1861                 }
1862         }
1863         return ret_val;
1864 }
1865
1866 /******************************************************************************
1867  * Sets up link for a fiber based adapter
1868  *
1869  * hw - Struct containing variables accessed by shared code
1870  *
1871  * Manipulates Physical Coding Sublayer functions in order to configure
1872  * link. Assumes the hardware has been previously reset and the transmitter
1873  * and receiver are not enabled.
1874  *****************************************************************************/
1875 static int
1876 e1000_setup_fiber_link(struct eth_device *nic)
1877 {
1878         struct e1000_hw *hw = nic->priv;
1879         uint32_t ctrl;
1880         uint32_t status;
1881         uint32_t txcw = 0;
1882         uint32_t i;
1883         uint32_t signal;
1884         int32_t ret_val;
1885
1886         DEBUGFUNC();
1887         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1888          * set when the optics detect a signal. On older adapters, it will be
1889          * cleared when there is a signal
1890          */
1891         ctrl = E1000_READ_REG(hw, CTRL);
1892         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1893                 signal = E1000_CTRL_SWDPIN1;
1894         else
1895                 signal = 0;
1896
1897         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1898                ctrl);
1899         /* Take the link out of reset */
1900         ctrl &= ~(E1000_CTRL_LRST);
1901
1902         e1000_config_collision_dist(hw);
1903
1904         /* Check for a software override of the flow control settings, and setup
1905          * the device accordingly.  If auto-negotiation is enabled, then software
1906          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1907          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1908          * auto-negotiation is disabled, then software will have to manually
1909          * configure the two flow control enable bits in the CTRL register.
1910          *
1911          * The possible values of the "fc" parameter are:
1912          *      0:  Flow control is completely disabled
1913          *      1:  Rx flow control is enabled (we can receive pause frames, but
1914          *          not send pause frames).
1915          *      2:  Tx flow control is enabled (we can send pause frames but we do
1916          *          not support receiving pause frames).
1917          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1918          */
1919         switch (hw->fc) {
1920         case e1000_fc_none:
1921                 /* Flow control is completely disabled by a software over-ride. */
1922                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1923                 break;
1924         case e1000_fc_rx_pause:
1925                 /* RX Flow control is enabled and TX Flow control is disabled by a
1926                  * software over-ride. Since there really isn't a way to advertise
1927                  * that we are capable of RX Pause ONLY, we will advertise that we
1928                  * support both symmetric and asymmetric RX PAUSE. Later, we will
1929                  *  disable the adapter's ability to send PAUSE frames.
1930                  */
1931                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1932                 break;
1933         case e1000_fc_tx_pause:
1934                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1935                  * software over-ride.
1936                  */
1937                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1938                 break;
1939         case e1000_fc_full:
1940                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1941                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1942                 break;
1943         default:
1944                 DEBUGOUT("Flow control param set incorrectly\n");
1945                 return -E1000_ERR_CONFIG;
1946                 break;
1947         }
1948
1949         /* Since auto-negotiation is enabled, take the link out of reset (the link
1950          * will be in reset, because we previously reset the chip). This will
1951          * restart auto-negotiation.  If auto-neogtiation is successful then the
1952          * link-up status bit will be set and the flow control enable bits (RFCE
1953          * and TFCE) will be set according to their negotiated value.
1954          */
1955         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
1956
1957         E1000_WRITE_REG(hw, TXCW, txcw);
1958         E1000_WRITE_REG(hw, CTRL, ctrl);
1959         E1000_WRITE_FLUSH(hw);
1960
1961         hw->txcw = txcw;
1962         mdelay(1);
1963
1964         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1965          * indication in the Device Status Register.  Time-out if a link isn't
1966          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1967          * less than 500 milliseconds even if the other end is doing it in SW).
1968          */
1969         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1970                 DEBUGOUT("Looking for Link\n");
1971                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1972                         mdelay(10);
1973                         status = E1000_READ_REG(hw, STATUS);
1974                         if (status & E1000_STATUS_LU)
1975                                 break;
1976                 }
1977                 if (i == (LINK_UP_TIMEOUT / 10)) {
1978                         /* AutoNeg failed to achieve a link, so we'll call
1979                          * e1000_check_for_link. This routine will force the link up if we
1980                          * detect a signal. This will allow us to communicate with
1981                          * non-autonegotiating link partners.
1982                          */
1983                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1984                         hw->autoneg_failed = 1;
1985                         ret_val = e1000_check_for_link(nic);
1986                         if (ret_val < 0) {
1987                                 DEBUGOUT("Error while checking for link\n");
1988                                 return ret_val;
1989                         }
1990                         hw->autoneg_failed = 0;
1991                 } else {
1992                         hw->autoneg_failed = 0;
1993                         DEBUGOUT("Valid Link Found\n");
1994                 }
1995         } else {
1996                 DEBUGOUT("No Signal Detected\n");
1997                 return -E1000_ERR_NOLINK;
1998         }
1999         return 0;
2000 }
2001
2002 /*****************************************************************************
2003  * Set PHY to class A mode
2004  * Assumes the following operations will follow to enable the new class mode.
2005  *  1. Do a PHY soft reset
2006  *  2. Restart auto-negotiation or force link.
2007  *
2008  * hw - Struct containing variables accessed by shared code
2009  ****************************************************************************/
2010 static int32_t
2011 e1000_set_phy_mode(struct e1000_hw *hw)
2012 {
2013         int32_t ret_val;
2014         uint16_t eeprom_data;
2015
2016         DEBUGFUNC();
2017
2018         if ((hw->mac_type == e1000_82545_rev_3) &&
2019                 (hw->media_type == e1000_media_type_copper)) {
2020                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
2021                                 1, &eeprom_data);
2022                 if (ret_val)
2023                         return ret_val;
2024
2025                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
2026                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
2027                         ret_val = e1000_write_phy_reg(hw,
2028                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
2029                         if (ret_val)
2030                                 return ret_val;
2031                         ret_val = e1000_write_phy_reg(hw,
2032                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
2033                         if (ret_val)
2034                                 return ret_val;
2035
2036                         hw->phy_reset_disable = FALSE;
2037                 }
2038         }
2039
2040         return E1000_SUCCESS;
2041 }
2042
2043 /******************************************************************************
2044 * Make sure we have a valid PHY and change PHY mode before link setup.
2045 *
2046 * hw - Struct containing variables accessed by shared code
2047 ******************************************************************************/
2048 static int32_t
2049 e1000_copper_link_preconfig(struct e1000_hw *hw)
2050 {
2051         uint32_t ctrl;
2052         int32_t ret_val;
2053         uint16_t phy_data;
2054
2055         DEBUGFUNC();
2056
2057         ctrl = E1000_READ_REG(hw, CTRL);
2058         /* With 82543, we need to force speed and duplex on the MAC equal to what
2059          * the PHY speed and duplex configuration is. In addition, we need to
2060          * perform a hardware reset on the PHY to take it out of reset.
2061          */
2062         if (hw->mac_type > e1000_82543) {
2063                 ctrl |= E1000_CTRL_SLU;
2064                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2065                 E1000_WRITE_REG(hw, CTRL, ctrl);
2066         } else {
2067                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2068                                 | E1000_CTRL_SLU);
2069                 E1000_WRITE_REG(hw, CTRL, ctrl);
2070                 ret_val = e1000_phy_hw_reset(hw);
2071                 if (ret_val)
2072                         return ret_val;
2073         }
2074
2075         /* Make sure we have a valid PHY */
2076         ret_val = e1000_detect_gig_phy(hw);
2077         if (ret_val) {
2078                 DEBUGOUT("Error, did not detect valid phy.\n");
2079                 return ret_val;
2080         }
2081         DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2082
2083 #ifndef CONFIG_AP1000
2084         /* Set PHY to class A mode (if necessary) */
2085         ret_val = e1000_set_phy_mode(hw);
2086         if (ret_val)
2087                 return ret_val;
2088 #endif
2089         if ((hw->mac_type == e1000_82545_rev_3) ||
2090                 (hw->mac_type == e1000_82546_rev_3)) {
2091                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2092                                 &phy_data);
2093                 phy_data |= 0x00000008;
2094                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2095                                 phy_data);
2096         }
2097
2098         if (hw->mac_type <= e1000_82543 ||
2099                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2100                 hw->mac_type == e1000_82541_rev_2
2101                 || hw->mac_type == e1000_82547_rev_2)
2102                         hw->phy_reset_disable = FALSE;
2103
2104         return E1000_SUCCESS;
2105 }
2106
2107 /*****************************************************************************
2108  *
2109  * This function sets the lplu state according to the active flag.  When
2110  * activating lplu this function also disables smart speed and vise versa.
2111  * lplu will not be activated unless the device autonegotiation advertisment
2112  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2113  * hw: Struct containing variables accessed by shared code
2114  * active - true to enable lplu false to disable lplu.
2115  *
2116  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2117  *            E1000_SUCCESS at any other case.
2118  *
2119  ****************************************************************************/
2120
2121 static int32_t
2122 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2123 {
2124         uint32_t phy_ctrl = 0;
2125         int32_t ret_val;
2126         uint16_t phy_data;
2127         DEBUGFUNC();
2128
2129         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2130             && hw->phy_type != e1000_phy_igp_3)
2131                 return E1000_SUCCESS;
2132
2133         /* During driver activity LPLU should not be used or it will attain link
2134          * from the lowest speeds starting from 10Mbps. The capability is used
2135          * for Dx transitions and states */
2136         if (hw->mac_type == e1000_82541_rev_2
2137                         || hw->mac_type == e1000_82547_rev_2) {
2138                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2139                                 &phy_data);
2140                 if (ret_val)
2141                         return ret_val;
2142         } else if (hw->mac_type == e1000_ich8lan) {
2143                 /* MAC writes into PHY register based on the state transition
2144                  * and start auto-negotiation. SW driver can overwrite the
2145                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2146                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2147         } else {
2148                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2149                                 &phy_data);
2150                 if (ret_val)
2151                         return ret_val;
2152         }
2153
2154         if (!active) {
2155                 if (hw->mac_type == e1000_82541_rev_2 ||
2156                         hw->mac_type == e1000_82547_rev_2) {
2157                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2158                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2159                                         phy_data);
2160                         if (ret_val)
2161                                 return ret_val;
2162                 } else {
2163                         if (hw->mac_type == e1000_ich8lan) {
2164                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2165                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2166                         } else {
2167                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2168                                 ret_val = e1000_write_phy_reg(hw,
2169                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2170                                 if (ret_val)
2171                                         return ret_val;
2172                         }
2173                 }
2174
2175         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2176          * Dx states where the power conservation is most important.  During
2177          * driver activity we should enable SmartSpeed, so performance is
2178          * maintained. */
2179                 if (hw->smart_speed == e1000_smart_speed_on) {
2180                         ret_val = e1000_read_phy_reg(hw,
2181                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2182                         if (ret_val)
2183                                 return ret_val;
2184
2185                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2186                         ret_val = e1000_write_phy_reg(hw,
2187                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2188                         if (ret_val)
2189                                 return ret_val;
2190                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2191                         ret_val = e1000_read_phy_reg(hw,
2192                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2193                         if (ret_val)
2194                                 return ret_val;
2195
2196                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2197                         ret_val = e1000_write_phy_reg(hw,
2198                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2199                         if (ret_val)
2200                                 return ret_val;
2201                 }
2202
2203         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2204                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2205                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2206
2207                 if (hw->mac_type == e1000_82541_rev_2 ||
2208                     hw->mac_type == e1000_82547_rev_2) {
2209                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2210                         ret_val = e1000_write_phy_reg(hw,
2211                                         IGP01E1000_GMII_FIFO, phy_data);
2212                         if (ret_val)
2213                                 return ret_val;
2214                 } else {
2215                         if (hw->mac_type == e1000_ich8lan) {
2216                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2217                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2218                         } else {
2219                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2220                                 ret_val = e1000_write_phy_reg(hw,
2221                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2222                                 if (ret_val)
2223                                         return ret_val;
2224                         }
2225                 }
2226
2227                 /* When LPLU is enabled we should disable SmartSpeed */
2228                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2229                                 &phy_data);
2230                 if (ret_val)
2231                         return ret_val;
2232
2233                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2234                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2235                                 phy_data);
2236                 if (ret_val)
2237                         return ret_val;
2238         }
2239         return E1000_SUCCESS;
2240 }
2241
2242 /*****************************************************************************
2243  *
2244  * This function sets the lplu d0 state according to the active flag.  When
2245  * activating lplu this function also disables smart speed and vise versa.
2246  * lplu will not be activated unless the device autonegotiation advertisment
2247  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2248  * hw: Struct containing variables accessed by shared code
2249  * active - true to enable lplu false to disable lplu.
2250  *
2251  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2252  *            E1000_SUCCESS at any other case.
2253  *
2254  ****************************************************************************/
2255
2256 static int32_t
2257 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2258 {
2259         uint32_t phy_ctrl = 0;
2260         int32_t ret_val;
2261         uint16_t phy_data;
2262         DEBUGFUNC();
2263
2264         if (hw->mac_type <= e1000_82547_rev_2)
2265                 return E1000_SUCCESS;
2266
2267         if (hw->mac_type == e1000_ich8lan) {
2268                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2269         } else {
2270                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2271                                 &phy_data);
2272                 if (ret_val)
2273                         return ret_val;
2274         }
2275
2276         if (!active) {
2277                 if (hw->mac_type == e1000_ich8lan) {
2278                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2279                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2280                 } else {
2281                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2282                         ret_val = e1000_write_phy_reg(hw,
2283                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2284                         if (ret_val)
2285                                 return ret_val;
2286                 }
2287
2288         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2289          * Dx states where the power conservation is most important.  During
2290          * driver activity we should enable SmartSpeed, so performance is
2291          * maintained. */
2292                 if (hw->smart_speed == e1000_smart_speed_on) {
2293                         ret_val = e1000_read_phy_reg(hw,
2294                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2295                         if (ret_val)
2296                                 return ret_val;
2297
2298                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2299                         ret_val = e1000_write_phy_reg(hw,
2300                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2301                         if (ret_val)
2302                                 return ret_val;
2303                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2304                         ret_val = e1000_read_phy_reg(hw,
2305                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2306                         if (ret_val)
2307                                 return ret_val;
2308
2309                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2310                         ret_val = e1000_write_phy_reg(hw,
2311                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2312                         if (ret_val)
2313                                 return ret_val;
2314                 }
2315
2316
2317         } else {
2318
2319                 if (hw->mac_type == e1000_ich8lan) {
2320                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2321                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2322                 } else {
2323                         phy_data |= IGP02E1000_PM_D0_LPLU;
2324                         ret_val = e1000_write_phy_reg(hw,
2325                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2326                         if (ret_val)
2327                                 return ret_val;
2328                 }
2329
2330                 /* When LPLU is enabled we should disable SmartSpeed */
2331                 ret_val = e1000_read_phy_reg(hw,
2332                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2333                 if (ret_val)
2334                         return ret_val;
2335
2336                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2337                 ret_val = e1000_write_phy_reg(hw,
2338                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2339                 if (ret_val)
2340                         return ret_val;
2341
2342         }
2343         return E1000_SUCCESS;
2344 }
2345
2346 /********************************************************************
2347 * Copper link setup for e1000_phy_igp series.
2348 *
2349 * hw - Struct containing variables accessed by shared code
2350 *********************************************************************/
2351 static int32_t
2352 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2353 {
2354         uint32_t led_ctrl;
2355         int32_t ret_val;
2356         uint16_t phy_data;
2357
2358         DEBUGOUT();
2359
2360         if (hw->phy_reset_disable)
2361                 return E1000_SUCCESS;
2362
2363         ret_val = e1000_phy_reset(hw);
2364         if (ret_val) {
2365                 DEBUGOUT("Error Resetting the PHY\n");
2366                 return ret_val;
2367         }
2368
2369         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2370         mdelay(15);
2371         if (hw->mac_type != e1000_ich8lan) {
2372                 /* Configure activity LED after PHY reset */
2373                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2374                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2375                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2376                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2377         }
2378
2379         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2380         if (hw->phy_type == e1000_phy_igp) {
2381                 /* disable lplu d3 during driver init */
2382                 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2383                 if (ret_val) {
2384                         DEBUGOUT("Error Disabling LPLU D3\n");
2385                         return ret_val;
2386                 }
2387         }
2388
2389         /* disable lplu d0 during driver init */
2390         ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2391         if (ret_val) {
2392                 DEBUGOUT("Error Disabling LPLU D0\n");
2393                 return ret_val;
2394         }
2395         /* Configure mdi-mdix settings */
2396         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2397         if (ret_val)
2398                 return ret_val;
2399
2400         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2401                 hw->dsp_config_state = e1000_dsp_config_disabled;
2402                 /* Force MDI for earlier revs of the IGP PHY */
2403                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2404                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2405                 hw->mdix = 1;
2406
2407         } else {
2408                 hw->dsp_config_state = e1000_dsp_config_enabled;
2409                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2410
2411                 switch (hw->mdix) {
2412                 case 1:
2413                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2414                         break;
2415                 case 2:
2416                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2417                         break;
2418                 case 0:
2419                 default:
2420                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2421                         break;
2422                 }
2423         }
2424         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2425         if (ret_val)
2426                 return ret_val;
2427
2428         /* set auto-master slave resolution settings */
2429         if (hw->autoneg) {
2430                 e1000_ms_type phy_ms_setting = hw->master_slave;
2431
2432                 if (hw->ffe_config_state == e1000_ffe_config_active)
2433                         hw->ffe_config_state = e1000_ffe_config_enabled;
2434
2435                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2436                         hw->dsp_config_state = e1000_dsp_config_enabled;
2437
2438                 /* when autonegotiation advertisment is only 1000Mbps then we
2439                   * should disable SmartSpeed and enable Auto MasterSlave
2440                   * resolution as hardware default. */
2441                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2442                         /* Disable SmartSpeed */
2443                         ret_val = e1000_read_phy_reg(hw,
2444                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2445                         if (ret_val)
2446                                 return ret_val;
2447                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2448                         ret_val = e1000_write_phy_reg(hw,
2449                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2450                         if (ret_val)
2451                                 return ret_val;
2452                         /* Set auto Master/Slave resolution process */
2453                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2454                                         &phy_data);
2455                         if (ret_val)
2456                                 return ret_val;
2457                         phy_data &= ~CR_1000T_MS_ENABLE;
2458                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2459                                         phy_data);
2460                         if (ret_val)
2461                                 return ret_val;
2462                 }
2463
2464                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2465                 if (ret_val)
2466                         return ret_val;
2467
2468                 /* load defaults for future use */
2469                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2470                                 ((phy_data & CR_1000T_MS_VALUE) ?
2471                                 e1000_ms_force_master :
2472                                 e1000_ms_force_slave) :
2473                                 e1000_ms_auto;
2474
2475                 switch (phy_ms_setting) {
2476                 case e1000_ms_force_master:
2477                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2478                         break;
2479                 case e1000_ms_force_slave:
2480                         phy_data |= CR_1000T_MS_ENABLE;
2481                         phy_data &= ~(CR_1000T_MS_VALUE);
2482                         break;
2483                 case e1000_ms_auto:
2484                         phy_data &= ~CR_1000T_MS_ENABLE;
2485                 default:
2486                         break;
2487                 }
2488                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2489                 if (ret_val)
2490                         return ret_val;
2491         }
2492
2493         return E1000_SUCCESS;
2494 }
2495
2496 /*****************************************************************************
2497  * This function checks the mode of the firmware.
2498  *
2499  * returns  - TRUE when the mode is IAMT or FALSE.
2500  ****************************************************************************/
2501 boolean_t
2502 e1000_check_mng_mode(struct e1000_hw *hw)
2503 {
2504         uint32_t fwsm;
2505         DEBUGFUNC();
2506
2507         fwsm = E1000_READ_REG(hw, FWSM);
2508
2509         if (hw->mac_type == e1000_ich8lan) {
2510                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2511                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2512                         return TRUE;
2513         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2514                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2515                         return TRUE;
2516
2517         return FALSE;
2518 }
2519
2520 static int32_t
2521 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2522 {
2523         uint32_t reg_val;
2524         uint16_t swfw;
2525         DEBUGFUNC();
2526
2527         if ((hw->mac_type == e1000_80003es2lan) &&
2528                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2529                 swfw = E1000_SWFW_PHY1_SM;
2530         } else {
2531                 swfw = E1000_SWFW_PHY0_SM;
2532         }
2533         if (e1000_swfw_sync_acquire(hw, swfw))
2534                 return -E1000_ERR_SWFW_SYNC;
2535
2536         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2537                         & E1000_KUMCTRLSTA_OFFSET) | data;
2538         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2539         udelay(2);
2540
2541         return E1000_SUCCESS;
2542 }
2543
2544 static int32_t
2545 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2546 {
2547         uint32_t reg_val;
2548         uint16_t swfw;
2549         DEBUGFUNC();
2550
2551         if ((hw->mac_type == e1000_80003es2lan) &&
2552             (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2553                 swfw = E1000_SWFW_PHY1_SM;
2554         } else {
2555                 swfw = E1000_SWFW_PHY0_SM;
2556         }
2557         if (e1000_swfw_sync_acquire(hw, swfw))
2558                 return -E1000_ERR_SWFW_SYNC;
2559
2560         /* Write register address */
2561         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2562                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2563         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2564         udelay(2);
2565
2566         /* Read the data returned */
2567         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2568         *data = (uint16_t)reg_val;
2569
2570         return E1000_SUCCESS;
2571 }
2572
2573 /********************************************************************
2574 * Copper link setup for e1000_phy_gg82563 series.
2575 *
2576 * hw - Struct containing variables accessed by shared code
2577 *********************************************************************/
2578 static int32_t
2579 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2580 {
2581         int32_t ret_val;
2582         uint16_t phy_data;
2583         uint32_t reg_data;
2584
2585         DEBUGFUNC();
2586
2587         if (!hw->phy_reset_disable) {
2588                 /* Enable CRS on TX for half-duplex operation. */
2589                 ret_val = e1000_read_phy_reg(hw,
2590                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2591                 if (ret_val)
2592                         return ret_val;
2593
2594                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2595                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2596                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2597
2598                 ret_val = e1000_write_phy_reg(hw,
2599                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2600                 if (ret_val)
2601                         return ret_val;
2602
2603                 /* Options:
2604                  *   MDI/MDI-X = 0 (default)
2605                  *   0 - Auto for all speeds
2606                  *   1 - MDI mode
2607                  *   2 - MDI-X mode
2608                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2609                  */
2610                 ret_val = e1000_read_phy_reg(hw,
2611                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2612                 if (ret_val)
2613                         return ret_val;
2614
2615                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2616
2617                 switch (hw->mdix) {
2618                 case 1:
2619                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2620                         break;
2621                 case 2:
2622                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2623                         break;
2624                 case 0:
2625                 default:
2626                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2627                         break;
2628                 }
2629
2630                 /* Options:
2631                  *   disable_polarity_correction = 0 (default)
2632                  *       Automatic Correction for Reversed Cable Polarity
2633                  *   0 - Disabled
2634                  *   1 - Enabled
2635                  */
2636                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2637                 ret_val = e1000_write_phy_reg(hw,
2638                                 GG82563_PHY_SPEC_CTRL, phy_data);
2639
2640                 if (ret_val)
2641                         return ret_val;
2642
2643                 /* SW Reset the PHY so all changes take effect */
2644                 ret_val = e1000_phy_reset(hw);
2645                 if (ret_val) {
2646                         DEBUGOUT("Error Resetting the PHY\n");
2647                         return ret_val;
2648                 }
2649         } /* phy_reset_disable */
2650
2651         if (hw->mac_type == e1000_80003es2lan) {
2652                 /* Bypass RX and TX FIFO's */
2653                 ret_val = e1000_write_kmrn_reg(hw,
2654                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2655                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2656                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2657                 if (ret_val)
2658                         return ret_val;
2659
2660                 ret_val = e1000_read_phy_reg(hw,
2661                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2662                 if (ret_val)
2663                         return ret_val;
2664
2665                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2666                 ret_val = e1000_write_phy_reg(hw,
2667                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2668
2669                 if (ret_val)
2670                         return ret_val;
2671
2672                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2673                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2674                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2675
2676                 ret_val = e1000_read_phy_reg(hw,
2677                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2678                 if (ret_val)
2679                         return ret_val;
2680
2681         /* Do not init these registers when the HW is in IAMT mode, since the
2682          * firmware will have already initialized them.  We only initialize
2683          * them if the HW is not in IAMT mode.
2684          */
2685                 if (e1000_check_mng_mode(hw) == FALSE) {
2686                         /* Enable Electrical Idle on the PHY */
2687                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2688                         ret_val = e1000_write_phy_reg(hw,
2689                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2690                         if (ret_val)
2691                                 return ret_val;
2692
2693                         ret_val = e1000_read_phy_reg(hw,
2694                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2695                         if (ret_val)
2696                                 return ret_val;
2697
2698                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2699                         ret_val = e1000_write_phy_reg(hw,
2700                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2701
2702                         if (ret_val)
2703                                 return ret_val;
2704                 }
2705
2706                 /* Workaround: Disable padding in Kumeran interface in the MAC
2707                  * and in the PHY to avoid CRC errors.
2708                  */
2709                 ret_val = e1000_read_phy_reg(hw,
2710                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2711                 if (ret_val)
2712                         return ret_val;
2713                 phy_data |= GG82563_ICR_DIS_PADDING;
2714                 ret_val = e1000_write_phy_reg(hw,
2715                                 GG82563_PHY_INBAND_CTRL, phy_data);
2716                 if (ret_val)
2717                         return ret_val;
2718         }
2719         return E1000_SUCCESS;
2720 }
2721
2722 /********************************************************************
2723 * Copper link setup for e1000_phy_m88 series.
2724 *
2725 * hw - Struct containing variables accessed by shared code
2726 *********************************************************************/
2727 static int32_t
2728 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2729 {
2730         int32_t ret_val;
2731         uint16_t phy_data;
2732
2733         DEBUGFUNC();
2734
2735         if (hw->phy_reset_disable)
2736                 return E1000_SUCCESS;
2737
2738         /* Enable CRS on TX. This must be set for half-duplex operation. */
2739         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2740         if (ret_val)
2741                 return ret_val;
2742
2743         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2744
2745         /* Options:
2746          *   MDI/MDI-X = 0 (default)
2747          *   0 - Auto for all speeds
2748          *   1 - MDI mode
2749          *   2 - MDI-X mode
2750          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2751          */
2752         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2753
2754         switch (hw->mdix) {
2755         case 1:
2756                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2757                 break;
2758         case 2:
2759                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2760                 break;
2761         case 3:
2762                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2763                 break;
2764         case 0:
2765         default:
2766                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2767                 break;
2768         }
2769
2770         /* Options:
2771          *   disable_polarity_correction = 0 (default)
2772          *       Automatic Correction for Reversed Cable Polarity
2773          *   0 - Disabled
2774          *   1 - Enabled
2775          */
2776         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2777         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2778         if (ret_val)
2779                 return ret_val;
2780
2781         if (hw->phy_revision < M88E1011_I_REV_4) {
2782                 /* Force TX_CLK in the Extended PHY Specific Control Register
2783                  * to 25MHz clock.
2784                  */
2785                 ret_val = e1000_read_phy_reg(hw,
2786                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2787                 if (ret_val)
2788                         return ret_val;
2789
2790                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2791
2792                 if ((hw->phy_revision == E1000_REVISION_2) &&
2793                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2794                         /* Vidalia Phy, set the downshift counter to 5x */
2795                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2796                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2797                         ret_val = e1000_write_phy_reg(hw,
2798                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2799                         if (ret_val)
2800                                 return ret_val;
2801                 } else {
2802                         /* Configure Master and Slave downshift values */
2803                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2804                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2805                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2806                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2807                         ret_val = e1000_write_phy_reg(hw,
2808                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2809                         if (ret_val)
2810                                 return ret_val;
2811                 }
2812         }
2813
2814         /* SW Reset the PHY so all changes take effect */
2815         ret_val = e1000_phy_reset(hw);
2816         if (ret_val) {
2817                 DEBUGOUT("Error Resetting the PHY\n");
2818                 return ret_val;
2819         }
2820
2821         return E1000_SUCCESS;
2822 }
2823
2824 /********************************************************************
2825 * Setup auto-negotiation and flow control advertisements,
2826 * and then perform auto-negotiation.
2827 *
2828 * hw - Struct containing variables accessed by shared code
2829 *********************************************************************/
2830 static int32_t
2831 e1000_copper_link_autoneg(struct e1000_hw *hw)
2832 {
2833         int32_t ret_val;
2834         uint16_t phy_data;
2835
2836         DEBUGFUNC();
2837
2838         /* Perform some bounds checking on the hw->autoneg_advertised
2839          * parameter.  If this variable is zero, then set it to the default.
2840          */
2841         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2842
2843         /* If autoneg_advertised is zero, we assume it was not defaulted
2844          * by the calling code so we set to advertise full capability.
2845          */
2846         if (hw->autoneg_advertised == 0)
2847                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2848
2849         /* IFE phy only supports 10/100 */
2850         if (hw->phy_type == e1000_phy_ife)
2851                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2852
2853         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2854         ret_val = e1000_phy_setup_autoneg(hw);
2855         if (ret_val) {
2856                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2857                 return ret_val;
2858         }
2859         DEBUGOUT("Restarting Auto-Neg\n");
2860
2861         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2862          * the Auto Neg Restart bit in the PHY control register.
2863          */
2864         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2865         if (ret_val)
2866                 return ret_val;
2867
2868         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2869         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2870         if (ret_val)
2871                 return ret_val;
2872
2873         /* Does the user want to wait for Auto-Neg to complete here, or
2874          * check at a later time (for example, callback routine).
2875          */
2876         /* If we do not wait for autonegtation to complete I
2877          * do not see a valid link status.
2878          * wait_autoneg_complete = 1 .
2879          */
2880         if (hw->wait_autoneg_complete) {
2881                 ret_val = e1000_wait_autoneg(hw);
2882                 if (ret_val) {
2883                         DEBUGOUT("Error while waiting for autoneg"
2884                                         "to complete\n");
2885                         return ret_val;
2886                 }
2887         }
2888
2889         hw->get_link_status = TRUE;
2890
2891         return E1000_SUCCESS;
2892 }
2893
2894 /******************************************************************************
2895 * Config the MAC and the PHY after link is up.
2896 *   1) Set up the MAC to the current PHY speed/duplex
2897 *      if we are on 82543.  If we
2898 *      are on newer silicon, we only need to configure
2899 *      collision distance in the Transmit Control Register.
2900 *   2) Set up flow control on the MAC to that established with
2901 *      the link partner.
2902 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
2903 *
2904 * hw - Struct containing variables accessed by shared code
2905 ******************************************************************************/
2906 static int32_t
2907 e1000_copper_link_postconfig(struct e1000_hw *hw)
2908 {
2909         int32_t ret_val;
2910         DEBUGFUNC();
2911
2912         if (hw->mac_type >= e1000_82544) {
2913                 e1000_config_collision_dist(hw);
2914         } else {
2915                 ret_val = e1000_config_mac_to_phy(hw);
2916                 if (ret_val) {
2917                         DEBUGOUT("Error configuring MAC to PHY settings\n");
2918                         return ret_val;
2919                 }
2920         }
2921         ret_val = e1000_config_fc_after_link_up(hw);
2922         if (ret_val) {
2923                 DEBUGOUT("Error Configuring Flow Control\n");
2924                 return ret_val;
2925         }
2926         return E1000_SUCCESS;
2927 }
2928
2929 /******************************************************************************
2930 * Detects which PHY is present and setup the speed and duplex
2931 *
2932 * hw - Struct containing variables accessed by shared code
2933 ******************************************************************************/
2934 static int
2935 e1000_setup_copper_link(struct eth_device *nic)
2936 {
2937         struct e1000_hw *hw = nic->priv;
2938         int32_t ret_val;
2939         uint16_t i;
2940         uint16_t phy_data;
2941         uint16_t reg_data;
2942
2943         DEBUGFUNC();
2944
2945         switch (hw->mac_type) {
2946         case e1000_80003es2lan:
2947         case e1000_ich8lan:
2948                 /* Set the mac to wait the maximum time between each
2949                  * iteration and increase the max iterations when
2950                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2951                 ret_val = e1000_write_kmrn_reg(hw,
2952                                 GG82563_REG(0x34, 4), 0xFFFF);
2953                 if (ret_val)
2954                         return ret_val;
2955                 ret_val = e1000_read_kmrn_reg(hw,
2956                                 GG82563_REG(0x34, 9), &reg_data);
2957                 if (ret_val)
2958                         return ret_val;
2959                 reg_data |= 0x3F;
2960                 ret_val = e1000_write_kmrn_reg(hw,
2961                                 GG82563_REG(0x34, 9), reg_data);
2962                 if (ret_val)
2963                         return ret_val;
2964         default:
2965                 break;
2966         }
2967
2968         /* Check if it is a valid PHY and set PHY mode if necessary. */
2969         ret_val = e1000_copper_link_preconfig(hw);
2970         if (ret_val)
2971                 return ret_val;
2972         switch (hw->mac_type) {
2973         case e1000_80003es2lan:
2974                 /* Kumeran registers are written-only */
2975                 reg_data =
2976                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2977                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2978                 ret_val = e1000_write_kmrn_reg(hw,
2979                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
2980                 if (ret_val)
2981                         return ret_val;
2982                 break;
2983         default:
2984                 break;
2985         }
2986
2987         if (hw->phy_type == e1000_phy_igp ||
2988                 hw->phy_type == e1000_phy_igp_3 ||
2989                 hw->phy_type == e1000_phy_igp_2) {
2990                 ret_val = e1000_copper_link_igp_setup(hw);
2991                 if (ret_val)
2992                         return ret_val;
2993         } else if (hw->phy_type == e1000_phy_m88) {
2994                 ret_val = e1000_copper_link_mgp_setup(hw);
2995                 if (ret_val)
2996                         return ret_val;
2997         } else if (hw->phy_type == e1000_phy_gg82563) {
2998                 ret_val = e1000_copper_link_ggp_setup(hw);
2999                 if (ret_val)
3000                         return ret_val;
3001         }
3002
3003         /* always auto */
3004         /* Setup autoneg and flow control advertisement
3005           * and perform autonegotiation */
3006         ret_val = e1000_copper_link_autoneg(hw);
3007         if (ret_val)
3008                 return ret_val;
3009
3010         /* Check link status. Wait up to 100 microseconds for link to become
3011          * valid.
3012          */
3013         for (i = 0; i < 10; i++) {
3014                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3015                 if (ret_val)
3016                         return ret_val;
3017                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3018                 if (ret_val)
3019                         return ret_val;
3020
3021                 if (phy_data & MII_SR_LINK_STATUS) {
3022                         /* Config the MAC and PHY after link is up */
3023                         ret_val = e1000_copper_link_postconfig(hw);
3024                         if (ret_val)
3025                                 return ret_val;
3026
3027                         DEBUGOUT("Valid link established!!!\n");
3028                         return E1000_SUCCESS;
3029                 }
3030                 udelay(10);
3031         }
3032
3033         DEBUGOUT("Unable to establish link!!!\n");
3034         return E1000_SUCCESS;
3035 }
3036
3037 /******************************************************************************
3038 * Configures PHY autoneg and flow control advertisement settings
3039 *
3040 * hw - Struct containing variables accessed by shared code
3041 ******************************************************************************/
3042 int32_t
3043 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3044 {
3045         int32_t ret_val;
3046         uint16_t mii_autoneg_adv_reg;
3047         uint16_t mii_1000t_ctrl_reg;
3048
3049         DEBUGFUNC();
3050
3051         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3052         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3053         if (ret_val)
3054                 return ret_val;
3055
3056         if (hw->phy_type != e1000_phy_ife) {
3057                 /* Read the MII 1000Base-T Control Register (Address 9). */
3058                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3059                                 &mii_1000t_ctrl_reg);
3060                 if (ret_val)
3061                         return ret_val;
3062         } else
3063                 mii_1000t_ctrl_reg = 0;
3064
3065         /* Need to parse both autoneg_advertised and fc and set up
3066          * the appropriate PHY registers.  First we will parse for
3067          * autoneg_advertised software override.  Since we can advertise
3068          * a plethora of combinations, we need to check each bit
3069          * individually.
3070          */
3071
3072         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3073          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3074          * the  1000Base-T Control Register (Address 9).
3075          */
3076         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3077         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3078
3079         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3080
3081         /* Do we want to advertise 10 Mb Half Duplex? */
3082         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3083                 DEBUGOUT("Advertise 10mb Half duplex\n");
3084                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3085         }
3086
3087         /* Do we want to advertise 10 Mb Full Duplex? */
3088         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3089                 DEBUGOUT("Advertise 10mb Full duplex\n");
3090                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3091         }
3092
3093         /* Do we want to advertise 100 Mb Half Duplex? */
3094         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3095                 DEBUGOUT("Advertise 100mb Half duplex\n");
3096                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3097         }
3098
3099         /* Do we want to advertise 100 Mb Full Duplex? */
3100         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3101                 DEBUGOUT("Advertise 100mb Full duplex\n");
3102                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3103         }
3104
3105         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3106         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3107                 DEBUGOUT
3108                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3109         }
3110
3111         /* Do we want to advertise 1000 Mb Full Duplex? */
3112         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3113                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3114                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3115         }
3116
3117         /* Check for a software override of the flow control settings, and
3118          * setup the PHY advertisement registers accordingly.  If
3119          * auto-negotiation is enabled, then software will have to set the
3120          * "PAUSE" bits to the correct value in the Auto-Negotiation
3121          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3122          *
3123          * The possible values of the "fc" parameter are:
3124          *      0:  Flow control is completely disabled
3125          *      1:  Rx flow control is enabled (we can receive pause frames
3126          *          but not send pause frames).
3127          *      2:  Tx flow control is enabled (we can send pause frames
3128          *          but we do not support receiving pause frames).
3129          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3130          *  other:  No software override.  The flow control configuration
3131          *          in the EEPROM is used.
3132          */
3133         switch (hw->fc) {
3134         case e1000_fc_none:     /* 0 */
3135                 /* Flow control (RX & TX) is completely disabled by a
3136                  * software over-ride.
3137                  */
3138                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3139                 break;
3140         case e1000_fc_rx_pause: /* 1 */
3141                 /* RX Flow control is enabled, and TX Flow control is
3142                  * disabled, by a software over-ride.
3143                  */
3144                 /* Since there really isn't a way to advertise that we are
3145                  * capable of RX Pause ONLY, we will advertise that we
3146                  * support both symmetric and asymmetric RX PAUSE.  Later
3147                  * (in e1000_config_fc_after_link_up) we will disable the
3148                  *hw's ability to send PAUSE frames.
3149                  */
3150                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3151                 break;
3152         case e1000_fc_tx_pause: /* 2 */
3153                 /* TX Flow control is enabled, and RX Flow control is
3154                  * disabled, by a software over-ride.
3155                  */
3156                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3157                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3158                 break;
3159         case e1000_fc_full:     /* 3 */
3160                 /* Flow control (both RX and TX) is enabled by a software
3161                  * over-ride.
3162                  */
3163                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3164                 break;
3165         default:
3166                 DEBUGOUT("Flow control param set incorrectly\n");
3167                 return -E1000_ERR_CONFIG;
3168         }
3169
3170         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3171         if (ret_val)
3172                 return ret_val;
3173
3174         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3175
3176         if (hw->phy_type != e1000_phy_ife) {
3177                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3178                                 mii_1000t_ctrl_reg);
3179                 if (ret_val)
3180                         return ret_val;
3181         }
3182
3183         return E1000_SUCCESS;
3184 }
3185
3186 /******************************************************************************
3187 * Sets the collision distance in the Transmit Control register
3188 *
3189 * hw - Struct containing variables accessed by shared code
3190 *
3191 * Link should have been established previously. Reads the speed and duplex
3192 * information from the Device Status register.
3193 ******************************************************************************/
3194 static void
3195 e1000_config_collision_dist(struct e1000_hw *hw)
3196 {
3197         uint32_t tctl, coll_dist;
3198
3199         DEBUGFUNC();
3200
3201         if (hw->mac_type < e1000_82543)
3202                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3203         else
3204                 coll_dist = E1000_COLLISION_DISTANCE;
3205
3206         tctl = E1000_READ_REG(hw, TCTL);
3207
3208         tctl &= ~E1000_TCTL_COLD;
3209         tctl |= coll_dist << E1000_COLD_SHIFT;
3210
3211         E1000_WRITE_REG(hw, TCTL, tctl);
3212         E1000_WRITE_FLUSH(hw);
3213 }
3214
3215 /******************************************************************************
3216 * Sets MAC speed and duplex settings to reflect the those in the PHY
3217 *
3218 * hw - Struct containing variables accessed by shared code
3219 * mii_reg - data to write to the MII control register
3220 *
3221 * The contents of the PHY register containing the needed information need to
3222 * be passed in.
3223 ******************************************************************************/
3224 static int
3225 e1000_config_mac_to_phy(struct e1000_hw *hw)
3226 {
3227         uint32_t ctrl;
3228         uint16_t phy_data;
3229
3230         DEBUGFUNC();
3231
3232         /* Read the Device Control Register and set the bits to Force Speed
3233          * and Duplex.
3234          */
3235         ctrl = E1000_READ_REG(hw, CTRL);
3236         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3237         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3238
3239         /* Set up duplex in the Device Control and Transmit Control
3240          * registers depending on negotiated values.
3241          */
3242         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3243                 DEBUGOUT("PHY Read Error\n");
3244                 return -E1000_ERR_PHY;
3245         }
3246         if (phy_data & M88E1000_PSSR_DPLX)
3247                 ctrl |= E1000_CTRL_FD;
3248         else
3249                 ctrl &= ~E1000_CTRL_FD;
3250
3251         e1000_config_collision_dist(hw);
3252
3253         /* Set up speed in the Device Control register depending on
3254          * negotiated values.
3255          */
3256         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3257                 ctrl |= E1000_CTRL_SPD_1000;
3258         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3259                 ctrl |= E1000_CTRL_SPD_100;
3260         /* Write the configured values back to the Device Control Reg. */
3261         E1000_WRITE_REG(hw, CTRL, ctrl);
3262         return 0;
3263 }
3264
3265 /******************************************************************************
3266  * Forces the MAC's flow control settings.
3267  *
3268  * hw - Struct containing variables accessed by shared code
3269  *
3270  * Sets the TFCE and RFCE bits in the device control register to reflect
3271  * the adapter settings. TFCE and RFCE need to be explicitly set by
3272  * software when a Copper PHY is used because autonegotiation is managed
3273  * by the PHY rather than the MAC. Software must also configure these
3274  * bits when link is forced on a fiber connection.
3275  *****************************************************************************/
3276 static int
3277 e1000_force_mac_fc(struct e1000_hw *hw)
3278 {
3279         uint32_t ctrl;
3280
3281         DEBUGFUNC();
3282
3283         /* Get the current configuration of the Device Control Register */
3284         ctrl = E1000_READ_REG(hw, CTRL);
3285
3286         /* Because we didn't get link via the internal auto-negotiation
3287          * mechanism (we either forced link or we got link via PHY
3288          * auto-neg), we have to manually enable/disable transmit an
3289          * receive flow control.
3290          *
3291          * The "Case" statement below enables/disable flow control
3292          * according to the "hw->fc" parameter.
3293          *
3294          * The possible values of the "fc" parameter are:
3295          *      0:  Flow control is completely disabled
3296          *      1:  Rx flow control is enabled (we can receive pause
3297          *          frames but not send pause frames).
3298          *      2:  Tx flow control is enabled (we can send pause frames
3299          *          frames but we do not receive pause frames).
3300          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3301          *  other:  No other values should be possible at this point.
3302          */
3303
3304         switch (hw->fc) {
3305         case e1000_fc_none:
3306                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3307                 break;
3308         case e1000_fc_rx_pause:
3309                 ctrl &= (~E1000_CTRL_TFCE);
3310                 ctrl |= E1000_CTRL_RFCE;
3311                 break;
3312         case e1000_fc_tx_pause:
3313                 ctrl &= (~E1000_CTRL_RFCE);
3314                 ctrl |= E1000_CTRL_TFCE;
3315                 break;
3316         case e1000_fc_full:
3317                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3318                 break;
3319         default:
3320                 DEBUGOUT("Flow control param set incorrectly\n");
3321                 return -E1000_ERR_CONFIG;
3322         }
3323
3324         /* Disable TX Flow Control for 82542 (rev 2.0) */
3325         if (hw->mac_type == e1000_82542_rev2_0)
3326                 ctrl &= (~E1000_CTRL_TFCE);
3327
3328         E1000_WRITE_REG(hw, CTRL, ctrl);
3329         return 0;
3330 }
3331
3332 /******************************************************************************
3333  * Configures flow control settings after link is established
3334  *
3335  * hw - Struct containing variables accessed by shared code
3336  *
3337  * Should be called immediately after a valid link has been established.
3338  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3339  * and autonegotiation is enabled, the MAC flow control settings will be set
3340  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3341  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3342  *****************************************************************************/
3343 static int32_t
3344 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3345 {
3346         int32_t ret_val;
3347         uint16_t mii_status_reg;
3348         uint16_t mii_nway_adv_reg;
3349         uint16_t mii_nway_lp_ability_reg;
3350         uint16_t speed;
3351         uint16_t duplex;
3352
3353         DEBUGFUNC();
3354
3355         /* Check for the case where we have fiber media and auto-neg failed
3356          * so we had to force link.  In this case, we need to force the
3357          * configuration of the MAC to match the "fc" parameter.
3358          */
3359         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3360                 || ((hw->media_type == e1000_media_type_internal_serdes)
3361                 && (hw->autoneg_failed))
3362                 || ((hw->media_type == e1000_media_type_copper)
3363                 && (!hw->autoneg))) {
3364                 ret_val = e1000_force_mac_fc(hw);
3365                 if (ret_val < 0) {
3366                         DEBUGOUT("Error forcing flow control settings\n");
3367                         return ret_val;
3368                 }
3369         }
3370
3371         /* Check for the case where we have copper media and auto-neg is
3372          * enabled.  In this case, we need to check and see if Auto-Neg
3373          * has completed, and if so, how the PHY and link partner has
3374          * flow control configured.
3375          */
3376         if (hw->media_type == e1000_media_type_copper) {
3377                 /* Read the MII Status Register and check to see if AutoNeg
3378                  * has completed.  We read this twice because this reg has
3379                  * some "sticky" (latched) bits.
3380                  */
3381                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3382                         DEBUGOUT("PHY Read Error \n");
3383                         return -E1000_ERR_PHY;
3384                 }
3385                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3386                         DEBUGOUT("PHY Read Error \n");
3387                         return -E1000_ERR_PHY;
3388                 }
3389
3390                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3391                         /* The AutoNeg process has completed, so we now need to
3392                          * read both the Auto Negotiation Advertisement Register
3393                          * (Address 4) and the Auto_Negotiation Base Page Ability
3394                          * Register (Address 5) to determine how flow control was
3395                          * negotiated.
3396                          */
3397                         if (e1000_read_phy_reg
3398                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3399                                 DEBUGOUT("PHY Read Error\n");
3400                                 return -E1000_ERR_PHY;
3401                         }
3402                         if (e1000_read_phy_reg
3403                             (hw, PHY_LP_ABILITY,
3404                              &mii_nway_lp_ability_reg) < 0) {
3405                                 DEBUGOUT("PHY Read Error\n");
3406                                 return -E1000_ERR_PHY;
3407                         }
3408
3409                         /* Two bits in the Auto Negotiation Advertisement Register
3410                          * (Address 4) and two bits in the Auto Negotiation Base
3411                          * Page Ability Register (Address 5) determine flow control
3412                          * for both the PHY and the link partner.  The following
3413                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3414                          * 1999, describes these PAUSE resolution bits and how flow
3415                          * control is determined based upon these settings.
3416                          * NOTE:  DC = Don't Care
3417                          *
3418                          *   LOCAL DEVICE  |   LINK PARTNER
3419                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3420                          *-------|---------|-------|---------|--------------------
3421                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3422                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3423                          *   0   |    1    |   1   |    0    | e1000_fc_none
3424                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3425                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3426                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3427                          *   1   |    1    |   0   |    0    | e1000_fc_none
3428                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3429                          *
3430                          */
3431                         /* Are both PAUSE bits set to 1?  If so, this implies
3432                          * Symmetric Flow Control is enabled at both ends.  The
3433                          * ASM_DIR bits are irrelevant per the spec.
3434                          *
3435                          * For Symmetric Flow Control:
3436                          *
3437                          *   LOCAL DEVICE  |   LINK PARTNER
3438                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3439                          *-------|---------|-------|---------|--------------------
3440                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3441                          *
3442                          */
3443                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3444                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3445                                 /* Now we need to check if the user selected RX ONLY
3446                                  * of pause frames.  In this case, we had to advertise
3447                                  * FULL flow control because we could not advertise RX
3448                                  * ONLY. Hence, we must now check to see if we need to
3449                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3450                                  */
3451                                 if (hw->original_fc == e1000_fc_full) {
3452                                         hw->fc = e1000_fc_full;
3453                                         DEBUGOUT("Flow Control = FULL.\r\n");
3454                                 } else {
3455                                         hw->fc = e1000_fc_rx_pause;
3456                                         DEBUGOUT
3457                                             ("Flow Control = RX PAUSE frames only.\r\n");
3458                                 }
3459                         }
3460                         /* For receiving PAUSE frames ONLY.
3461                          *
3462                          *   LOCAL DEVICE  |   LINK PARTNER
3463                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3464                          *-------|---------|-------|---------|--------------------
3465                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3466                          *
3467                          */
3468                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3469                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3470                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3471                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3472                         {
3473                                 hw->fc = e1000_fc_tx_pause;
3474                                 DEBUGOUT
3475                                     ("Flow Control = TX PAUSE frames only.\r\n");
3476                         }
3477                         /* For transmitting PAUSE frames ONLY.
3478                          *
3479                          *   LOCAL DEVICE  |   LINK PARTNER
3480                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3481                          *-------|---------|-------|---------|--------------------
3482                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3483                          *
3484                          */
3485                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3486                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3487                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3488                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3489                         {
3490                                 hw->fc = e1000_fc_rx_pause;
3491                                 DEBUGOUT
3492                                     ("Flow Control = RX PAUSE frames only.\r\n");
3493                         }
3494                         /* Per the IEEE spec, at this point flow control should be
3495                          * disabled.  However, we want to consider that we could
3496                          * be connected to a legacy switch that doesn't advertise
3497                          * desired flow control, but can be forced on the link
3498                          * partner.  So if we advertised no flow control, that is
3499                          * what we will resolve to.  If we advertised some kind of
3500                          * receive capability (Rx Pause Only or Full Flow Control)
3501                          * and the link partner advertised none, we will configure
3502                          * ourselves to enable Rx Flow Control only.  We can do
3503                          * this safely for two reasons:  If the link partner really
3504                          * didn't want flow control enabled, and we enable Rx, no
3505                          * harm done since we won't be receiving any PAUSE frames
3506                          * anyway.  If the intent on the link partner was to have
3507                          * flow control enabled, then by us enabling RX only, we
3508                          * can at least receive pause frames and process them.
3509                          * This is a good idea because in most cases, since we are
3510                          * predominantly a server NIC, more times than not we will
3511                          * be asked to delay transmission of packets than asking
3512                          * our link partner to pause transmission of frames.
3513                          */
3514                         else if (hw->original_fc == e1000_fc_none ||
3515                                  hw->original_fc == e1000_fc_tx_pause) {
3516                                 hw->fc = e1000_fc_none;
3517                                 DEBUGOUT("Flow Control = NONE.\r\n");
3518                         } else {
3519                                 hw->fc = e1000_fc_rx_pause;
3520                                 DEBUGOUT
3521                                     ("Flow Control = RX PAUSE frames only.\r\n");
3522                         }
3523
3524                         /* Now we need to do one last check...  If we auto-
3525                          * negotiated to HALF DUPLEX, flow control should not be
3526                          * enabled per IEEE 802.3 spec.
3527                          */
3528                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3529
3530                         if (duplex == HALF_DUPLEX)
3531                                 hw->fc = e1000_fc_none;
3532
3533                         /* Now we call a subroutine to actually force the MAC
3534                          * controller to use the correct flow control settings.
3535                          */
3536                         ret_val = e1000_force_mac_fc(hw);
3537                         if (ret_val < 0) {
3538                                 DEBUGOUT
3539                                     ("Error forcing flow control settings\n");
3540                                 return ret_val;
3541                         }
3542                 } else {
3543                         DEBUGOUT
3544                             ("Copper PHY and Auto Neg has not completed.\r\n");
3545                 }
3546         }
3547         return E1000_SUCCESS;
3548 }
3549
3550 /******************************************************************************
3551  * Checks to see if the link status of the hardware has changed.
3552  *
3553  * hw - Struct containing variables accessed by shared code
3554  *
3555  * Called by any function that needs to check the link status of the adapter.
3556  *****************************************************************************/
3557 static int
3558 e1000_check_for_link(struct eth_device *nic)
3559 {
3560         struct e1000_hw *hw = nic->priv;
3561         uint32_t rxcw;
3562         uint32_t ctrl;
3563         uint32_t status;
3564         uint32_t rctl;
3565         uint32_t signal;
3566         int32_t ret_val;
3567         uint16_t phy_data;
3568         uint16_t lp_capability;
3569
3570         DEBUGFUNC();
3571
3572         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3573          * set when the optics detect a signal. On older adapters, it will be
3574          * cleared when there is a signal
3575          */
3576         ctrl = E1000_READ_REG(hw, CTRL);
3577         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3578                 signal = E1000_CTRL_SWDPIN1;
3579         else
3580                 signal = 0;
3581
3582         status = E1000_READ_REG(hw, STATUS);
3583         rxcw = E1000_READ_REG(hw, RXCW);
3584         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3585
3586         /* If we have a copper PHY then we only want to go out to the PHY
3587          * registers to see if Auto-Neg has completed and/or if our link
3588          * status has changed.  The get_link_status flag will be set if we
3589          * receive a Link Status Change interrupt or we have Rx Sequence
3590          * Errors.
3591          */
3592         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3593                 /* First we want to see if the MII Status Register reports
3594                  * link.  If so, then we want to get the current speed/duplex
3595                  * of the PHY.
3596                  * Read the register twice since the link bit is sticky.
3597                  */
3598                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3599                         DEBUGOUT("PHY Read Error\n");
3600                         return -E1000_ERR_PHY;
3601                 }
3602                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3603                         DEBUGOUT("PHY Read Error\n");
3604                         return -E1000_ERR_PHY;
3605                 }
3606
3607                 if (phy_data & MII_SR_LINK_STATUS) {
3608                         hw->get_link_status = FALSE;
3609                 } else {
3610                         /* No link detected */
3611                         return -E1000_ERR_NOLINK;
3612                 }
3613
3614                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3615                  * have Si on board that is 82544 or newer, Auto
3616                  * Speed Detection takes care of MAC speed/duplex
3617                  * configuration.  So we only need to configure Collision
3618                  * Distance in the MAC.  Otherwise, we need to force
3619                  * speed/duplex on the MAC to the current PHY speed/duplex
3620                  * settings.
3621                  */
3622                 if (hw->mac_type >= e1000_82544)
3623                         e1000_config_collision_dist(hw);
3624                 else {
3625                         ret_val = e1000_config_mac_to_phy(hw);
3626                         if (ret_val < 0) {
3627                                 DEBUGOUT
3628                                     ("Error configuring MAC to PHY settings\n");
3629                                 return ret_val;
3630                         }
3631                 }
3632
3633                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3634                  * need to restore the desired flow control settings because we may
3635                  * have had to re-autoneg with a different link partner.
3636                  */
3637                 ret_val = e1000_config_fc_after_link_up(hw);
3638                 if (ret_val < 0) {
3639                         DEBUGOUT("Error configuring flow control\n");
3640                         return ret_val;
3641                 }
3642
3643                 /* At this point we know that we are on copper and we have
3644                  * auto-negotiated link.  These are conditions for checking the link
3645                  * parter capability register.  We use the link partner capability to
3646                  * determine if TBI Compatibility needs to be turned on or off.  If
3647                  * the link partner advertises any speed in addition to Gigabit, then
3648                  * we assume that they are GMII-based, and TBI compatibility is not
3649                  * needed. If no other speeds are advertised, we assume the link
3650                  * partner is TBI-based, and we turn on TBI Compatibility.
3651                  */
3652                 if (hw->tbi_compatibility_en) {
3653                         if (e1000_read_phy_reg
3654                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3655                                 DEBUGOUT("PHY Read Error\n");
3656                                 return -E1000_ERR_PHY;
3657                         }
3658                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3659                                              NWAY_LPAR_10T_FD_CAPS |
3660                                              NWAY_LPAR_100TX_HD_CAPS |
3661                                              NWAY_LPAR_100TX_FD_CAPS |
3662                                              NWAY_LPAR_100T4_CAPS)) {
3663                                 /* If our link partner advertises anything in addition to
3664                                  * gigabit, we do not need to enable TBI compatibility.
3665                                  */
3666                                 if (hw->tbi_compatibility_on) {
3667                                         /* If we previously were in the mode, turn it off. */
3668                                         rctl = E1000_READ_REG(hw, RCTL);
3669                                         rctl &= ~E1000_RCTL_SBP;
3670                                         E1000_WRITE_REG(hw, RCTL, rctl);
3671                                         hw->tbi_compatibility_on = FALSE;
3672                                 }
3673                         } else {
3674                                 /* If TBI compatibility is was previously off, turn it on. For
3675                                  * compatibility with a TBI link partner, we will store bad
3676                                  * packets. Some frames have an additional byte on the end and
3677                                  * will look like CRC errors to to the hardware.
3678                                  */
3679                                 if (!hw->tbi_compatibility_on) {
3680                                         hw->tbi_compatibility_on = TRUE;
3681                                         rctl = E1000_READ_REG(hw, RCTL);
3682                                         rctl |= E1000_RCTL_SBP;
3683                                         E1000_WRITE_REG(hw, RCTL, rctl);
3684                                 }
3685                         }
3686                 }
3687         }
3688         /* If we don't have link (auto-negotiation failed or link partner cannot
3689          * auto-negotiate), the cable is plugged in (we have signal), and our
3690          * link partner is not trying to auto-negotiate with us (we are receiving
3691          * idles or data), we need to force link up. We also need to give
3692          * auto-negotiation time to complete, in case the cable was just plugged
3693          * in. The autoneg_failed flag does this.
3694          */
3695         else if ((hw->media_type == e1000_media_type_fiber) &&
3696                  (!(status & E1000_STATUS_LU)) &&
3697                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3698                  (!(rxcw & E1000_RXCW_C))) {
3699                 if (hw->autoneg_failed == 0) {
3700                         hw->autoneg_failed = 1;
3701                         return 0;
3702                 }
3703                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3704
3705                 /* Disable auto-negotiation in the TXCW register */
3706                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3707
3708                 /* Force link-up and also force full-duplex. */
3709                 ctrl = E1000_READ_REG(hw, CTRL);
3710                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3711                 E1000_WRITE_REG(hw, CTRL, ctrl);
3712
3713                 /* Configure Flow Control after forcing link up. */
3714                 ret_val = e1000_config_fc_after_link_up(hw);
3715                 if (ret_val < 0) {
3716                         DEBUGOUT("Error configuring flow control\n");
3717                         return ret_val;
3718                 }
3719         }
3720         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3721          * auto-negotiation in the TXCW register and disable forced link in the
3722          * Device Control register in an attempt to auto-negotiate with our link
3723          * partner.
3724          */
3725         else if ((hw->media_type == e1000_media_type_fiber) &&
3726                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3727                 DEBUGOUT
3728                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3729                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3730                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3731         }
3732         return 0;
3733 }
3734
3735 /******************************************************************************
3736 * Configure the MAC-to-PHY interface for 10/100Mbps
3737 *
3738 * hw - Struct containing variables accessed by shared code
3739 ******************************************************************************/
3740 static int32_t
3741 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3742 {
3743         int32_t ret_val = E1000_SUCCESS;
3744         uint32_t tipg;
3745         uint16_t reg_data;
3746
3747         DEBUGFUNC();
3748
3749         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3750         ret_val = e1000_write_kmrn_reg(hw,
3751                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3752         if (ret_val)
3753                 return ret_val;
3754
3755         /* Configure Transmit Inter-Packet Gap */
3756         tipg = E1000_READ_REG(hw, TIPG);
3757         tipg &= ~E1000_TIPG_IPGT_MASK;
3758         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3759         E1000_WRITE_REG(hw, TIPG, tipg);
3760
3761         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3762
3763         if (ret_val)
3764                 return ret_val;
3765
3766         if (duplex == HALF_DUPLEX)
3767                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3768         else
3769                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3770
3771         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3772
3773         return ret_val;
3774 }
3775
3776 static int32_t
3777 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3778 {
3779         int32_t ret_val = E1000_SUCCESS;
3780         uint16_t reg_data;
3781         uint32_t tipg;
3782
3783         DEBUGFUNC();
3784
3785         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3786         ret_val = e1000_write_kmrn_reg(hw,
3787                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3788         if (ret_val)
3789                 return ret_val;
3790
3791         /* Configure Transmit Inter-Packet Gap */
3792         tipg = E1000_READ_REG(hw, TIPG);
3793         tipg &= ~E1000_TIPG_IPGT_MASK;
3794         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3795         E1000_WRITE_REG(hw, TIPG, tipg);
3796
3797         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3798
3799         if (ret_val)
3800                 return ret_val;
3801
3802         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3803         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3804
3805         return ret_val;
3806 }
3807
3808 /******************************************************************************
3809  * Detects the current speed and duplex settings of the hardware.
3810  *
3811  * hw - Struct containing variables accessed by shared code
3812  * speed - Speed of the connection
3813  * duplex - Duplex setting of the connection
3814  *****************************************************************************/
3815 static int
3816 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3817                 uint16_t *duplex)
3818 {
3819         uint32_t status;
3820         int32_t ret_val;
3821         uint16_t phy_data;
3822
3823         DEBUGFUNC();
3824
3825         if (hw->mac_type >= e1000_82543) {
3826                 status = E1000_READ_REG(hw, STATUS);
3827                 if (status & E1000_STATUS_SPEED_1000) {
3828                         *speed = SPEED_1000;
3829                         DEBUGOUT("1000 Mbs, ");
3830                 } else if (status & E1000_STATUS_SPEED_100) {
3831                         *speed = SPEED_100;
3832                         DEBUGOUT("100 Mbs, ");
3833                 } else {
3834                         *speed = SPEED_10;
3835                         DEBUGOUT("10 Mbs, ");
3836                 }
3837
3838                 if (status & E1000_STATUS_FD) {
3839                         *duplex = FULL_DUPLEX;
3840                         DEBUGOUT("Full Duplex\r\n");
3841                 } else {
3842                         *duplex = HALF_DUPLEX;
3843                         DEBUGOUT(" Half Duplex\r\n");
3844                 }
3845         } else {
3846                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3847                 *speed = SPEED_1000;
3848                 *duplex = FULL_DUPLEX;
3849         }
3850
3851         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3852          * even if it is operating at half duplex.  Here we set the duplex
3853          * settings to match the duplex in the link partner's capabilities.
3854          */
3855         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3856                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3857                 if (ret_val)
3858                         return ret_val;
3859
3860                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3861                         *duplex = HALF_DUPLEX;
3862                 else {
3863                         ret_val = e1000_read_phy_reg(hw,
3864                                         PHY_LP_ABILITY, &phy_data);
3865                         if (ret_val)
3866                                 return ret_val;
3867                         if ((*speed == SPEED_100 &&
3868                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3869                                 || (*speed == SPEED_10
3870                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3871                                 *duplex = HALF_DUPLEX;
3872                 }
3873         }
3874
3875         if ((hw->mac_type == e1000_80003es2lan) &&
3876                 (hw->media_type == e1000_media_type_copper)) {
3877                 if (*speed == SPEED_1000)
3878                         ret_val = e1000_configure_kmrn_for_1000(hw);
3879                 else
3880                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3881                 if (ret_val)
3882                         return ret_val;
3883         }
3884         return E1000_SUCCESS;
3885 }
3886
3887 /******************************************************************************
3888 * Blocks until autoneg completes or times out (~4.5 seconds)
3889 *
3890 * hw - Struct containing variables accessed by shared code
3891 ******************************************************************************/
3892 static int
3893 e1000_wait_autoneg(struct e1000_hw *hw)
3894 {
3895         uint16_t i;
3896         uint16_t phy_data;
3897
3898         DEBUGFUNC();
3899         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3900
3901         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3902         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3903                 /* Read the MII Status Register and wait for Auto-Neg
3904                  * Complete bit to be set.
3905                  */
3906                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3907                         DEBUGOUT("PHY Read Error\n");
3908                         return -E1000_ERR_PHY;
3909                 }
3910                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3911                         DEBUGOUT("PHY Read Error\n");
3912                         return -E1000_ERR_PHY;
3913                 }
3914                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3915                         DEBUGOUT("Auto-Neg complete.\n");
3916                         return 0;
3917                 }
3918                 mdelay(100);
3919         }
3920         DEBUGOUT("Auto-Neg timedout.\n");
3921         return -E1000_ERR_TIMEOUT;
3922 }
3923
3924 /******************************************************************************
3925 * Raises the Management Data Clock
3926 *
3927 * hw - Struct containing variables accessed by shared code
3928 * ctrl - Device control register's current value
3929 ******************************************************************************/
3930 static void
3931 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3932 {
3933         /* Raise the clock input to the Management Data Clock (by setting the MDC
3934          * bit), and then delay 2 microseconds.
3935          */
3936         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3937         E1000_WRITE_FLUSH(hw);
3938         udelay(2);
3939 }
3940
3941 /******************************************************************************
3942 * Lowers the Management Data Clock
3943 *
3944 * hw - Struct containing variables accessed by shared code
3945 * ctrl - Device control register's current value
3946 ******************************************************************************/
3947 static void
3948 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3949 {
3950         /* Lower the clock input to the Management Data Clock (by clearing the MDC
3951          * bit), and then delay 2 microseconds.
3952          */
3953         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3954         E1000_WRITE_FLUSH(hw);
3955         udelay(2);
3956 }
3957
3958 /******************************************************************************
3959 * Shifts data bits out to the PHY
3960 *
3961 * hw - Struct containing variables accessed by shared code
3962 * data - Data to send out to the PHY
3963 * count - Number of bits to shift out
3964 *
3965 * Bits are shifted out in MSB to LSB order.
3966 ******************************************************************************/
3967 static void
3968 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3969 {
3970         uint32_t ctrl;
3971         uint32_t mask;
3972
3973         /* We need to shift "count" number of bits out to the PHY. So, the value
3974          * in the "data" parameter will be shifted out to the PHY one bit at a
3975          * time. In order to do this, "data" must be broken down into bits.
3976          */
3977         mask = 0x01;
3978         mask <<= (count - 1);
3979
3980         ctrl = E1000_READ_REG(hw, CTRL);
3981
3982         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3983         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3984
3985         while (mask) {
3986                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3987                  * then raising and lowering the Management Data Clock. A "0" is
3988                  * shifted out to the PHY by setting the MDIO bit to "0" and then
3989                  * raising and lowering the clock.
3990                  */
3991                 if (data & mask)
3992                         ctrl |= E1000_CTRL_MDIO;
3993                 else
3994                         ctrl &= ~E1000_CTRL_MDIO;
3995
3996                 E1000_WRITE_REG(hw, CTRL, ctrl);
3997                 E1000_WRITE_FLUSH(hw);
3998
3999                 udelay(2);
4000
4001                 e1000_raise_mdi_clk(hw, &ctrl);
4002                 e1000_lower_mdi_clk(hw, &ctrl);
4003
4004                 mask = mask >> 1;
4005         }
4006 }
4007
4008 /******************************************************************************
4009 * Shifts data bits in from the PHY
4010 *
4011 * hw - Struct containing variables accessed by shared code
4012 *
4013 * Bits are shifted in in MSB to LSB order.
4014 ******************************************************************************/
4015 static uint16_t
4016 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4017 {
4018         uint32_t ctrl;
4019         uint16_t data = 0;
4020         uint8_t i;
4021
4022         /* In order to read a register from the PHY, we need to shift in a total
4023          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4024          * to avoid contention on the MDIO pin when a read operation is performed.
4025          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4026          * by raising the input to the Management Data Clock (setting the MDC bit),
4027          * and then reading the value of the MDIO bit.
4028          */
4029         ctrl = E1000_READ_REG(hw, CTRL);
4030
4031         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4032         ctrl &= ~E1000_CTRL_MDIO_DIR;
4033         ctrl &= ~E1000_CTRL_MDIO;
4034
4035         E1000_WRITE_REG(hw, CTRL, ctrl);
4036         E1000_WRITE_FLUSH(hw);
4037
4038         /* Raise and Lower the clock before reading in the data. This accounts for
4039          * the turnaround bits. The first clock occurred when we clocked out the
4040          * last bit of the Register Address.
4041          */
4042         e1000_raise_mdi_clk(hw, &ctrl);
4043         e1000_lower_mdi_clk(hw, &ctrl);
4044
4045         for (data = 0, i = 0; i < 16; i++) {
4046                 data = data << 1;
4047                 e1000_raise_mdi_clk(hw, &ctrl);
4048                 ctrl = E1000_READ_REG(hw, CTRL);
4049                 /* Check to see if we shifted in a "1". */
4050                 if (ctrl & E1000_CTRL_MDIO)
4051                         data |= 1;
4052                 e1000_lower_mdi_clk(hw, &ctrl);
4053         }
4054
4055         e1000_raise_mdi_clk(hw, &ctrl);
4056         e1000_lower_mdi_clk(hw, &ctrl);
4057
4058         return data;
4059 }
4060
4061 /*****************************************************************************
4062 * Reads the value from a PHY register
4063 *
4064 * hw - Struct containing variables accessed by shared code
4065 * reg_addr - address of the PHY register to read
4066 ******************************************************************************/
4067 static int
4068 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4069 {
4070         uint32_t i;
4071         uint32_t mdic = 0;
4072         const uint32_t phy_addr = 1;
4073
4074         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4075                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4076                 return -E1000_ERR_PARAM;
4077         }
4078
4079         if (hw->mac_type > e1000_82543) {
4080                 /* Set up Op-code, Phy Address, and register address in the MDI
4081                  * Control register.  The MAC will take care of interfacing with the
4082                  * PHY to retrieve the desired data.
4083                  */
4084                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4085                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4086                         (E1000_MDIC_OP_READ));
4087
4088                 E1000_WRITE_REG(hw, MDIC, mdic);
4089
4090                 /* Poll the ready bit to see if the MDI read completed */
4091                 for (i = 0; i < 64; i++) {
4092                         udelay(10);
4093                         mdic = E1000_READ_REG(hw, MDIC);
4094                         if (mdic & E1000_MDIC_READY)
4095                                 break;
4096                 }
4097                 if (!(mdic & E1000_MDIC_READY)) {
4098                         DEBUGOUT("MDI Read did not complete\n");
4099                         return -E1000_ERR_PHY;
4100                 }
4101                 if (mdic & E1000_MDIC_ERROR) {
4102                         DEBUGOUT("MDI Error\n");
4103                         return -E1000_ERR_PHY;
4104                 }
4105                 *phy_data = (uint16_t) mdic;
4106         } else {
4107                 /* We must first send a preamble through the MDIO pin to signal the
4108                  * beginning of an MII instruction.  This is done by sending 32
4109                  * consecutive "1" bits.
4110                  */
4111                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4112
4113                 /* Now combine the next few fields that are required for a read
4114                  * operation.  We use this method instead of calling the
4115                  * e1000_shift_out_mdi_bits routine five different times. The format of
4116                  * a MII read instruction consists of a shift out of 14 bits and is
4117                  * defined as follows:
4118                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4119                  * followed by a shift in of 18 bits.  This first two bits shifted in
4120                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4121                  * READ operation is performed.  These two bits are thrown away
4122                  * followed by a shift in of 16 bits which contains the desired data.
4123                  */
4124                 mdic = ((reg_addr) | (phy_addr << 5) |
4125                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4126
4127                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4128
4129                 /* Now that we've shifted out the read command to the MII, we need to
4130                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4131                  * register address.
4132                  */
4133                 *phy_data = e1000_shift_in_mdi_bits(hw);
4134         }
4135         return 0;
4136 }
4137
4138 /******************************************************************************
4139 * Writes a value to a PHY register
4140 *
4141 * hw - Struct containing variables accessed by shared code
4142 * reg_addr - address of the PHY register to write
4143 * data - data to write to the PHY
4144 ******************************************************************************/
4145 static int
4146 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4147 {
4148         uint32_t i;
4149         uint32_t mdic = 0;
4150         const uint32_t phy_addr = 1;
4151
4152         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4153                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4154                 return -E1000_ERR_PARAM;
4155         }
4156
4157         if (hw->mac_type > e1000_82543) {
4158                 /* Set up Op-code, Phy Address, register address, and data intended
4159                  * for the PHY register in the MDI Control register.  The MAC will take
4160                  * care of interfacing with the PHY to send the desired data.
4161                  */
4162                 mdic = (((uint32_t) phy_data) |
4163                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4164                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4165                         (E1000_MDIC_OP_WRITE));
4166
4167                 E1000_WRITE_REG(hw, MDIC, mdic);
4168
4169                 /* Poll the ready bit to see if the MDI read completed */
4170                 for (i = 0; i < 64; i++) {
4171                         udelay(10);
4172                         mdic = E1000_READ_REG(hw, MDIC);
4173                         if (mdic & E1000_MDIC_READY)
4174                                 break;
4175                 }
4176                 if (!(mdic & E1000_MDIC_READY)) {
4177                         DEBUGOUT("MDI Write did not complete\n");
4178                         return -E1000_ERR_PHY;
4179                 }
4180         } else {
4181                 /* We'll need to use the SW defined pins to shift the write command
4182                  * out to the PHY. We first send a preamble to the PHY to signal the
4183                  * beginning of the MII instruction.  This is done by sending 32
4184                  * consecutive "1" bits.
4185                  */
4186                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4187
4188                 /* Now combine the remaining required fields that will indicate a
4189                  * write operation. We use this method instead of calling the
4190                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4191                  * format of a MII write instruction is as follows:
4192                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4193                  */
4194                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4195                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4196                 mdic <<= 16;
4197                 mdic |= (uint32_t) phy_data;
4198
4199                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4200         }
4201         return 0;
4202 }
4203
4204 /******************************************************************************
4205  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4206  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4207  * the caller to figure out how to deal with it.
4208  *
4209  * hw - Struct containing variables accessed by shared code
4210  *
4211  * returns: - E1000_BLK_PHY_RESET
4212  *            E1000_SUCCESS
4213  *
4214  *****************************************************************************/
4215 int32_t
4216 e1000_check_phy_reset_block(struct e1000_hw *hw)
4217 {
4218         uint32_t manc = 0;
4219         uint32_t fwsm = 0;
4220
4221         if (hw->mac_type == e1000_ich8lan) {
4222                 fwsm = E1000_READ_REG(hw, FWSM);
4223                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4224                                                 : E1000_BLK_PHY_RESET;
4225         }
4226
4227         if (hw->mac_type > e1000_82547_rev_2)
4228                 manc = E1000_READ_REG(hw, MANC);
4229         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4230                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4231 }
4232
4233 /***************************************************************************
4234  * Checks if the PHY configuration is done
4235  *
4236  * hw: Struct containing variables accessed by shared code
4237  *
4238  * returns: - E1000_ERR_RESET if fail to reset MAC
4239  *            E1000_SUCCESS at any other case.
4240  *
4241  ***************************************************************************/
4242 static int32_t
4243 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4244 {
4245         int32_t timeout = PHY_CFG_TIMEOUT;
4246         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4247
4248         DEBUGFUNC();
4249
4250         switch (hw->mac_type) {
4251         default:
4252                 mdelay(10);
4253                 break;
4254         case e1000_80003es2lan:
4255                 /* Separate *_CFG_DONE_* bit for each port */
4256                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4257                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4258         /* Fall Through */
4259         case e1000_82571:
4260         case e1000_82572:
4261                 while (timeout) {
4262                         if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4263                                 break;
4264                         else
4265                                 mdelay(1);
4266                         timeout--;
4267                 }
4268                 if (!timeout) {
4269                         DEBUGOUT("MNG configuration cycle has not "
4270                                         "completed.\n");
4271                         return -E1000_ERR_RESET;
4272                 }
4273                 break;
4274         }
4275
4276         return E1000_SUCCESS;
4277 }
4278
4279 /******************************************************************************
4280 * Returns the PHY to the power-on reset state
4281 *
4282 * hw - Struct containing variables accessed by shared code
4283 ******************************************************************************/
4284 int32_t
4285 e1000_phy_hw_reset(struct e1000_hw *hw)
4286 {
4287         uint32_t ctrl, ctrl_ext;
4288         uint32_t led_ctrl;
4289         int32_t ret_val;
4290         uint16_t swfw;
4291
4292         DEBUGFUNC();
4293
4294         /* In the case of the phy reset being blocked, it's not an error, we
4295          * simply return success without performing the reset. */
4296         ret_val = e1000_check_phy_reset_block(hw);
4297         if (ret_val)
4298                 return E1000_SUCCESS;
4299
4300         DEBUGOUT("Resetting Phy...\n");
4301
4302         if (hw->mac_type > e1000_82543) {
4303                 if ((hw->mac_type == e1000_80003es2lan) &&
4304                         (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
4305                         swfw = E1000_SWFW_PHY1_SM;
4306                 } else {
4307                         swfw = E1000_SWFW_PHY0_SM;
4308                 }
4309                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4310                         DEBUGOUT("Unable to acquire swfw sync\n");
4311                         return -E1000_ERR_SWFW_SYNC;
4312                 }
4313                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4314                  * bit. Then, take it out of reset.
4315                  */
4316                 ctrl = E1000_READ_REG(hw, CTRL);
4317                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4318                 E1000_WRITE_FLUSH(hw);
4319
4320                 if (hw->mac_type < e1000_82571)
4321                         udelay(10);
4322                 else
4323                         udelay(100);
4324
4325                 E1000_WRITE_REG(hw, CTRL, ctrl);
4326                 E1000_WRITE_FLUSH(hw);
4327
4328                 if (hw->mac_type >= e1000_82571)
4329                         mdelay(10);
4330
4331         } else {
4332                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4333                  * bit to put the PHY into reset. Then, take it out of reset.
4334                  */
4335                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4336                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4337                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4338                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4339                 E1000_WRITE_FLUSH(hw);
4340                 mdelay(10);
4341                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4342                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4343                 E1000_WRITE_FLUSH(hw);
4344         }
4345         udelay(150);
4346
4347         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4348                 /* Configure activity LED after PHY reset */
4349                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4350                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4351                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4352                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4353         }
4354
4355         /* Wait for FW to finish PHY configuration. */
4356         ret_val = e1000_get_phy_cfg_done(hw);
4357         if (ret_val != E1000_SUCCESS)
4358                 return ret_val;
4359
4360         return ret_val;
4361 }
4362
4363 /******************************************************************************
4364  * IGP phy init script - initializes the GbE PHY
4365  *
4366  * hw - Struct containing variables accessed by shared code
4367  *****************************************************************************/
4368 static void
4369 e1000_phy_init_script(struct e1000_hw *hw)
4370 {
4371         uint32_t ret_val;
4372         uint16_t phy_saved_data;
4373         DEBUGFUNC();
4374
4375         if (hw->phy_init_script) {
4376                 mdelay(20);
4377
4378                 /* Save off the current value of register 0x2F5B to be
4379                  * restored at the end of this routine. */
4380                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4381
4382                 /* Disabled the PHY transmitter */
4383                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4384
4385                 mdelay(20);
4386
4387                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4388
4389                 mdelay(5);
4390
4391                 switch (hw->mac_type) {
4392                 case e1000_82541:
4393                 case e1000_82547:
4394                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4395
4396                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4397
4398                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4399
4400                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4401
4402                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4403
4404                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4405
4406                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4407
4408                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4409
4410                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4411                         break;
4412
4413                 case e1000_82541_rev_2:
4414                 case e1000_82547_rev_2:
4415                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4416                         break;
4417                 default:
4418                         break;
4419                 }
4420
4421                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4422
4423                 mdelay(20);
4424
4425                 /* Now enable the transmitter */
4426                 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4427
4428                 if (hw->mac_type == e1000_82547) {
4429                         uint16_t fused, fine, coarse;
4430
4431                         /* Move to analog registers page */
4432                         e1000_read_phy_reg(hw,
4433                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4434
4435                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4436                                 e1000_read_phy_reg(hw,
4437                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4438
4439                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4440                                 coarse = fused
4441                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4442
4443                                 if (coarse >
4444                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4445                                         coarse -=
4446                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4447                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4448                                 } else if (coarse
4449                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4450                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4451
4452                                 fused = (fused
4453                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4454                                         (fine
4455                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4456                                         (coarse
4457                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4458
4459                                 e1000_write_phy_reg(hw,
4460                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4461                                 e1000_write_phy_reg(hw,
4462                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4463                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4464                         }
4465                 }
4466         }
4467 }
4468
4469 /******************************************************************************
4470 * Resets the PHY
4471 *
4472 * hw - Struct containing variables accessed by shared code
4473 *
4474 * Sets bit 15 of the MII Control register
4475 ******************************************************************************/
4476 int32_t
4477 e1000_phy_reset(struct e1000_hw *hw)
4478 {
4479         int32_t ret_val;
4480         uint16_t phy_data;
4481
4482         DEBUGFUNC();
4483
4484         /* In the case of the phy reset being blocked, it's not an error, we
4485          * simply return success without performing the reset. */
4486         ret_val = e1000_check_phy_reset_block(hw);
4487         if (ret_val)
4488                 return E1000_SUCCESS;
4489
4490         switch (hw->phy_type) {
4491         case e1000_phy_igp:
4492         case e1000_phy_igp_2:
4493         case e1000_phy_igp_3:
4494         case e1000_phy_ife:
4495                 ret_val = e1000_phy_hw_reset(hw);
4496                 if (ret_val)
4497                         return ret_val;
4498                 break;
4499         default:
4500                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4501                 if (ret_val)
4502                         return ret_val;
4503
4504                 phy_data |= MII_CR_RESET;
4505                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4506                 if (ret_val)
4507                         return ret_val;
4508
4509                 udelay(1);
4510                 break;
4511         }
4512
4513         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4514                 e1000_phy_init_script(hw);
4515
4516         return E1000_SUCCESS;
4517 }
4518
4519 static int e1000_set_phy_type (struct e1000_hw *hw)
4520 {
4521         DEBUGFUNC ();
4522
4523         if (hw->mac_type == e1000_undefined)
4524                 return -E1000_ERR_PHY_TYPE;
4525
4526         switch (hw->phy_id) {
4527         case M88E1000_E_PHY_ID:
4528         case M88E1000_I_PHY_ID:
4529         case M88E1011_I_PHY_ID:
4530         case M88E1111_I_PHY_ID:
4531                 hw->phy_type = e1000_phy_m88;
4532                 break;
4533         case IGP01E1000_I_PHY_ID:
4534                 if (hw->mac_type == e1000_82541 ||
4535                         hw->mac_type == e1000_82541_rev_2 ||
4536                         hw->mac_type == e1000_82547 ||
4537                         hw->mac_type == e1000_82547_rev_2) {
4538                         hw->phy_type = e1000_phy_igp;
4539                         hw->phy_type = e1000_phy_igp;
4540                         break;
4541                 }
4542         case IGP03E1000_E_PHY_ID:
4543                 hw->phy_type = e1000_phy_igp_3;
4544                 break;
4545         case IFE_E_PHY_ID:
4546         case IFE_PLUS_E_PHY_ID:
4547         case IFE_C_E_PHY_ID:
4548                 hw->phy_type = e1000_phy_ife;
4549                 break;
4550         case GG82563_E_PHY_ID:
4551                 if (hw->mac_type == e1000_80003es2lan) {
4552                         hw->phy_type = e1000_phy_gg82563;
4553                         break;
4554                 }
4555                 /* Fall Through */
4556         default:
4557                 /* Should never have loaded on this device */
4558                 hw->phy_type = e1000_phy_undefined;
4559                 return -E1000_ERR_PHY_TYPE;
4560         }
4561
4562         return E1000_SUCCESS;
4563 }
4564
4565 /******************************************************************************
4566 * Probes the expected PHY address for known PHY IDs
4567 *
4568 * hw - Struct containing variables accessed by shared code
4569 ******************************************************************************/
4570 static int32_t
4571 e1000_detect_gig_phy(struct e1000_hw *hw)
4572 {
4573         int32_t phy_init_status, ret_val;
4574         uint16_t phy_id_high, phy_id_low;
4575         boolean_t match = FALSE;
4576
4577         DEBUGFUNC();
4578
4579         /* The 82571 firmware may still be configuring the PHY.  In this
4580          * case, we cannot access the PHY until the configuration is done.  So
4581          * we explicitly set the PHY values. */
4582         if (hw->mac_type == e1000_82571 ||
4583                 hw->mac_type == e1000_82572) {
4584                 hw->phy_id = IGP01E1000_I_PHY_ID;
4585                 hw->phy_type = e1000_phy_igp_2;
4586                 return E1000_SUCCESS;
4587         }
4588
4589         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4590          * work- around that forces PHY page 0 to be set or the reads fail.
4591          * The rest of the code in this routine uses e1000_read_phy_reg to
4592          * read the PHY ID.  So for ESB-2 we need to have this set so our
4593          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4594          * the routines below will figure this out as well. */
4595         if (hw->mac_type == e1000_80003es2lan)
4596                 hw->phy_type = e1000_phy_gg82563;
4597
4598         /* Read the PHY ID Registers to identify which PHY is onboard. */
4599         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4600         if (ret_val)
4601                 return ret_val;
4602
4603         hw->phy_id = (uint32_t) (phy_id_high << 16);
4604         udelay(20);
4605         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4606         if (ret_val)
4607                 return ret_val;
4608
4609         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4610         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4611
4612         switch (hw->mac_type) {
4613         case e1000_82543:
4614                 if (hw->phy_id == M88E1000_E_PHY_ID)
4615                         match = TRUE;
4616                 break;
4617         case e1000_82544:
4618                 if (hw->phy_id == M88E1000_I_PHY_ID)
4619                         match = TRUE;
4620                 break;
4621         case e1000_82540:
4622         case e1000_82545:
4623         case e1000_82545_rev_3:
4624         case e1000_82546:
4625         case e1000_82546_rev_3:
4626                 if (hw->phy_id == M88E1011_I_PHY_ID)
4627                         match = TRUE;
4628                 break;
4629         case e1000_82541:
4630         case e1000_82541_rev_2:
4631         case e1000_82547:
4632         case e1000_82547_rev_2:
4633                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4634                         match = TRUE;
4635
4636                 break;
4637         case e1000_82573:
4638                 if (hw->phy_id == M88E1111_I_PHY_ID)
4639                         match = TRUE;
4640                 break;
4641         case e1000_80003es2lan:
4642                 if (hw->phy_id == GG82563_E_PHY_ID)
4643                         match = TRUE;
4644                 break;
4645         case e1000_ich8lan:
4646                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4647                         match = TRUE;
4648                 if (hw->phy_id == IFE_E_PHY_ID)
4649                         match = TRUE;
4650                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4651                         match = TRUE;
4652                 if (hw->phy_id == IFE_C_E_PHY_ID)
4653                         match = TRUE;
4654                 break;
4655         default:
4656                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4657                 return -E1000_ERR_CONFIG;
4658         }
4659
4660         phy_init_status = e1000_set_phy_type(hw);
4661
4662         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4663                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4664                 return 0;
4665         }
4666         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4667         return -E1000_ERR_PHY;
4668 }
4669
4670 /*****************************************************************************
4671  * Set media type and TBI compatibility.
4672  *
4673  * hw - Struct containing variables accessed by shared code
4674  * **************************************************************************/
4675 void
4676 e1000_set_media_type(struct e1000_hw *hw)
4677 {
4678         uint32_t status;
4679
4680         DEBUGFUNC();
4681
4682         if (hw->mac_type != e1000_82543) {
4683                 /* tbi_compatibility is only valid on 82543 */
4684                 hw->tbi_compatibility_en = FALSE;
4685         }
4686
4687         switch (hw->device_id) {
4688         case E1000_DEV_ID_82545GM_SERDES:
4689         case E1000_DEV_ID_82546GB_SERDES:
4690         case E1000_DEV_ID_82571EB_SERDES:
4691         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4692         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4693         case E1000_DEV_ID_82572EI_SERDES:
4694         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4695                 hw->media_type = e1000_media_type_internal_serdes;
4696                 break;
4697         default:
4698                 switch (hw->mac_type) {
4699                 case e1000_82542_rev2_0:
4700                 case e1000_82542_rev2_1:
4701                         hw->media_type = e1000_media_type_fiber;
4702                         break;
4703                 case e1000_ich8lan:
4704                 case e1000_82573:
4705                         /* The STATUS_TBIMODE bit is reserved or reused
4706                          * for the this device.
4707                          */
4708                         hw->media_type = e1000_media_type_copper;
4709                         break;
4710                 default:
4711                         status = E1000_READ_REG(hw, STATUS);
4712                         if (status & E1000_STATUS_TBIMODE) {
4713                                 hw->media_type = e1000_media_type_fiber;
4714                                 /* tbi_compatibility not valid on fiber */
4715                                 hw->tbi_compatibility_en = FALSE;
4716                         } else {
4717                                 hw->media_type = e1000_media_type_copper;
4718                         }
4719                         break;
4720                 }
4721         }
4722 }
4723
4724 /**
4725  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4726  *
4727  * e1000_sw_init initializes the Adapter private data structure.
4728  * Fields are initialized based on PCI device information and
4729  * OS network device settings (MTU size).
4730  **/
4731
4732 static int
4733 e1000_sw_init(struct eth_device *nic, int cardnum)
4734 {
4735         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4736         int result;
4737
4738         /* PCI config space info */
4739         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4740         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4741         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4742                              &hw->subsystem_vendor_id);
4743         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4744
4745         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4746         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4747
4748         /* identify the MAC */
4749         result = e1000_set_mac_type(hw);
4750         if (result) {
4751                 E1000_ERR("Unknown MAC Type\n");
4752                 return result;
4753         }
4754
4755         switch (hw->mac_type) {
4756         default:
4757                 break;
4758         case e1000_82541:
4759         case e1000_82547:
4760         case e1000_82541_rev_2:
4761         case e1000_82547_rev_2:
4762                 hw->phy_init_script = 1;
4763                 break;
4764         }
4765
4766         /* lan a vs. lan b settings */
4767         if (hw->mac_type == e1000_82546)
4768                 /*this also works w/ multiple 82546 cards */
4769                 /*but not if they're intermingled /w other e1000s */
4770                 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
4771         else
4772                 hw->lan_loc = e1000_lan_a;
4773
4774         /* flow control settings */
4775         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4776         hw->fc_low_water = E1000_FC_LOW_THRESH;
4777         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4778         hw->fc_send_xon = 1;
4779
4780         /* Media type - copper or fiber */
4781         e1000_set_media_type(hw);
4782
4783         if (hw->mac_type >= e1000_82543) {
4784                 uint32_t status = E1000_READ_REG(hw, STATUS);
4785
4786                 if (status & E1000_STATUS_TBIMODE) {
4787                         DEBUGOUT("fiber interface\n");
4788                         hw->media_type = e1000_media_type_fiber;
4789                 } else {
4790                         DEBUGOUT("copper interface\n");
4791                         hw->media_type = e1000_media_type_copper;
4792                 }
4793         } else {
4794                 hw->media_type = e1000_media_type_fiber;
4795         }
4796
4797         hw->tbi_compatibility_en = TRUE;
4798         hw->wait_autoneg_complete = TRUE;
4799         if (hw->mac_type < e1000_82543)
4800                 hw->report_tx_early = 0;
4801         else
4802                 hw->report_tx_early = 1;
4803
4804         return E1000_SUCCESS;
4805 }
4806
4807 void
4808 fill_rx(struct e1000_hw *hw)
4809 {
4810         struct e1000_rx_desc *rd;
4811
4812         rx_last = rx_tail;
4813         rd = rx_base + rx_tail;
4814         rx_tail = (rx_tail + 1) % 8;
4815         memset(rd, 0, 16);
4816         rd->buffer_addr = cpu_to_le64((u32) & packet);
4817         E1000_WRITE_REG(hw, RDT, rx_tail);
4818 }
4819
4820 /**
4821  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4822  * @adapter: board private structure
4823  *
4824  * Configure the Tx unit of the MAC after a reset.
4825  **/
4826
4827 static void
4828 e1000_configure_tx(struct e1000_hw *hw)
4829 {
4830         unsigned long ptr;
4831         unsigned long tctl;
4832         unsigned long tipg, tarc;
4833         uint32_t ipgr1, ipgr2;
4834
4835         ptr = (u32) tx_pool;
4836         if (ptr & 0xf)
4837                 ptr = (ptr + 0x10) & (~0xf);
4838
4839         tx_base = (typeof(tx_base)) ptr;
4840
4841         E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4842         E1000_WRITE_REG(hw, TDBAH, 0);
4843
4844         E1000_WRITE_REG(hw, TDLEN, 128);
4845
4846         /* Setup the HW Tx Head and Tail descriptor pointers */
4847         E1000_WRITE_REG(hw, TDH, 0);
4848         E1000_WRITE_REG(hw, TDT, 0);
4849         tx_tail = 0;
4850
4851         /* Set the default values for the Tx Inter Packet Gap timer */
4852         if (hw->mac_type <= e1000_82547_rev_2 &&
4853             (hw->media_type == e1000_media_type_fiber ||
4854              hw->media_type == e1000_media_type_internal_serdes))
4855                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4856         else
4857                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4858
4859         /* Set the default values for the Tx Inter Packet Gap timer */
4860         switch (hw->mac_type) {
4861         case e1000_82542_rev2_0:
4862         case e1000_82542_rev2_1:
4863                 tipg = DEFAULT_82542_TIPG_IPGT;
4864                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4865                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4866                 break;
4867         case e1000_80003es2lan:
4868                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4869                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4870                 break;
4871         default:
4872                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4873                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4874                 break;
4875         }
4876         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4877         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4878         E1000_WRITE_REG(hw, TIPG, tipg);
4879         /* Program the Transmit Control Register */
4880         tctl = E1000_READ_REG(hw, TCTL);
4881         tctl &= ~E1000_TCTL_CT;
4882         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4883             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4884
4885         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4886                 tarc = E1000_READ_REG(hw, TARC0);
4887                 /* set the speed mode bit, we'll clear it if we're not at
4888                  * gigabit link later */
4889                 /* git bit can be set to 1*/
4890         } else if (hw->mac_type == e1000_80003es2lan) {
4891                 tarc = E1000_READ_REG(hw, TARC0);
4892                 tarc |= 1;
4893                 E1000_WRITE_REG(hw, TARC0, tarc);
4894                 tarc = E1000_READ_REG(hw, TARC1);
4895                 tarc |= 1;
4896                 E1000_WRITE_REG(hw, TARC1, tarc);
4897         }
4898
4899
4900         e1000_config_collision_dist(hw);
4901         /* Setup Transmit Descriptor Settings for eop descriptor */
4902         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4903
4904         /* Need to set up RS bit */
4905         if (hw->mac_type < e1000_82543)
4906                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4907         else
4908                 hw->txd_cmd |= E1000_TXD_CMD_RS;
4909         E1000_WRITE_REG(hw, TCTL, tctl);
4910 }
4911
4912 /**
4913  * e1000_setup_rctl - configure the receive control register
4914  * @adapter: Board private structure
4915  **/
4916 static void
4917 e1000_setup_rctl(struct e1000_hw *hw)
4918 {
4919         uint32_t rctl;
4920
4921         rctl = E1000_READ_REG(hw, RCTL);
4922
4923         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4924
4925         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4926                 | E1000_RCTL_RDMTS_HALF;        /* |
4927                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4928
4929         if (hw->tbi_compatibility_on == 1)
4930                 rctl |= E1000_RCTL_SBP;
4931         else
4932                 rctl &= ~E1000_RCTL_SBP;
4933
4934         rctl &= ~(E1000_RCTL_SZ_4096);
4935                 rctl |= E1000_RCTL_SZ_2048;
4936                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4937         E1000_WRITE_REG(hw, RCTL, rctl);
4938 }
4939
4940 /**
4941  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4942  * @adapter: board private structure
4943  *
4944  * Configure the Rx unit of the MAC after a reset.
4945  **/
4946 static void
4947 e1000_configure_rx(struct e1000_hw *hw)
4948 {
4949         unsigned long ptr;
4950         unsigned long rctl, ctrl_ext;
4951         rx_tail = 0;
4952         /* make sure receives are disabled while setting up the descriptors */
4953         rctl = E1000_READ_REG(hw, RCTL);
4954         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4955         if (hw->mac_type >= e1000_82540) {
4956                 /* Set the interrupt throttling rate.  Value is calculated
4957                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4958 #define MAX_INTS_PER_SEC        8000
4959 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
4960                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4961         }
4962
4963         if (hw->mac_type >= e1000_82571) {
4964                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4965                 /* Reset delay timers after every interrupt */
4966                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4967                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4968                 E1000_WRITE_FLUSH(hw);
4969         }
4970         /* Setup the Base and Length of the Rx Descriptor Ring */
4971         ptr = (u32) rx_pool;
4972         if (ptr & 0xf)
4973                 ptr = (ptr + 0x10) & (~0xf);
4974         rx_base = (typeof(rx_base)) ptr;
4975         E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
4976         E1000_WRITE_REG(hw, RDBAH, 0);
4977
4978         E1000_WRITE_REG(hw, RDLEN, 128);
4979
4980         /* Setup the HW Rx Head and Tail Descriptor Pointers */
4981         E1000_WRITE_REG(hw, RDH, 0);
4982         E1000_WRITE_REG(hw, RDT, 0);
4983         /* Enable Receives */
4984
4985         E1000_WRITE_REG(hw, RCTL, rctl);
4986         fill_rx(hw);
4987 }
4988
4989 /**************************************************************************
4990 POLL - Wait for a frame
4991 ***************************************************************************/
4992 static int
4993 e1000_poll(struct eth_device *nic)
4994 {
4995         struct e1000_hw *hw = nic->priv;
4996         struct e1000_rx_desc *rd;
4997         /* return true if there's an ethernet packet ready to read */
4998         rd = rx_base + rx_last;
4999         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5000                 return 0;
5001         /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5002         NetReceive((uchar *)packet, le32_to_cpu(rd->length));
5003         fill_rx(hw);
5004         return 1;
5005 }
5006
5007 /**************************************************************************
5008 TRANSMIT - Transmit a frame
5009 ***************************************************************************/
5010 static int
5011 e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
5012 {
5013         struct e1000_hw *hw = nic->priv;
5014         struct e1000_tx_desc *txp;
5015         int i = 0;
5016
5017         txp = tx_base + tx_tail;
5018         tx_tail = (tx_tail + 1) % 8;
5019
5020         txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
5021         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5022         txp->upper.data = 0;
5023         E1000_WRITE_REG(hw, TDT, tx_tail);
5024
5025         E1000_WRITE_FLUSH(hw);
5026         while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5027                 if (i++ > TOUT_LOOP) {
5028                         DEBUGOUT("e1000: tx timeout\n");
5029                         return 0;
5030                 }
5031                 udelay(10);     /* give the nic a chance to write to the register */
5032         }
5033         return 1;
5034 }
5035
5036 /*reset function*/
5037 static inline int
5038 e1000_reset(struct eth_device *nic)
5039 {
5040         struct e1000_hw *hw = nic->priv;
5041
5042         e1000_reset_hw(hw);
5043         if (hw->mac_type >= e1000_82544) {
5044                 E1000_WRITE_REG(hw, WUC, 0);
5045         }
5046         return e1000_init_hw(nic);
5047 }
5048
5049 /**************************************************************************
5050 DISABLE - Turn off ethernet interface
5051 ***************************************************************************/
5052 static void
5053 e1000_disable(struct eth_device *nic)
5054 {
5055         struct e1000_hw *hw = nic->priv;
5056
5057         /* Turn off the ethernet interface */
5058         E1000_WRITE_REG(hw, RCTL, 0);
5059         E1000_WRITE_REG(hw, TCTL, 0);
5060
5061         /* Clear the transmit ring */
5062         E1000_WRITE_REG(hw, TDH, 0);
5063         E1000_WRITE_REG(hw, TDT, 0);
5064
5065         /* Clear the receive ring */
5066         E1000_WRITE_REG(hw, RDH, 0);
5067         E1000_WRITE_REG(hw, RDT, 0);
5068
5069         /* put the card in its initial state */
5070 #if 0
5071         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5072 #endif
5073         mdelay(10);
5074
5075 }
5076
5077 /**************************************************************************
5078 INIT - set up ethernet interface(s)
5079 ***************************************************************************/
5080 static int
5081 e1000_init(struct eth_device *nic, bd_t * bis)
5082 {
5083         struct e1000_hw *hw = nic->priv;
5084         int ret_val = 0;
5085
5086         ret_val = e1000_reset(nic);
5087         if (ret_val < 0) {
5088                 if ((ret_val == -E1000_ERR_NOLINK) ||
5089                     (ret_val == -E1000_ERR_TIMEOUT)) {
5090                         E1000_ERR("Valid Link not detected\n");
5091                 } else {
5092                         E1000_ERR("Hardware Initialization Failed\n");
5093                 }
5094                 return 0;
5095         }
5096         e1000_configure_tx(hw);
5097         e1000_setup_rctl(hw);
5098         e1000_configure_rx(hw);
5099         return 1;
5100 }
5101
5102 /******************************************************************************
5103  * Gets the current PCI bus type of hardware
5104  *
5105  * hw - Struct containing variables accessed by shared code
5106  *****************************************************************************/
5107 void e1000_get_bus_type(struct e1000_hw *hw)
5108 {
5109         uint32_t status;
5110
5111         switch (hw->mac_type) {
5112         case e1000_82542_rev2_0:
5113         case e1000_82542_rev2_1:
5114                 hw->bus_type = e1000_bus_type_pci;
5115                 break;
5116         case e1000_82571:
5117         case e1000_82572:
5118         case e1000_82573:
5119         case e1000_80003es2lan:
5120                 hw->bus_type = e1000_bus_type_pci_express;
5121                 break;
5122         case e1000_ich8lan:
5123                 hw->bus_type = e1000_bus_type_pci_express;
5124                 break;
5125         default:
5126                 status = E1000_READ_REG(hw, STATUS);
5127                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5128                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5129                 break;
5130         }
5131 }
5132
5133 /**************************************************************************
5134 PROBE - Look for an adapter, this routine's visible to the outside
5135 You should omit the last argument struct pci_device * for a non-PCI NIC
5136 ***************************************************************************/
5137 int
5138 e1000_initialize(bd_t * bis)
5139 {
5140         pci_dev_t devno;
5141         int card_number = 0;
5142         struct eth_device *nic = NULL;
5143         struct e1000_hw *hw = NULL;
5144         u32 iobase;
5145         int idx = 0;
5146         u32 PciCommandWord;
5147
5148         while (1) {             /* Find PCI device(s) */
5149                 if ((devno = pci_find_devices(supported, idx++)) < 0) {
5150                         break;
5151                 }
5152
5153                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
5154                 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
5155                 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
5156
5157                 pci_write_config_dword(devno, PCI_COMMAND,
5158                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
5159                 /* Check if I/O accesses and Bus Mastering are enabled. */
5160                 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
5161                 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
5162                         printf("Error: Can not enable MEM access.\n");
5163                         continue;
5164                 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
5165                         printf("Error: Can not enable Bus Mastering.\n");
5166                         continue;
5167                 }
5168
5169                 nic = (struct eth_device *) malloc(sizeof (*nic));
5170                 hw = (struct e1000_hw *) malloc(sizeof (*hw));
5171                 hw->pdev = devno;
5172                 nic->priv = hw;
5173                 nic->iobase = bus_to_phys(devno, iobase);
5174
5175                 sprintf(nic->name, "e1000#%d", card_number);
5176
5177                 /* Are these variables needed? */
5178                 hw->fc = e1000_fc_default;
5179                 hw->original_fc = e1000_fc_default;
5180                 hw->autoneg_failed = 0;
5181                 hw->autoneg = 1;
5182                 hw->get_link_status = TRUE;
5183                 hw->hw_addr = (typeof(hw->hw_addr)) iobase;
5184                 hw->mac_type = e1000_undefined;
5185
5186                 /* MAC and Phy settings */
5187                 if (e1000_sw_init(nic, card_number) < 0) {
5188                         free(hw);
5189                         free(nic);
5190                         return 0;
5191                 }
5192                 if (e1000_check_phy_reset_block(hw))
5193                         printf("phy reset block error \n");
5194                 e1000_reset_hw(hw);
5195 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
5196                 if (e1000_init_eeprom_params(hw)) {
5197                         printf("The EEPROM Checksum Is Not Valid\n");
5198                         free(hw);
5199                         free(nic);
5200                         return 0;
5201                 }
5202                 if (e1000_validate_eeprom_checksum(nic) < 0) {
5203                         printf("The EEPROM Checksum Is Not Valid\n");
5204                         free(hw);
5205                         free(nic);
5206                         return 0;
5207                 }
5208 #endif
5209                 e1000_read_mac_addr(nic);
5210
5211                 /* get the bus type information */
5212                 e1000_get_bus_type(hw);
5213
5214                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
5215                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5216                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5217
5218                 nic->init = e1000_init;
5219                 nic->recv = e1000_poll;
5220                 nic->send = e1000_transmit;
5221                 nic->halt = e1000_disable;
5222
5223                 eth_register(nic);
5224
5225                 card_number++;
5226         }
5227         return card_number;
5228 }