drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms of the GNU General Public License as published by the Free
  14   Software Foundation; either version 2 of the License, or (at your option)
  15   any later version.
  16
  17   This program is distributed in the hope that it will be useful, but WITHOUT
  18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20   more details.
  21
  22   You should have received a copy of the GNU General Public License along with
  23   this program; if not, write to the Free Software Foundation, Inc., 59
  24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25
  26   The full GNU General Public License is included in this distribution in the
  27   file called LICENSE.
  28
  29   Contact Information:
  30   Linux NICS <linux.nics@intel.com>
  31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32
  33 *******************************************************************************/
  34 /*
  35  *  Copyright (C) Archway Digital Solutions.
  36  *
  37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  38  *  2/9/2002
  39  *
  40  *  Copyright (C) Linux Networx.
  41  *  Massive upgrade to work with the new intel gigabit NICs.
  42  *  <ebiederman at lnxi dot com>
  43  *
  44  *  Copyright 2011 Freescale Semiconductor, Inc.
  45  */
  46
  47 #include "e1000.h"
  48
  49 #define TOUT_LOOP   100000
  50
  51 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  52 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  53
  54 #define E1000_DEFAULT_PCI_PBA   0x00000030
  55 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  56
  57 /* NIC specific static variables go here */
  58
  59 static char tx_pool[128 + 16];
  60 static char rx_pool[128 + 16];
  61 static char packet[2096];
  62
  63 static struct e1000_tx_desc *tx_base;
  64 static struct e1000_rx_desc *rx_base;
  65
  66 static int tx_tail;
  67 static int rx_tail, rx_last;
  68
  69 static struct pci_device_id supported[] = {
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  72         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  87         /* E1000 PCIe card */
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
 103         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
 104         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
 105         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
 106         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
 107         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
 108         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
 109         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
 110         {}
 111 };
 112
 113 /* Function forward declarations */
 114 static int e1000_setup_link(struct eth_device *nic);
 115 static int e1000_setup_fiber_link(struct eth_device *nic);
 116 static int e1000_setup_copper_link(struct eth_device *nic);
 117 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 118 static void e1000_config_collision_dist(struct e1000_hw *hw);
 119 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 120 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 121 static int e1000_check_for_link(struct eth_device *nic);
 122 static int e1000_wait_autoneg(struct e1000_hw *hw);
 123 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 124                                        uint16_t * duplex);
 125 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 126                               uint16_t * phy_data);
 127 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 128                                uint16_t phy_data);
 129 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 130 static int e1000_phy_reset(struct e1000_hw *hw);
 131 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 132 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 133 static void e1000_set_media_type(struct e1000_hw *hw);
 134
 135 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 136 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 137 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
 138 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
 139 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
 140                         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
 141 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
 142         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
 143 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
 144
 145 #ifndef CONFIG_AP1000 /* remove for warnings */
 146 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 147                 uint16_t words,
 148                 uint16_t *data);
 149 /******************************************************************************
 150  * Raises the EEPROM's clock input.
 151  *
 152  * hw - Struct containing variables accessed by shared code
 153  * eecd - EECD's current value
 154  *****************************************************************************/
 155 static void
 156 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 157 {
 158         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 159          * wait 50 microseconds.
 160          */
 161         *eecd = *eecd | E1000_EECD_SK;
 162         E1000_WRITE_REG(hw, EECD, *eecd);
 163         E1000_WRITE_FLUSH(hw);
 164         udelay(50);
 165 }
 166
 167 /******************************************************************************
 168  * Lowers the EEPROM's clock input.
 169  *
 170  * hw - Struct containing variables accessed by shared code
 171  * eecd - EECD's current value
 172  *****************************************************************************/
 173 static void
 174 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 175 {
 176         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 177          * wait 50 microseconds.
 178          */
 179         *eecd = *eecd & ~E1000_EECD_SK;
 180         E1000_WRITE_REG(hw, EECD, *eecd);
 181         E1000_WRITE_FLUSH(hw);
 182         udelay(50);
 183 }
 184
 185 /******************************************************************************
 186  * Shift data bits out to the EEPROM.
 187  *
 188  * hw - Struct containing variables accessed by shared code
 189  * data - data to send to the EEPROM
 190  * count - number of bits to shift out
 191  *****************************************************************************/
 192 static void
 193 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 194 {
 195         uint32_t eecd;
 196         uint32_t mask;
 197
 198         /* We need to shift "count" bits out to the EEPROM. So, value in the
 199          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 200          * In order to do this, "data" must be broken down into bits.
 201          */
 202         mask = 0x01 << (count - 1);
 203         eecd = E1000_READ_REG(hw, EECD);
 204         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 205         do {
 206                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 207                  * and then raising and then lowering the clock (the SK bit controls
 208                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 209                  * by setting "DI" to "0" and then raising and then lowering the clock.
 210                  */
 211                 eecd &= ~E1000_EECD_DI;
 212
 213                 if (data & mask)
 214                         eecd |= E1000_EECD_DI;
 215
 216                 E1000_WRITE_REG(hw, EECD, eecd);
 217                 E1000_WRITE_FLUSH(hw);
 218
 219                 udelay(50);
 220
 221                 e1000_raise_ee_clk(hw, &eecd);
 222                 e1000_lower_ee_clk(hw, &eecd);
 223
 224                 mask = mask >> 1;
 225
 226         } while (mask);
 227
 228         /* We leave the "DI" bit set to "0" when we leave this routine. */
 229         eecd &= ~E1000_EECD_DI;
 230         E1000_WRITE_REG(hw, EECD, eecd);
 231 }
 232
 233 /******************************************************************************
 234  * Shift data bits in from the EEPROM
 235  *
 236  * hw - Struct containing variables accessed by shared code
 237  *****************************************************************************/
 238 static uint16_t
 239 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 240 {
 241         uint32_t eecd;
 242         uint32_t i;
 243         uint16_t data;
 244
 245         /* In order to read a register from the EEPROM, we need to shift 'count'
 246          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 247          * input to the EEPROM (setting the SK bit), and then reading the
 248          * value of the "DO" bit.  During this "shifting in" process the
 249          * "DI" bit should always be clear.
 250          */
 251
 252         eecd = E1000_READ_REG(hw, EECD);
 253
 254         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 255         data = 0;
 256
 257         for (i = 0; i < count; i++) {
 258                 data = data << 1;
 259                 e1000_raise_ee_clk(hw, &eecd);
 260
 261                 eecd = E1000_READ_REG(hw, EECD);
 262
 263                 eecd &= ~(E1000_EECD_DI);
 264                 if (eecd & E1000_EECD_DO)
 265                         data |= 1;
 266
 267                 e1000_lower_ee_clk(hw, &eecd);
 268         }
 269
 270         return data;
 271 }
 272
 273 /******************************************************************************
 274  * Returns EEPROM to a "standby" state
 275  *
 276  * hw - Struct containing variables accessed by shared code
 277  *****************************************************************************/
 278 static void
 279 e1000_standby_eeprom(struct e1000_hw *hw)
 280 {
 281         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 282         uint32_t eecd;
 283
 284         eecd = E1000_READ_REG(hw, EECD);
 285
 286         if (eeprom->type == e1000_eeprom_microwire) {
 287                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 288                 E1000_WRITE_REG(hw, EECD, eecd);
 289                 E1000_WRITE_FLUSH(hw);
 290                 udelay(eeprom->delay_usec);
 291
 292                 /* Clock high */
 293                 eecd |= E1000_EECD_SK;
 294                 E1000_WRITE_REG(hw, EECD, eecd);
 295                 E1000_WRITE_FLUSH(hw);
 296                 udelay(eeprom->delay_usec);
 297
 298                 /* Select EEPROM */
 299                 eecd |= E1000_EECD_CS;
 300                 E1000_WRITE_REG(hw, EECD, eecd);
 301                 E1000_WRITE_FLUSH(hw);
 302                 udelay(eeprom->delay_usec);
 303
 304                 /* Clock low */
 305                 eecd &= ~E1000_EECD_SK;
 306                 E1000_WRITE_REG(hw, EECD, eecd);
 307                 E1000_WRITE_FLUSH(hw);
 308                 udelay(eeprom->delay_usec);
 309         } else if (eeprom->type == e1000_eeprom_spi) {
 310                 /* Toggle CS to flush commands */
 311                 eecd |= E1000_EECD_CS;
 312                 E1000_WRITE_REG(hw, EECD, eecd);
 313                 E1000_WRITE_FLUSH(hw);
 314                 udelay(eeprom->delay_usec);
 315                 eecd &= ~E1000_EECD_CS;
 316                 E1000_WRITE_REG(hw, EECD, eecd);
 317                 E1000_WRITE_FLUSH(hw);
 318                 udelay(eeprom->delay_usec);
 319         }
 320 }
 321
 322 /***************************************************************************
 323 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 324 *
 325 * hw - Struct containing variables accessed by shared code
 326 ****************************************************************************/
 327 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 328 {
 329         uint32_t eecd = 0;
 330
 331         DEBUGFUNC();
 332
 333         if (hw->mac_type == e1000_ich8lan)
 334                 return FALSE;
 335
 336         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 337                 eecd = E1000_READ_REG(hw, EECD);
 338
 339                 /* Isolate bits 15 & 16 */
 340                 eecd = ((eecd >> 15) & 0x03);
 341
 342                 /* If both bits are set, device is Flash type */
 343                 if (eecd == 0x03)
 344                         return FALSE;
 345         }
 346         return TRUE;
 347 }
 348
 349 /******************************************************************************
 350  * Prepares EEPROM for access
 351  *
 352  * hw - Struct containing variables accessed by shared code
 353  *
 354  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 355  * function should be called before issuing a command to the EEPROM.
 356  *****************************************************************************/
 357 static int32_t
 358 e1000_acquire_eeprom(struct e1000_hw *hw)
 359 {
 360         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 361         uint32_t eecd, i = 0;
 362
 363         DEBUGFUNC();
 364
 365         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 366                 return -E1000_ERR_SWFW_SYNC;
 367         eecd = E1000_READ_REG(hw, EECD);
 368
 369         if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
 370                 /* Request EEPROM Access */
 371                 if (hw->mac_type > e1000_82544) {
 372                         eecd |= E1000_EECD_REQ;
 373                         E1000_WRITE_REG(hw, EECD, eecd);
 374                         eecd = E1000_READ_REG(hw, EECD);
 375                         while ((!(eecd & E1000_EECD_GNT)) &&
 376                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 377                                 i++;
 378                                 udelay(5);
 379                                 eecd = E1000_READ_REG(hw, EECD);
 380                         }
 381                         if (!(eecd & E1000_EECD_GNT)) {
 382                                 eecd &= ~E1000_EECD_REQ;
 383                                 E1000_WRITE_REG(hw, EECD, eecd);
 384                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 385                                 return -E1000_ERR_EEPROM;
 386                         }
 387                 }
 388         }
 389
 390         /* Setup EEPROM for Read/Write */
 391
 392         if (eeprom->type == e1000_eeprom_microwire) {
 393                 /* Clear SK and DI */
 394                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 395                 E1000_WRITE_REG(hw, EECD, eecd);
 396
 397                 /* Set CS */
 398                 eecd |= E1000_EECD_CS;
 399                 E1000_WRITE_REG(hw, EECD, eecd);
 400         } else if (eeprom->type == e1000_eeprom_spi) {
 401                 /* Clear SK and CS */
 402                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 403                 E1000_WRITE_REG(hw, EECD, eecd);
 404                 udelay(1);
 405         }
 406
 407         return E1000_SUCCESS;
 408 }
 409
 410 /******************************************************************************
 411  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 412  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 413  * registers must be mapped, or this will crash.
 414  *
 415  * hw - Struct containing variables accessed by shared code
 416  *****************************************************************************/
 417 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 418 {
 419         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 420         uint32_t eecd = E1000_READ_REG(hw, EECD);
 421         int32_t ret_val = E1000_SUCCESS;
 422         uint16_t eeprom_size;
 423
 424         DEBUGFUNC();
 425
 426         switch (hw->mac_type) {
 427         case e1000_82542_rev2_0:
 428         case e1000_82542_rev2_1:
 429         case e1000_82543:
 430         case e1000_82544:
 431                 eeprom->type = e1000_eeprom_microwire;
 432                 eeprom->word_size = 64;
 433                 eeprom->opcode_bits = 3;
 434                 eeprom->address_bits = 6;
 435                 eeprom->delay_usec = 50;
 436                 eeprom->use_eerd = FALSE;
 437                 eeprom->use_eewr = FALSE;
 438         break;
 439         case e1000_82540:
 440         case e1000_82545:
 441         case e1000_82545_rev_3:
 442         case e1000_82546:
 443         case e1000_82546_rev_3:
 444                 eeprom->type = e1000_eeprom_microwire;
 445                 eeprom->opcode_bits = 3;
 446                 eeprom->delay_usec = 50;
 447                 if (eecd & E1000_EECD_SIZE) {
 448                         eeprom->word_size = 256;
 449                         eeprom->address_bits = 8;
 450                 } else {
 451                         eeprom->word_size = 64;
 452                         eeprom->address_bits = 6;
 453                 }
 454                 eeprom->use_eerd = FALSE;
 455                 eeprom->use_eewr = FALSE;
 456                 break;
 457         case e1000_82541:
 458         case e1000_82541_rev_2:
 459         case e1000_82547:
 460         case e1000_82547_rev_2:
 461                 if (eecd & E1000_EECD_TYPE) {
 462                         eeprom->type = e1000_eeprom_spi;
 463                         eeprom->opcode_bits = 8;
 464                         eeprom->delay_usec = 1;
 465                         if (eecd & E1000_EECD_ADDR_BITS) {
 466                                 eeprom->page_size = 32;
 467                                 eeprom->address_bits = 16;
 468                         } else {
 469                                 eeprom->page_size = 8;
 470                                 eeprom->address_bits = 8;
 471                         }
 472                 } else {
 473                         eeprom->type = e1000_eeprom_microwire;
 474                         eeprom->opcode_bits = 3;
 475                         eeprom->delay_usec = 50;
 476                         if (eecd & E1000_EECD_ADDR_BITS) {
 477                                 eeprom->word_size = 256;
 478                                 eeprom->address_bits = 8;
 479                         } else {
 480                                 eeprom->word_size = 64;
 481                                 eeprom->address_bits = 6;
 482                         }
 483                 }
 484                 eeprom->use_eerd = FALSE;
 485                 eeprom->use_eewr = FALSE;
 486                 break;
 487         case e1000_82571:
 488         case e1000_82572:
 489                 eeprom->type = e1000_eeprom_spi;
 490                 eeprom->opcode_bits = 8;
 491                 eeprom->delay_usec = 1;
 492                 if (eecd & E1000_EECD_ADDR_BITS) {
 493                         eeprom->page_size = 32;
 494                         eeprom->address_bits = 16;
 495                 } else {
 496                         eeprom->page_size = 8;
 497                         eeprom->address_bits = 8;
 498                 }
 499                 eeprom->use_eerd = FALSE;
 500                 eeprom->use_eewr = FALSE;
 501                 break;
 502         case e1000_82573:
 503         case e1000_82574:
 504                 eeprom->type = e1000_eeprom_spi;
 505                 eeprom->opcode_bits = 8;
 506                 eeprom->delay_usec = 1;
 507                 if (eecd & E1000_EECD_ADDR_BITS) {
 508                         eeprom->page_size = 32;
 509                         eeprom->address_bits = 16;
 510                 } else {
 511                         eeprom->page_size = 8;
 512                         eeprom->address_bits = 8;
 513                 }
 514                 eeprom->use_eerd = TRUE;
 515                 eeprom->use_eewr = TRUE;
 516                 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
 517                         eeprom->type = e1000_eeprom_flash;
 518                         eeprom->word_size = 2048;
 519
 520                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 521                  * Flash update issue on parts which use a FLASH for NVM. */
 522                         eecd &= ~E1000_EECD_AUPDEN;
 523                         E1000_WRITE_REG(hw, EECD, eecd);
 524                 }
 525                 break;
 526         case e1000_80003es2lan:
 527                 eeprom->type = e1000_eeprom_spi;
 528                 eeprom->opcode_bits = 8;
 529                 eeprom->delay_usec = 1;
 530                 if (eecd & E1000_EECD_ADDR_BITS) {
 531                         eeprom->page_size = 32;
 532                         eeprom->address_bits = 16;
 533                 } else {
 534                         eeprom->page_size = 8;
 535                         eeprom->address_bits = 8;
 536                 }
 537                 eeprom->use_eerd = TRUE;
 538                 eeprom->use_eewr = FALSE;
 539                 break;
 540
 541         /* ich8lan does not support currently. if needed, please
 542          * add corresponding code and functions.
 543          */
 544 #if 0
 545         case e1000_ich8lan:
 546                 {
 547                 int32_t  i = 0;
 548
 549                 eeprom->type = e1000_eeprom_ich8;
 550                 eeprom->use_eerd = FALSE;
 551                 eeprom->use_eewr = FALSE;
 552                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 553                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 554                                 ICH_FLASH_GFPREG);
 555                 /* Zero the shadow RAM structure. But don't load it from NVM
 556                  * so as to save time for driver init */
 557                 if (hw->eeprom_shadow_ram != NULL) {
 558                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 559                                 hw->eeprom_shadow_ram[i].modified = FALSE;
 560                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 561                         }
 562                 }
 563
 564                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 565                                 ICH_FLASH_SECTOR_SIZE;
 566
 567                 hw->flash_bank_size = ((flash_size >> 16)
 568                                 & ICH_GFPREG_BASE_MASK) + 1;
 569                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 570
 571                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 572
 573                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 574                 break;
 575                 }
 576 #endif
 577         default:
 578                 break;
 579         }
 580
 581         if (eeprom->type == e1000_eeprom_spi) {
 582                 /* eeprom_size will be an enum [0..8] that maps
 583                  * to eeprom sizes 128B to
 584                  * 32KB (incremented by powers of 2).
 585                  */
 586                 if (hw->mac_type <= e1000_82547_rev_2) {
 587                         /* Set to default value for initial eeprom read. */
 588                         eeprom->word_size = 64;
 589                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 590                                         &eeprom_size);
 591                         if (ret_val)
 592                                 return ret_val;
 593                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 594                                 >> EEPROM_SIZE_SHIFT;
 595                         /* 256B eeprom size was not supported in earlier
 596                          * hardware, so we bump eeprom_size up one to
 597                          * ensure that "1" (which maps to 256B) is never
 598                          * the result used in the shifting logic below. */
 599                         if (eeprom_size)
 600                                 eeprom_size++;
 601                 } else {
 602                         eeprom_size = (uint16_t)((eecd &
 603                                 E1000_EECD_SIZE_EX_MASK) >>
 604                                 E1000_EECD_SIZE_EX_SHIFT);
 605                 }
 606
 607                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 608         }
 609         return ret_val;
 610 }
 611
 612 /******************************************************************************
 613  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 614  *
 615  * hw - Struct containing variables accessed by shared code
 616  *****************************************************************************/
 617 static int32_t
 618 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 619 {
 620         uint32_t attempts = 100000;
 621         uint32_t i, reg = 0;
 622         int32_t done = E1000_ERR_EEPROM;
 623
 624         for (i = 0; i < attempts; i++) {
 625                 if (eerd == E1000_EEPROM_POLL_READ)
 626                         reg = E1000_READ_REG(hw, EERD);
 627                 else
 628                         reg = E1000_READ_REG(hw, EEWR);
 629
 630                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 631                         done = E1000_SUCCESS;
 632                         break;
 633                 }
 634                 udelay(5);
 635         }
 636
 637         return done;
 638 }
 639
 640 /******************************************************************************
 641  * Reads a 16 bit word from the EEPROM using the EERD register.
 642  *
 643  * hw - Struct containing variables accessed by shared code
 644  * offset - offset of  word in the EEPROM to read
 645  * data - word read from the EEPROM
 646  * words - number of words to read
 647  *****************************************************************************/
 648 static int32_t
 649 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 650                         uint16_t offset,
 651                         uint16_t words,
 652                         uint16_t *data)
 653 {
 654         uint32_t i, eerd = 0;
 655         int32_t error = 0;
 656
 657         for (i = 0; i < words; i++) {
 658                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 659                         E1000_EEPROM_RW_REG_START;
 660
 661                 E1000_WRITE_REG(hw, EERD, eerd);
 662                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 663
 664                 if (error)
 665                         break;
 666                 data[i] = (E1000_READ_REG(hw, EERD) >>
 667                                 E1000_EEPROM_RW_REG_DATA);
 668
 669         }
 670
 671         return error;
 672 }
 673
 674 static void
 675 e1000_release_eeprom(struct e1000_hw *hw)
 676 {
 677         uint32_t eecd;
 678
 679         DEBUGFUNC();
 680
 681         eecd = E1000_READ_REG(hw, EECD);
 682
 683         if (hw->eeprom.type == e1000_eeprom_spi) {
 684                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 685                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 686
 687                 E1000_WRITE_REG(hw, EECD, eecd);
 688
 689                 udelay(hw->eeprom.delay_usec);
 690         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 691                 /* cleanup eeprom */
 692
 693                 /* CS on Microwire is active-high */
 694                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 695
 696                 E1000_WRITE_REG(hw, EECD, eecd);
 697
 698                 /* Rising edge of clock */
 699                 eecd |= E1000_EECD_SK;
 700                 E1000_WRITE_REG(hw, EECD, eecd);
 701                 E1000_WRITE_FLUSH(hw);
 702                 udelay(hw->eeprom.delay_usec);
 703
 704                 /* Falling edge of clock */
 705                 eecd &= ~E1000_EECD_SK;
 706                 E1000_WRITE_REG(hw, EECD, eecd);
 707                 E1000_WRITE_FLUSH(hw);
 708                 udelay(hw->eeprom.delay_usec);
 709         }
 710
 711         /* Stop requesting EEPROM access */
 712         if (hw->mac_type > e1000_82544) {
 713                 eecd &= ~E1000_EECD_REQ;
 714                 E1000_WRITE_REG(hw, EECD, eecd);
 715         }
 716 }
 717 /******************************************************************************
 718  * Reads a 16 bit word from the EEPROM.
 719  *
 720  * hw - Struct containing variables accessed by shared code
 721  *****************************************************************************/
 722 static int32_t
 723 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 724 {
 725         uint16_t retry_count = 0;
 726         uint8_t spi_stat_reg;
 727
 728         DEBUGFUNC();
 729
 730         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 731          * EEPROM will signal that the command has been completed by clearing
 732          * bit 0 of the internal status register.  If it's not cleared within
 733          * 5 milliseconds, then error out.
 734          */
 735         retry_count = 0;
 736         do {
 737                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 738                         hw->eeprom.opcode_bits);
 739                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 740                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 741                         break;
 742
 743                 udelay(5);
 744                 retry_count += 5;
 745
 746                 e1000_standby_eeprom(hw);
 747         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 748
 749         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 750          * only 0-5mSec on 5V devices)
 751          */
 752         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 753                 DEBUGOUT("SPI EEPROM Status error\n");
 754                 return -E1000_ERR_EEPROM;
 755         }
 756
 757         return E1000_SUCCESS;
 758 }
 759
 760 /******************************************************************************
 761  * Reads a 16 bit word from the EEPROM.
 762  *
 763  * hw - Struct containing variables accessed by shared code
 764  * offset - offset of  word in the EEPROM to read
 765  * data - word read from the EEPROM
 766  *****************************************************************************/
 767 static int32_t
 768 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 769                 uint16_t words, uint16_t *data)
 770 {
 771         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 772         uint32_t i = 0;
 773
 774         DEBUGFUNC();
 775
 776         /* If eeprom is not yet detected, do so now */
 777         if (eeprom->word_size == 0)
 778                 e1000_init_eeprom_params(hw);
 779
 780         /* A check for invalid values:  offset too large, too many words,
 781          * and not enough words.
 782          */
 783         if ((offset >= eeprom->word_size) ||
 784                 (words > eeprom->word_size - offset) ||
 785                 (words == 0)) {
 786                 DEBUGOUT("\"words\" parameter out of bounds."
 787                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 788                 return -E1000_ERR_EEPROM;
 789         }
 790
 791         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 792          * directly. In this case, we need to acquire the EEPROM so that
 793          * FW or other port software does not interrupt.
 794          */
 795         if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
 796                 hw->eeprom.use_eerd == FALSE) {
 797
 798                 /* Prepare the EEPROM for bit-bang reading */
 799                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 800                         return -E1000_ERR_EEPROM;
 801         }
 802
 803         /* Eerd register EEPROM access requires no eeprom aquire/release */
 804         if (eeprom->use_eerd == TRUE)
 805                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 806
 807         /* ich8lan does not support currently. if needed, please
 808          * add corresponding code and functions.
 809          */
 810 #if 0
 811         /* ICH EEPROM access is done via the ICH flash controller */
 812         if (eeprom->type == e1000_eeprom_ich8)
 813                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 814 #endif
 815         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 816          * acquired the EEPROM at this point, so any returns should relase it */
 817         if (eeprom->type == e1000_eeprom_spi) {
 818                 uint16_t word_in;
 819                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 820
 821                 if (e1000_spi_eeprom_ready(hw)) {
 822                         e1000_release_eeprom(hw);
 823                         return -E1000_ERR_EEPROM;
 824                 }
 825
 826                 e1000_standby_eeprom(hw);
 827
 828                 /* Some SPI eeproms use the 8th address bit embedded in
 829                  * the opcode */
 830                 if ((eeprom->address_bits == 8) && (offset >= 128))
 831                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 832
 833                 /* Send the READ command (opcode + addr)  */
 834                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 835                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 836                                 eeprom->address_bits);
 837
 838                 /* Read the data.  The address of the eeprom internally
 839                  * increments with each byte (spi) being read, saving on the
 840                  * overhead of eeprom setup and tear-down.  The address
 841                  * counter will roll over if reading beyond the size of
 842                  * the eeprom, thus allowing the entire memory to be read
 843                  * starting from any offset. */
 844                 for (i = 0; i < words; i++) {
 845                         word_in = e1000_shift_in_ee_bits(hw, 16);
 846                         data[i] = (word_in >> 8) | (word_in << 8);
 847                 }
 848         } else if (eeprom->type == e1000_eeprom_microwire) {
 849                 for (i = 0; i < words; i++) {
 850                         /* Send the READ command (opcode + addr)  */
 851                         e1000_shift_out_ee_bits(hw,
 852                                 EEPROM_READ_OPCODE_MICROWIRE,
 853                                 eeprom->opcode_bits);
 854                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 855                                 eeprom->address_bits);
 856
 857                         /* Read the data.  For microwire, each word requires
 858                          * the overhead of eeprom setup and tear-down. */
 859                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 860                         e1000_standby_eeprom(hw);
 861                 }
 862         }
 863
 864         /* End this read operation */
 865         e1000_release_eeprom(hw);
 866
 867         return E1000_SUCCESS;
 868 }
 869
 870 /******************************************************************************
 871  * Verifies that the EEPROM has a valid checksum
 872  *
 873  * hw - Struct containing variables accessed by shared code
 874  *
 875  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 876  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 877  * valid.
 878  *****************************************************************************/
 879 static int
 880 e1000_validate_eeprom_checksum(struct eth_device *nic)
 881 {
 882         struct e1000_hw *hw = nic->priv;
 883         uint16_t checksum = 0;
 884         uint16_t i, eeprom_data;
 885
 886         DEBUGFUNC();
 887
 888         for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
 889                 if (e1000_read_eeprom(hw, i, 1,  &eeprom_data) < 0) {
 890                         DEBUGOUT("EEPROM Read Error\n");
 891                         return -E1000_ERR_EEPROM;
 892                 }
 893                 checksum += eeprom_data;
 894         }
 895
 896         if (checksum == (uint16_t) EEPROM_SUM) {
 897                 return 0;
 898         } else {
 899                 DEBUGOUT("EEPROM Checksum Invalid\n");
 900                 return -E1000_ERR_EEPROM;
 901         }
 902 }
 903
 904 /*****************************************************************************
 905  * Set PHY to class A mode
 906  * Assumes the following operations will follow to enable the new class mode.
 907  *  1. Do a PHY soft reset
 908  *  2. Restart auto-negotiation or force link.
 909  *
 910  * hw - Struct containing variables accessed by shared code
 911  ****************************************************************************/
 912 static int32_t
 913 e1000_set_phy_mode(struct e1000_hw *hw)
 914 {
 915         int32_t ret_val;
 916         uint16_t eeprom_data;
 917
 918         DEBUGFUNC();
 919
 920         if ((hw->mac_type == e1000_82545_rev_3) &&
 921                 (hw->media_type == e1000_media_type_copper)) {
 922                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 923                                 1, &eeprom_data);
 924                 if (ret_val)
 925                         return ret_val;
 926
 927                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 928                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 929                         ret_val = e1000_write_phy_reg(hw,
 930                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 931                         if (ret_val)
 932                                 return ret_val;
 933                         ret_val = e1000_write_phy_reg(hw,
 934                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 935                         if (ret_val)
 936                                 return ret_val;
 937
 938                         hw->phy_reset_disable = FALSE;
 939                 }
 940         }
 941
 942         return E1000_SUCCESS;
 943 }
 944 #endif /* #ifndef CONFIG_AP1000 */
 945
 946 /***************************************************************************
 947  *
 948  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 949  *
 950  * hw: Struct containing variables accessed by shared code
 951  *
 952  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 953  *            E1000_SUCCESS at any other case.
 954  *
 955  ***************************************************************************/
 956 static int32_t
 957 e1000_get_software_semaphore(struct e1000_hw *hw)
 958 {
 959          int32_t timeout = hw->eeprom.word_size + 1;
 960          uint32_t swsm;
 961
 962         DEBUGFUNC();
 963
 964         if (hw->mac_type != e1000_80003es2lan)
 965                 return E1000_SUCCESS;
 966
 967         while (timeout) {
 968                 swsm = E1000_READ_REG(hw, SWSM);
 969                 /* If SMBI bit cleared, it is now set and we hold
 970                  * the semaphore */
 971                 if (!(swsm & E1000_SWSM_SMBI))
 972                         break;
 973                 mdelay(1);
 974                 timeout--;
 975         }
 976
 977         if (!timeout) {
 978                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 979                 return -E1000_ERR_RESET;
 980         }
 981
 982         return E1000_SUCCESS;
 983 }
 984
 985 /***************************************************************************
 986  * This function clears HW semaphore bits.
 987  *
 988  * hw: Struct containing variables accessed by shared code
 989  *
 990  * returns: - None.
 991  *
 992  ***************************************************************************/
 993 static void
 994 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 995 {
 996          uint32_t swsm;
 997
 998         DEBUGFUNC();
 999
1000         if (!hw->eeprom_semaphore_present)
1001                 return;
1002
1003         swsm = E1000_READ_REG(hw, SWSM);
1004         if (hw->mac_type == e1000_80003es2lan) {
1005                 /* Release both semaphores. */
1006                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1007         } else
1008                 swsm &= ~(E1000_SWSM_SWESMBI);
1009         E1000_WRITE_REG(hw, SWSM, swsm);
1010 }
1011
1012 /***************************************************************************
1013  *
1014  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1015  * adapter or Eeprom access.
1016  *
1017  * hw: Struct containing variables accessed by shared code
1018  *
1019  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1020  *            E1000_SUCCESS at any other case.
1021  *
1022  ***************************************************************************/
1023 static int32_t
1024 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1025 {
1026         int32_t timeout;
1027         uint32_t swsm;
1028
1029         DEBUGFUNC();
1030
1031         if (!hw->eeprom_semaphore_present)
1032                 return E1000_SUCCESS;
1033
1034         if (hw->mac_type == e1000_80003es2lan) {
1035                 /* Get the SW semaphore. */
1036                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1037                         return -E1000_ERR_EEPROM;
1038         }
1039
1040         /* Get the FW semaphore. */
1041         timeout = hw->eeprom.word_size + 1;
1042         while (timeout) {
1043                 swsm = E1000_READ_REG(hw, SWSM);
1044                 swsm |= E1000_SWSM_SWESMBI;
1045                 E1000_WRITE_REG(hw, SWSM, swsm);
1046                 /* if we managed to set the bit we got the semaphore. */
1047                 swsm = E1000_READ_REG(hw, SWSM);
1048                 if (swsm & E1000_SWSM_SWESMBI)
1049                         break;
1050
1051                 udelay(50);
1052                 timeout--;
1053         }
1054
1055         if (!timeout) {
1056                 /* Release semaphores */
1057                 e1000_put_hw_eeprom_semaphore(hw);
1058                 DEBUGOUT("Driver can't access the Eeprom - "
1059                                 "SWESMBI bit is set.\n");
1060                 return -E1000_ERR_EEPROM;
1061         }
1062
1063         return E1000_SUCCESS;
1064 }
1065
1066 static int32_t
1067 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1068 {
1069         uint32_t swfw_sync = 0;
1070         uint32_t swmask = mask;
1071         uint32_t fwmask = mask << 16;
1072         int32_t timeout = 200;
1073
1074         DEBUGFUNC();
1075         while (timeout) {
1076                 if (e1000_get_hw_eeprom_semaphore(hw))
1077                         return -E1000_ERR_SWFW_SYNC;
1078
1079                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1080                 if (!(swfw_sync & (fwmask | swmask)))
1081                         break;
1082
1083                 /* firmware currently using resource (fwmask) */
1084                 /* or other software thread currently using resource (swmask) */
1085                 e1000_put_hw_eeprom_semaphore(hw);
1086                 mdelay(5);
1087                 timeout--;
1088         }
1089
1090         if (!timeout) {
1091                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1092                 return -E1000_ERR_SWFW_SYNC;
1093         }
1094
1095         swfw_sync |= swmask;
1096         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1097
1098         e1000_put_hw_eeprom_semaphore(hw);
1099         return E1000_SUCCESS;
1100 }
1101
1102 /******************************************************************************
1103  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1104  * second function of dual function devices
1105  *
1106  * nic - Struct containing variables accessed by shared code
1107  *****************************************************************************/
1108 static int
1109 e1000_read_mac_addr(struct eth_device *nic)
1110 {
1111 #ifndef CONFIG_AP1000
1112         struct e1000_hw *hw = nic->priv;
1113         uint16_t offset;
1114         uint16_t eeprom_data;
1115         int i;
1116
1117         DEBUGFUNC();
1118
1119         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1120                 offset = i >> 1;
1121                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1122                         DEBUGOUT("EEPROM Read Error\n");
1123                         return -E1000_ERR_EEPROM;
1124                 }
1125                 nic->enetaddr[i] = eeprom_data & 0xff;
1126                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1127         }
1128         if ((hw->mac_type == e1000_82546) &&
1129             (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
1130                 /* Invert the last bit if this is the second device */
1131                 nic->enetaddr[5] += 1;
1132         }
1133 #ifdef CONFIG_E1000_FALLBACK_MAC
1134         if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
1135                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1136
1137                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1138         }
1139 #endif
1140 #else
1141         /*
1142          * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1143          * environment variables.  Currently this does not support the addition
1144          * of a PMC e1000 card, which is certainly a possibility, so this should
1145          * be updated to properly use the env variable only for the onboard e1000
1146          */
1147
1148         int ii;
1149         char *s, *e;
1150
1151         DEBUGFUNC();
1152
1153         s = getenv ("ethaddr");
1154         if (s == NULL) {
1155                 return -E1000_ERR_EEPROM;
1156         } else {
1157                 for(ii = 0; ii < 6; ii++) {
1158                         nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1159                         if (s){
1160                                 s = (*e) ? e + 1 : e;
1161                         }
1162                 }
1163         }
1164 #endif
1165         return 0;
1166 }
1167
1168 /******************************************************************************
1169  * Initializes receive address filters.
1170  *
1171  * hw - Struct containing variables accessed by shared code
1172  *
1173  * Places the MAC address in receive address register 0 and clears the rest
1174  * of the receive addresss registers. Clears the multicast table. Assumes
1175  * the receiver is in reset when the routine is called.
1176  *****************************************************************************/
1177 static void
1178 e1000_init_rx_addrs(struct eth_device *nic)
1179 {
1180         struct e1000_hw *hw = nic->priv;
1181         uint32_t i;
1182         uint32_t addr_low;
1183         uint32_t addr_high;
1184
1185         DEBUGFUNC();
1186
1187         /* Setup the receive address. */
1188         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1189         addr_low = (nic->enetaddr[0] |
1190                     (nic->enetaddr[1] << 8) |
1191                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1192
1193         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1194
1195         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1196         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1197
1198         /* Zero out the other 15 receive addresses. */
1199         DEBUGOUT("Clearing RAR[1-15]\n");
1200         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1201                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1202                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1203         }
1204 }
1205
1206 /******************************************************************************
1207  * Clears the VLAN filer table
1208  *
1209  * hw - Struct containing variables accessed by shared code
1210  *****************************************************************************/
1211 static void
1212 e1000_clear_vfta(struct e1000_hw *hw)
1213 {
1214         uint32_t offset;
1215
1216         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1217                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1218 }
1219
1220 /******************************************************************************
1221  * Set the mac type member in the hw struct.
1222  *
1223  * hw - Struct containing variables accessed by shared code
1224  *****************************************************************************/
1225 int32_t
1226 e1000_set_mac_type(struct e1000_hw *hw)
1227 {
1228         DEBUGFUNC();
1229
1230         switch (hw->device_id) {
1231         case E1000_DEV_ID_82542:
1232                 switch (hw->revision_id) {
1233                 case E1000_82542_2_0_REV_ID:
1234                         hw->mac_type = e1000_82542_rev2_0;
1235                         break;
1236                 case E1000_82542_2_1_REV_ID:
1237                         hw->mac_type = e1000_82542_rev2_1;
1238                         break;
1239                 default:
1240                         /* Invalid 82542 revision ID */
1241                         return -E1000_ERR_MAC_TYPE;
1242                 }
1243                 break;
1244         case E1000_DEV_ID_82543GC_FIBER:
1245         case E1000_DEV_ID_82543GC_COPPER:
1246                 hw->mac_type = e1000_82543;
1247                 break;
1248         case E1000_DEV_ID_82544EI_COPPER:
1249         case E1000_DEV_ID_82544EI_FIBER:
1250         case E1000_DEV_ID_82544GC_COPPER:
1251         case E1000_DEV_ID_82544GC_LOM:
1252                 hw->mac_type = e1000_82544;
1253                 break;
1254         case E1000_DEV_ID_82540EM:
1255         case E1000_DEV_ID_82540EM_LOM:
1256         case E1000_DEV_ID_82540EP:
1257         case E1000_DEV_ID_82540EP_LOM:
1258         case E1000_DEV_ID_82540EP_LP:
1259                 hw->mac_type = e1000_82540;
1260                 break;
1261         case E1000_DEV_ID_82545EM_COPPER:
1262         case E1000_DEV_ID_82545EM_FIBER:
1263                 hw->mac_type = e1000_82545;
1264                 break;
1265         case E1000_DEV_ID_82545GM_COPPER:
1266         case E1000_DEV_ID_82545GM_FIBER:
1267         case E1000_DEV_ID_82545GM_SERDES:
1268                 hw->mac_type = e1000_82545_rev_3;
1269                 break;
1270         case E1000_DEV_ID_82546EB_COPPER:
1271         case E1000_DEV_ID_82546EB_FIBER:
1272         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1273                 hw->mac_type = e1000_82546;
1274                 break;
1275         case E1000_DEV_ID_82546GB_COPPER:
1276         case E1000_DEV_ID_82546GB_FIBER:
1277         case E1000_DEV_ID_82546GB_SERDES:
1278         case E1000_DEV_ID_82546GB_PCIE:
1279         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1280         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1281                 hw->mac_type = e1000_82546_rev_3;
1282                 break;
1283         case E1000_DEV_ID_82541EI:
1284         case E1000_DEV_ID_82541EI_MOBILE:
1285         case E1000_DEV_ID_82541ER_LOM:
1286                 hw->mac_type = e1000_82541;
1287                 break;
1288         case E1000_DEV_ID_82541ER:
1289         case E1000_DEV_ID_82541GI:
1290         case E1000_DEV_ID_82541GI_LF:
1291         case E1000_DEV_ID_82541GI_MOBILE:
1292                 hw->mac_type = e1000_82541_rev_2;
1293                 break;
1294         case E1000_DEV_ID_82547EI:
1295         case E1000_DEV_ID_82547EI_MOBILE:
1296                 hw->mac_type = e1000_82547;
1297                 break;
1298         case E1000_DEV_ID_82547GI:
1299                 hw->mac_type = e1000_82547_rev_2;
1300                 break;
1301         case E1000_DEV_ID_82571EB_COPPER:
1302         case E1000_DEV_ID_82571EB_FIBER:
1303         case E1000_DEV_ID_82571EB_SERDES:
1304         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1305         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1306         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1307         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1308         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1309         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1310                 hw->mac_type = e1000_82571;
1311                 break;
1312         case E1000_DEV_ID_82572EI_COPPER:
1313         case E1000_DEV_ID_82572EI_FIBER:
1314         case E1000_DEV_ID_82572EI_SERDES:
1315         case E1000_DEV_ID_82572EI:
1316                 hw->mac_type = e1000_82572;
1317                 break;
1318         case E1000_DEV_ID_82573E:
1319         case E1000_DEV_ID_82573E_IAMT:
1320         case E1000_DEV_ID_82573L:
1321                 hw->mac_type = e1000_82573;
1322                 break;
1323         case E1000_DEV_ID_82574L:
1324                 hw->mac_type = e1000_82574;
1325                 break;
1326         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1327         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1328         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1329         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1330                 hw->mac_type = e1000_80003es2lan;
1331                 break;
1332         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1333         case E1000_DEV_ID_ICH8_IGP_AMT:
1334         case E1000_DEV_ID_ICH8_IGP_C:
1335         case E1000_DEV_ID_ICH8_IFE:
1336         case E1000_DEV_ID_ICH8_IFE_GT:
1337         case E1000_DEV_ID_ICH8_IFE_G:
1338         case E1000_DEV_ID_ICH8_IGP_M:
1339                 hw->mac_type = e1000_ich8lan;
1340                 break;
1341         default:
1342                 /* Should never have loaded on this device */
1343                 return -E1000_ERR_MAC_TYPE;
1344         }
1345         return E1000_SUCCESS;
1346 }
1347
1348 /******************************************************************************
1349  * Reset the transmit and receive units; mask and clear all interrupts.
1350  *
1351  * hw - Struct containing variables accessed by shared code
1352  *****************************************************************************/
1353 void
1354 e1000_reset_hw(struct e1000_hw *hw)
1355 {
1356         uint32_t ctrl;
1357         uint32_t ctrl_ext;
1358         uint32_t icr;
1359         uint32_t manc;
1360         uint32_t pba = 0;
1361
1362         DEBUGFUNC();
1363
1364         /* get the correct pba value for both PCI and PCIe*/
1365         if (hw->mac_type <  e1000_82571)
1366                 pba = E1000_DEFAULT_PCI_PBA;
1367         else
1368                 pba = E1000_DEFAULT_PCIE_PBA;
1369
1370         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1371         if (hw->mac_type == e1000_82542_rev2_0) {
1372                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1373                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1374                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1375         }
1376
1377         /* Clear interrupt mask to stop board from generating interrupts */
1378         DEBUGOUT("Masking off all interrupts\n");
1379         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1380
1381         /* Disable the Transmit and Receive units.  Then delay to allow
1382          * any pending transactions to complete before we hit the MAC with
1383          * the global reset.
1384          */
1385         E1000_WRITE_REG(hw, RCTL, 0);
1386         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1387         E1000_WRITE_FLUSH(hw);
1388
1389         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1390         hw->tbi_compatibility_on = FALSE;
1391
1392         /* Delay to allow any outstanding PCI transactions to complete before
1393          * resetting the device
1394          */
1395         mdelay(10);
1396
1397         /* Issue a global reset to the MAC.  This will reset the chip's
1398          * transmit, receive, DMA, and link units.  It will not effect
1399          * the current PCI configuration.  The global reset bit is self-
1400          * clearing, and should clear within a microsecond.
1401          */
1402         DEBUGOUT("Issuing a global reset to MAC\n");
1403         ctrl = E1000_READ_REG(hw, CTRL);
1404
1405         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1406
1407         /* Force a reload from the EEPROM if necessary */
1408         if (hw->mac_type < e1000_82540) {
1409                 /* Wait for reset to complete */
1410                 udelay(10);
1411                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1412                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1413                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1414                 E1000_WRITE_FLUSH(hw);
1415                 /* Wait for EEPROM reload */
1416                 mdelay(2);
1417         } else {
1418                 /* Wait for EEPROM reload (it happens automatically) */
1419                 mdelay(4);
1420                 /* Dissable HW ARPs on ASF enabled adapters */
1421                 manc = E1000_READ_REG(hw, MANC);
1422                 manc &= ~(E1000_MANC_ARP_EN);
1423                 E1000_WRITE_REG(hw, MANC, manc);
1424         }
1425
1426         /* Clear interrupt mask to stop board from generating interrupts */
1427         DEBUGOUT("Masking off all interrupts\n");
1428         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1429
1430         /* Clear any pending interrupt events. */
1431         icr = E1000_READ_REG(hw, ICR);
1432
1433         /* If MWI was previously enabled, reenable it. */
1434         if (hw->mac_type == e1000_82542_rev2_0) {
1435                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1436         }
1437         E1000_WRITE_REG(hw, PBA, pba);
1438 }
1439
1440 /******************************************************************************
1441  *
1442  * Initialize a number of hardware-dependent bits
1443  *
1444  * hw: Struct containing variables accessed by shared code
1445  *
1446  * This function contains hardware limitation workarounds for PCI-E adapters
1447  *
1448  *****************************************************************************/
1449 static void
1450 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1451 {
1452         if ((hw->mac_type >= e1000_82571) &&
1453                         (!hw->initialize_hw_bits_disable)) {
1454                 /* Settings common to all PCI-express silicon */
1455                 uint32_t reg_ctrl, reg_ctrl_ext;
1456                 uint32_t reg_tarc0, reg_tarc1;
1457                 uint32_t reg_tctl;
1458                 uint32_t reg_txdctl, reg_txdctl1;
1459
1460                 /* link autonegotiation/sync workarounds */
1461                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1462                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1463
1464                 /* Enable not-done TX descriptor counting */
1465                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1466                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1467                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1468
1469                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1470                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1471                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1472
1473                 switch (hw->mac_type) {
1474                 case e1000_82571:
1475                 case e1000_82572:
1476                         /* Clear PHY TX compatible mode bits */
1477                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1478                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1479
1480                         /* link autonegotiation/sync workarounds */
1481                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1482
1483                         /* TX ring control fixes */
1484                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1485
1486                         /* Multiple read bit is reversed polarity */
1487                         reg_tctl = E1000_READ_REG(hw, TCTL);
1488                         if (reg_tctl & E1000_TCTL_MULR)
1489                                 reg_tarc1 &= ~(1 << 28);
1490                         else
1491                                 reg_tarc1 |= (1 << 28);
1492
1493                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1494                         break;
1495                 case e1000_82573:
1496                 case e1000_82574:
1497                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1498                         reg_ctrl_ext &= ~(1 << 23);
1499                         reg_ctrl_ext |= (1 << 22);
1500
1501                         /* TX byte count fix */
1502                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1503                         reg_ctrl &= ~(1 << 29);
1504
1505                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1506                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1507                         break;
1508                 case e1000_80003es2lan:
1509         /* improve small packet performace for fiber/serdes */
1510                         if ((hw->media_type == e1000_media_type_fiber)
1511                         || (hw->media_type ==
1512                                 e1000_media_type_internal_serdes)) {
1513                                 reg_tarc0 &= ~(1 << 20);
1514                         }
1515
1516                 /* Multiple read bit is reversed polarity */
1517                         reg_tctl = E1000_READ_REG(hw, TCTL);
1518                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1519                         if (reg_tctl & E1000_TCTL_MULR)
1520                                 reg_tarc1 &= ~(1 << 28);
1521                         else
1522                                 reg_tarc1 |= (1 << 28);
1523
1524                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1525                         break;
1526                 case e1000_ich8lan:
1527                         /* Reduce concurrent DMA requests to 3 from 4 */
1528                         if ((hw->revision_id < 3) ||
1529                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1530                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1531                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1532
1533                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1534                         reg_ctrl_ext |= (1 << 22);
1535                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1536
1537                         /* workaround TX hang with TSO=on */
1538                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1539
1540                         /* Multiple read bit is reversed polarity */
1541                         reg_tctl = E1000_READ_REG(hw, TCTL);
1542                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1543                         if (reg_tctl & E1000_TCTL_MULR)
1544                                 reg_tarc1 &= ~(1 << 28);
1545                         else
1546                                 reg_tarc1 |= (1 << 28);
1547
1548                         /* workaround TX hang with TSO=on */
1549                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1550
1551                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1552                         break;
1553                 default:
1554                         break;
1555                 }
1556
1557                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1558         }
1559 }
1560
1561 /******************************************************************************
1562  * Performs basic configuration of the adapter.
1563  *
1564  * hw - Struct containing variables accessed by shared code
1565  *
1566  * Assumes that the controller has previously been reset and is in a
1567  * post-reset uninitialized state. Initializes the receive address registers,
1568  * multicast table, and VLAN filter table. Calls routines to setup link
1569  * configuration and flow control settings. Clears all on-chip counters. Leaves
1570  * the transmit and receive units disabled and uninitialized.
1571  *****************************************************************************/
1572 static int
1573 e1000_init_hw(struct eth_device *nic)
1574 {
1575         struct e1000_hw *hw = nic->priv;
1576         uint32_t ctrl;
1577         uint32_t i;
1578         int32_t ret_val;
1579         uint16_t pcix_cmd_word;
1580         uint16_t pcix_stat_hi_word;
1581         uint16_t cmd_mmrbc;
1582         uint16_t stat_mmrbc;
1583         uint32_t mta_size;
1584         uint32_t reg_data;
1585         uint32_t ctrl_ext;
1586         DEBUGFUNC();
1587         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1588         if ((hw->mac_type == e1000_ich8lan) &&
1589                 ((hw->revision_id < 3) ||
1590                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1591                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1592                         reg_data = E1000_READ_REG(hw, STATUS);
1593                         reg_data &= ~0x80000000;
1594                         E1000_WRITE_REG(hw, STATUS, reg_data);
1595         }
1596         /* Do not need initialize Identification LED */
1597
1598         /* Set the media type and TBI compatibility */
1599         e1000_set_media_type(hw);
1600
1601         /* Must be called after e1000_set_media_type
1602          * because media_type is used */
1603         e1000_initialize_hardware_bits(hw);
1604
1605         /* Disabling VLAN filtering. */
1606         DEBUGOUT("Initializing the IEEE VLAN\n");
1607         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1608         if (hw->mac_type != e1000_ich8lan) {
1609                 if (hw->mac_type < e1000_82545_rev_3)
1610                         E1000_WRITE_REG(hw, VET, 0);
1611                 e1000_clear_vfta(hw);
1612         }
1613
1614         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1615         if (hw->mac_type == e1000_82542_rev2_0) {
1616                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1617                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1618                                       hw->
1619                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1620                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1621                 E1000_WRITE_FLUSH(hw);
1622                 mdelay(5);
1623         }
1624
1625         /* Setup the receive address. This involves initializing all of the Receive
1626          * Address Registers (RARs 0 - 15).
1627          */
1628         e1000_init_rx_addrs(nic);
1629
1630         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1631         if (hw->mac_type == e1000_82542_rev2_0) {
1632                 E1000_WRITE_REG(hw, RCTL, 0);
1633                 E1000_WRITE_FLUSH(hw);
1634                 mdelay(1);
1635                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1636         }
1637
1638         /* Zero out the Multicast HASH table */
1639         DEBUGOUT("Zeroing the MTA\n");
1640         mta_size = E1000_MC_TBL_SIZE;
1641         if (hw->mac_type == e1000_ich8lan)
1642                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1643         for (i = 0; i < mta_size; i++) {
1644                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1645                 /* use write flush to prevent Memory Write Block (MWB) from
1646                  * occuring when accessing our register space */
1647                 E1000_WRITE_FLUSH(hw);
1648         }
1649 #if 0
1650         /* Set the PCI priority bit correctly in the CTRL register.  This
1651          * determines if the adapter gives priority to receives, or if it
1652          * gives equal priority to transmits and receives.  Valid only on
1653          * 82542 and 82543 silicon.
1654          */
1655         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1656                 ctrl = E1000_READ_REG(hw, CTRL);
1657                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1658         }
1659 #endif
1660         switch (hw->mac_type) {
1661         case e1000_82545_rev_3:
1662         case e1000_82546_rev_3:
1663                 break;
1664         default:
1665         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1666         if (hw->bus_type == e1000_bus_type_pcix) {
1667                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1668                                      &pcix_cmd_word);
1669                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1670                                      &pcix_stat_hi_word);
1671                 cmd_mmrbc =
1672                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1673                     PCIX_COMMAND_MMRBC_SHIFT;
1674                 stat_mmrbc =
1675                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1676                     PCIX_STATUS_HI_MMRBC_SHIFT;
1677                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1678                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1679                 if (cmd_mmrbc > stat_mmrbc) {
1680                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1681                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1682                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1683                                               pcix_cmd_word);
1684                 }
1685         }
1686                 break;
1687         }
1688
1689         /* More time needed for PHY to initialize */
1690         if (hw->mac_type == e1000_ich8lan)
1691                 mdelay(15);
1692
1693         /* Call a subroutine to configure the link and setup flow control. */
1694         ret_val = e1000_setup_link(nic);
1695
1696         /* Set the transmit descriptor write-back policy */
1697         if (hw->mac_type > e1000_82544) {
1698                 ctrl = E1000_READ_REG(hw, TXDCTL);
1699                 ctrl =
1700                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1701                     E1000_TXDCTL_FULL_TX_DESC_WB;
1702                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1703         }
1704
1705         switch (hw->mac_type) {
1706         default:
1707                 break;
1708         case e1000_80003es2lan:
1709                 /* Enable retransmit on late collisions */
1710                 reg_data = E1000_READ_REG(hw, TCTL);
1711                 reg_data |= E1000_TCTL_RTLC;
1712                 E1000_WRITE_REG(hw, TCTL, reg_data);
1713
1714                 /* Configure Gigabit Carry Extend Padding */
1715                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1716                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1717                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1718                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1719
1720                 /* Configure Transmit Inter-Packet Gap */
1721                 reg_data = E1000_READ_REG(hw, TIPG);
1722                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1723                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1724                 E1000_WRITE_REG(hw, TIPG, reg_data);
1725
1726                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1727                 reg_data &= ~0x00100000;
1728                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1729                 /* Fall through */
1730         case e1000_82571:
1731         case e1000_82572:
1732         case e1000_ich8lan:
1733                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1734                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1735                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1736                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1737                 break;
1738         case e1000_82573:
1739         case e1000_82574:
1740                 reg_data = E1000_READ_REG(hw, GCR);
1741                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1742                 E1000_WRITE_REG(hw, GCR, reg_data);
1743         }
1744
1745 #if 0
1746         /* Clear all of the statistics registers (clear on read).  It is
1747          * important that we do this after we have tried to establish link
1748          * because the symbol error count will increment wildly if there
1749          * is no link.
1750          */
1751         e1000_clear_hw_cntrs(hw);
1752
1753         /* ICH8 No-snoop bits are opposite polarity.
1754          * Set to snoop by default after reset. */
1755         if (hw->mac_type == e1000_ich8lan)
1756                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1757 #endif
1758
1759         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1760                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1761                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1762                 /* Relaxed ordering must be disabled to avoid a parity
1763                  * error crash in a PCI slot. */
1764                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1765                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1766         }
1767
1768         return ret_val;
1769 }
1770
1771 /******************************************************************************
1772  * Configures flow control and link settings.
1773  *
1774  * hw - Struct containing variables accessed by shared code
1775  *
1776  * Determines which flow control settings to use. Calls the apropriate media-
1777  * specific link configuration function. Configures the flow control settings.
1778  * Assuming the adapter has a valid link partner, a valid link should be
1779  * established. Assumes the hardware has previously been reset and the
1780  * transmitter and receiver are not enabled.
1781  *****************************************************************************/
1782 static int
1783 e1000_setup_link(struct eth_device *nic)
1784 {
1785         struct e1000_hw *hw = nic->priv;
1786         uint32_t ctrl_ext;
1787         int32_t ret_val;
1788         uint16_t eeprom_data;
1789
1790         DEBUGFUNC();
1791
1792         /* In the case of the phy reset being blocked, we already have a link.
1793          * We do not have to set it up again. */
1794         if (e1000_check_phy_reset_block(hw))
1795                 return E1000_SUCCESS;
1796
1797 #ifndef CONFIG_AP1000
1798         /* Read and store word 0x0F of the EEPROM. This word contains bits
1799          * that determine the hardware's default PAUSE (flow control) mode,
1800          * a bit that determines whether the HW defaults to enabling or
1801          * disabling auto-negotiation, and the direction of the
1802          * SW defined pins. If there is no SW over-ride of the flow
1803          * control setting, then the variable hw->fc will
1804          * be initialized based on a value in the EEPROM.
1805          */
1806         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1807                                 &eeprom_data) < 0) {
1808                 DEBUGOUT("EEPROM Read Error\n");
1809                 return -E1000_ERR_EEPROM;
1810         }
1811 #else
1812         /* we have to hardcode the proper value for our hardware. */
1813         /* this value is for the 82540EM pci card used for prototyping, and it works. */
1814         eeprom_data = 0xb220;
1815 #endif
1816
1817         if (hw->fc == e1000_fc_default) {
1818                 switch (hw->mac_type) {
1819                 case e1000_ich8lan:
1820                 case e1000_82573:
1821                 case e1000_82574:
1822                         hw->fc = e1000_fc_full;
1823                         break;
1824                 default:
1825 #ifndef CONFIG_AP1000
1826                         ret_val = e1000_read_eeprom(hw,
1827                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1828                         if (ret_val) {
1829                                 DEBUGOUT("EEPROM Read Error\n");
1830                                 return -E1000_ERR_EEPROM;
1831                         }
1832 #else
1833                         eeprom_data = 0xb220;
1834 #endif
1835                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1836                                 hw->fc = e1000_fc_none;
1837                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1838                                     EEPROM_WORD0F_ASM_DIR)
1839                                 hw->fc = e1000_fc_tx_pause;
1840                         else
1841                                 hw->fc = e1000_fc_full;
1842                         break;
1843                 }
1844         }
1845
1846         /* We want to save off the original Flow Control configuration just
1847          * in case we get disconnected and then reconnected into a different
1848          * hub or switch with different Flow Control capabilities.
1849          */
1850         if (hw->mac_type == e1000_82542_rev2_0)
1851                 hw->fc &= (~e1000_fc_tx_pause);
1852
1853         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1854                 hw->fc &= (~e1000_fc_rx_pause);
1855
1856         hw->original_fc = hw->fc;
1857
1858         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1859
1860         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1861          * polarity value for the SW controlled pins, and setup the
1862          * Extended Device Control reg with that info.
1863          * This is needed because one of the SW controlled pins is used for
1864          * signal detection.  So this should be done before e1000_setup_pcs_link()
1865          * or e1000_phy_setup() is called.
1866          */
1867         if (hw->mac_type == e1000_82543) {
1868                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1869                             SWDPIO__EXT_SHIFT);
1870                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1871         }
1872
1873         /* Call the necessary subroutine to configure the link. */
1874         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1875             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1876         if (ret_val < 0) {
1877                 return ret_val;
1878         }
1879
1880         /* Initialize the flow control address, type, and PAUSE timer
1881          * registers to their default values.  This is done even if flow
1882          * control is disabled, because it does not hurt anything to
1883          * initialize these registers.
1884          */
1885         DEBUGOUT("Initializing the Flow Control address, type"
1886                         "and timer regs\n");
1887
1888         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1889         if (hw->mac_type != e1000_ich8lan) {
1890                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1891                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1892                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1893         }
1894
1895         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1896
1897         /* Set the flow control receive threshold registers.  Normally,
1898          * these registers will be set to a default threshold that may be
1899          * adjusted later by the driver's runtime code.  However, if the
1900          * ability to transmit pause frames in not enabled, then these
1901          * registers will be set to 0.
1902          */
1903         if (!(hw->fc & e1000_fc_tx_pause)) {
1904                 E1000_WRITE_REG(hw, FCRTL, 0);
1905                 E1000_WRITE_REG(hw, FCRTH, 0);
1906         } else {
1907                 /* We need to set up the Receive Threshold high and low water marks
1908                  * as well as (optionally) enabling the transmission of XON frames.
1909                  */
1910                 if (hw->fc_send_xon) {
1911                         E1000_WRITE_REG(hw, FCRTL,
1912                                         (hw->fc_low_water | E1000_FCRTL_XONE));
1913                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1914                 } else {
1915                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1916                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1917                 }
1918         }
1919         return ret_val;
1920 }
1921
1922 /******************************************************************************
1923  * Sets up link for a fiber based adapter
1924  *
1925  * hw - Struct containing variables accessed by shared code
1926  *
1927  * Manipulates Physical Coding Sublayer functions in order to configure
1928  * link. Assumes the hardware has been previously reset and the transmitter
1929  * and receiver are not enabled.
1930  *****************************************************************************/
1931 static int
1932 e1000_setup_fiber_link(struct eth_device *nic)
1933 {
1934         struct e1000_hw *hw = nic->priv;
1935         uint32_t ctrl;
1936         uint32_t status;
1937         uint32_t txcw = 0;
1938         uint32_t i;
1939         uint32_t signal;
1940         int32_t ret_val;
1941
1942         DEBUGFUNC();
1943         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1944          * set when the optics detect a signal. On older adapters, it will be
1945          * cleared when there is a signal
1946          */
1947         ctrl = E1000_READ_REG(hw, CTRL);
1948         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1949                 signal = E1000_CTRL_SWDPIN1;
1950         else
1951                 signal = 0;
1952
1953         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1954                ctrl);
1955         /* Take the link out of reset */
1956         ctrl &= ~(E1000_CTRL_LRST);
1957
1958         e1000_config_collision_dist(hw);
1959
1960         /* Check for a software override of the flow control settings, and setup
1961          * the device accordingly.  If auto-negotiation is enabled, then software
1962          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1963          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1964          * auto-negotiation is disabled, then software will have to manually
1965          * configure the two flow control enable bits in the CTRL register.
1966          *
1967          * The possible values of the "fc" parameter are:
1968          *      0:  Flow control is completely disabled
1969          *      1:  Rx flow control is enabled (we can receive pause frames, but
1970          *          not send pause frames).
1971          *      2:  Tx flow control is enabled (we can send pause frames but we do
1972          *          not support receiving pause frames).
1973          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1974          */
1975         switch (hw->fc) {
1976         case e1000_fc_none:
1977                 /* Flow control is completely disabled by a software over-ride. */
1978                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1979                 break;
1980         case e1000_fc_rx_pause:
1981                 /* RX Flow control is enabled and TX Flow control is disabled by a
1982                  * software over-ride. Since there really isn't a way to advertise
1983                  * that we are capable of RX Pause ONLY, we will advertise that we
1984                  * support both symmetric and asymmetric RX PAUSE. Later, we will
1985                  *  disable the adapter's ability to send PAUSE frames.
1986                  */
1987                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1988                 break;
1989         case e1000_fc_tx_pause:
1990                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1991                  * software over-ride.
1992                  */
1993                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1994                 break;
1995         case e1000_fc_full:
1996                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1997                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1998                 break;
1999         default:
2000                 DEBUGOUT("Flow control param set incorrectly\n");
2001                 return -E1000_ERR_CONFIG;
2002                 break;
2003         }
2004
2005         /* Since auto-negotiation is enabled, take the link out of reset (the link
2006          * will be in reset, because we previously reset the chip). This will
2007          * restart auto-negotiation.  If auto-neogtiation is successful then the
2008          * link-up status bit will be set and the flow control enable bits (RFCE
2009          * and TFCE) will be set according to their negotiated value.
2010          */
2011         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2012
2013         E1000_WRITE_REG(hw, TXCW, txcw);
2014         E1000_WRITE_REG(hw, CTRL, ctrl);
2015         E1000_WRITE_FLUSH(hw);
2016
2017         hw->txcw = txcw;
2018         mdelay(1);
2019
2020         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2021          * indication in the Device Status Register.  Time-out if a link isn't
2022          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2023          * less than 500 milliseconds even if the other end is doing it in SW).
2024          */
2025         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2026                 DEBUGOUT("Looking for Link\n");
2027                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2028                         mdelay(10);
2029                         status = E1000_READ_REG(hw, STATUS);
2030                         if (status & E1000_STATUS_LU)
2031                                 break;
2032                 }
2033                 if (i == (LINK_UP_TIMEOUT / 10)) {
2034                         /* AutoNeg failed to achieve a link, so we'll call
2035                          * e1000_check_for_link. This routine will force the link up if we
2036                          * detect a signal. This will allow us to communicate with
2037                          * non-autonegotiating link partners.
2038                          */
2039                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2040                         hw->autoneg_failed = 1;
2041                         ret_val = e1000_check_for_link(nic);
2042                         if (ret_val < 0) {
2043                                 DEBUGOUT("Error while checking for link\n");
2044                                 return ret_val;
2045                         }
2046                         hw->autoneg_failed = 0;
2047                 } else {
2048                         hw->autoneg_failed = 0;
2049                         DEBUGOUT("Valid Link Found\n");
2050                 }
2051         } else {
2052                 DEBUGOUT("No Signal Detected\n");
2053                 return -E1000_ERR_NOLINK;
2054         }
2055         return 0;
2056 }
2057
2058 /******************************************************************************
2059 * Make sure we have a valid PHY and change PHY mode before link setup.
2060 *
2061 * hw - Struct containing variables accessed by shared code
2062 ******************************************************************************/
2063 static int32_t
2064 e1000_copper_link_preconfig(struct e1000_hw *hw)
2065 {
2066         uint32_t ctrl;
2067         int32_t ret_val;
2068         uint16_t phy_data;
2069
2070         DEBUGFUNC();
2071
2072         ctrl = E1000_READ_REG(hw, CTRL);
2073         /* With 82543, we need to force speed and duplex on the MAC equal to what
2074          * the PHY speed and duplex configuration is. In addition, we need to
2075          * perform a hardware reset on the PHY to take it out of reset.
2076          */
2077         if (hw->mac_type > e1000_82543) {
2078                 ctrl |= E1000_CTRL_SLU;
2079                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2080                 E1000_WRITE_REG(hw, CTRL, ctrl);
2081         } else {
2082                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2083                                 | E1000_CTRL_SLU);
2084                 E1000_WRITE_REG(hw, CTRL, ctrl);
2085                 ret_val = e1000_phy_hw_reset(hw);
2086                 if (ret_val)
2087                         return ret_val;
2088         }
2089
2090         /* Make sure we have a valid PHY */
2091         ret_val = e1000_detect_gig_phy(hw);
2092         if (ret_val) {
2093                 DEBUGOUT("Error, did not detect valid phy.\n");
2094                 return ret_val;
2095         }
2096         DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2097
2098 #ifndef CONFIG_AP1000
2099         /* Set PHY to class A mode (if necessary) */
2100         ret_val = e1000_set_phy_mode(hw);
2101         if (ret_val)
2102                 return ret_val;
2103 #endif
2104         if ((hw->mac_type == e1000_82545_rev_3) ||
2105                 (hw->mac_type == e1000_82546_rev_3)) {
2106                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2107                                 &phy_data);
2108                 phy_data |= 0x00000008;
2109                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2110                                 phy_data);
2111         }
2112
2113         if (hw->mac_type <= e1000_82543 ||
2114                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2115                 hw->mac_type == e1000_82541_rev_2
2116                 || hw->mac_type == e1000_82547_rev_2)
2117                         hw->phy_reset_disable = FALSE;
2118
2119         return E1000_SUCCESS;
2120 }
2121
2122 /*****************************************************************************
2123  *
2124  * This function sets the lplu state according to the active flag.  When
2125  * activating lplu this function also disables smart speed and vise versa.
2126  * lplu will not be activated unless the device autonegotiation advertisment
2127  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2128  * hw: Struct containing variables accessed by shared code
2129  * active - true to enable lplu false to disable lplu.
2130  *
2131  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2132  *            E1000_SUCCESS at any other case.
2133  *
2134  ****************************************************************************/
2135
2136 static int32_t
2137 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2138 {
2139         uint32_t phy_ctrl = 0;
2140         int32_t ret_val;
2141         uint16_t phy_data;
2142         DEBUGFUNC();
2143
2144         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2145             && hw->phy_type != e1000_phy_igp_3)
2146                 return E1000_SUCCESS;
2147
2148         /* During driver activity LPLU should not be used or it will attain link
2149          * from the lowest speeds starting from 10Mbps. The capability is used
2150          * for Dx transitions and states */
2151         if (hw->mac_type == e1000_82541_rev_2
2152                         || hw->mac_type == e1000_82547_rev_2) {
2153                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2154                                 &phy_data);
2155                 if (ret_val)
2156                         return ret_val;
2157         } else if (hw->mac_type == e1000_ich8lan) {
2158                 /* MAC writes into PHY register based on the state transition
2159                  * and start auto-negotiation. SW driver can overwrite the
2160                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2161                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2162         } else {
2163                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2164                                 &phy_data);
2165                 if (ret_val)
2166                         return ret_val;
2167         }
2168
2169         if (!active) {
2170                 if (hw->mac_type == e1000_82541_rev_2 ||
2171                         hw->mac_type == e1000_82547_rev_2) {
2172                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2173                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2174                                         phy_data);
2175                         if (ret_val)
2176                                 return ret_val;
2177                 } else {
2178                         if (hw->mac_type == e1000_ich8lan) {
2179                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2180                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2181                         } else {
2182                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2183                                 ret_val = e1000_write_phy_reg(hw,
2184                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2185                                 if (ret_val)
2186                                         return ret_val;
2187                         }
2188                 }
2189
2190         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2191          * Dx states where the power conservation is most important.  During
2192          * driver activity we should enable SmartSpeed, so performance is
2193          * maintained. */
2194                 if (hw->smart_speed == e1000_smart_speed_on) {
2195                         ret_val = e1000_read_phy_reg(hw,
2196                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2197                         if (ret_val)
2198                                 return ret_val;
2199
2200                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2201                         ret_val = e1000_write_phy_reg(hw,
2202                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2203                         if (ret_val)
2204                                 return ret_val;
2205                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2206                         ret_val = e1000_read_phy_reg(hw,
2207                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2208                         if (ret_val)
2209                                 return ret_val;
2210
2211                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2212                         ret_val = e1000_write_phy_reg(hw,
2213                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2214                         if (ret_val)
2215                                 return ret_val;
2216                 }
2217
2218         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2219                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2220                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2221
2222                 if (hw->mac_type == e1000_82541_rev_2 ||
2223                     hw->mac_type == e1000_82547_rev_2) {
2224                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2225                         ret_val = e1000_write_phy_reg(hw,
2226                                         IGP01E1000_GMII_FIFO, phy_data);
2227                         if (ret_val)
2228                                 return ret_val;
2229                 } else {
2230                         if (hw->mac_type == e1000_ich8lan) {
2231                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2232                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2233                         } else {
2234                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2235                                 ret_val = e1000_write_phy_reg(hw,
2236                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2237                                 if (ret_val)
2238                                         return ret_val;
2239                         }
2240                 }
2241
2242                 /* When LPLU is enabled we should disable SmartSpeed */
2243                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2244                                 &phy_data);
2245                 if (ret_val)
2246                         return ret_val;
2247
2248                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2249                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2250                                 phy_data);
2251                 if (ret_val)
2252                         return ret_val;
2253         }
2254         return E1000_SUCCESS;
2255 }
2256
2257 /*****************************************************************************
2258  *
2259  * This function sets the lplu d0 state according to the active flag.  When
2260  * activating lplu this function also disables smart speed and vise versa.
2261  * lplu will not be activated unless the device autonegotiation advertisment
2262  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2263  * hw: Struct containing variables accessed by shared code
2264  * active - true to enable lplu false to disable lplu.
2265  *
2266  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2267  *            E1000_SUCCESS at any other case.
2268  *
2269  ****************************************************************************/
2270
2271 static int32_t
2272 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2273 {
2274         uint32_t phy_ctrl = 0;
2275         int32_t ret_val;
2276         uint16_t phy_data;
2277         DEBUGFUNC();
2278
2279         if (hw->mac_type <= e1000_82547_rev_2)
2280                 return E1000_SUCCESS;
2281
2282         if (hw->mac_type == e1000_ich8lan) {
2283                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2284         } else {
2285                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2286                                 &phy_data);
2287                 if (ret_val)
2288                         return ret_val;
2289         }
2290
2291         if (!active) {
2292                 if (hw->mac_type == e1000_ich8lan) {
2293                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2294                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2295                 } else {
2296                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2297                         ret_val = e1000_write_phy_reg(hw,
2298                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2299                         if (ret_val)
2300                                 return ret_val;
2301                 }
2302
2303         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2304          * Dx states where the power conservation is most important.  During
2305          * driver activity we should enable SmartSpeed, so performance is
2306          * maintained. */
2307                 if (hw->smart_speed == e1000_smart_speed_on) {
2308                         ret_val = e1000_read_phy_reg(hw,
2309                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2310                         if (ret_val)
2311                                 return ret_val;
2312
2313                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2314                         ret_val = e1000_write_phy_reg(hw,
2315                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2316                         if (ret_val)
2317                                 return ret_val;
2318                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2319                         ret_val = e1000_read_phy_reg(hw,
2320                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2321                         if (ret_val)
2322                                 return ret_val;
2323
2324                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2325                         ret_val = e1000_write_phy_reg(hw,
2326                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2327                         if (ret_val)
2328                                 return ret_val;
2329                 }
2330
2331
2332         } else {
2333
2334                 if (hw->mac_type == e1000_ich8lan) {
2335                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2336                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2337                 } else {
2338                         phy_data |= IGP02E1000_PM_D0_LPLU;
2339                         ret_val = e1000_write_phy_reg(hw,
2340                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2341                         if (ret_val)
2342                                 return ret_val;
2343                 }
2344
2345                 /* When LPLU is enabled we should disable SmartSpeed */
2346                 ret_val = e1000_read_phy_reg(hw,
2347                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2348                 if (ret_val)
2349                         return ret_val;
2350
2351                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2352                 ret_val = e1000_write_phy_reg(hw,
2353                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2354                 if (ret_val)
2355                         return ret_val;
2356
2357         }
2358         return E1000_SUCCESS;
2359 }
2360
2361 /********************************************************************
2362 * Copper link setup for e1000_phy_igp series.
2363 *
2364 * hw - Struct containing variables accessed by shared code
2365 *********************************************************************/
2366 static int32_t
2367 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2368 {
2369         uint32_t led_ctrl;
2370         int32_t ret_val;
2371         uint16_t phy_data;
2372
2373         DEBUGFUNC();
2374
2375         if (hw->phy_reset_disable)
2376                 return E1000_SUCCESS;
2377
2378         ret_val = e1000_phy_reset(hw);
2379         if (ret_val) {
2380                 DEBUGOUT("Error Resetting the PHY\n");
2381                 return ret_val;
2382         }
2383
2384         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2385         mdelay(15);
2386         if (hw->mac_type != e1000_ich8lan) {
2387                 /* Configure activity LED after PHY reset */
2388                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2389                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2390                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2391                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2392         }
2393
2394         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2395         if (hw->phy_type == e1000_phy_igp) {
2396                 /* disable lplu d3 during driver init */
2397                 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2398                 if (ret_val) {
2399                         DEBUGOUT("Error Disabling LPLU D3\n");
2400                         return ret_val;
2401                 }
2402         }
2403
2404         /* disable lplu d0 during driver init */
2405         ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2406         if (ret_val) {
2407                 DEBUGOUT("Error Disabling LPLU D0\n");
2408                 return ret_val;
2409         }
2410         /* Configure mdi-mdix settings */
2411         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2412         if (ret_val)
2413                 return ret_val;
2414
2415         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2416                 hw->dsp_config_state = e1000_dsp_config_disabled;
2417                 /* Force MDI for earlier revs of the IGP PHY */
2418                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2419                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2420                 hw->mdix = 1;
2421
2422         } else {
2423                 hw->dsp_config_state = e1000_dsp_config_enabled;
2424                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2425
2426                 switch (hw->mdix) {
2427                 case 1:
2428                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2429                         break;
2430                 case 2:
2431                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2432                         break;
2433                 case 0:
2434                 default:
2435                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2436                         break;
2437                 }
2438         }
2439         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2440         if (ret_val)
2441                 return ret_val;
2442
2443         /* set auto-master slave resolution settings */
2444         if (hw->autoneg) {
2445                 e1000_ms_type phy_ms_setting = hw->master_slave;
2446
2447                 if (hw->ffe_config_state == e1000_ffe_config_active)
2448                         hw->ffe_config_state = e1000_ffe_config_enabled;
2449
2450                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2451                         hw->dsp_config_state = e1000_dsp_config_enabled;
2452
2453                 /* when autonegotiation advertisment is only 1000Mbps then we
2454                   * should disable SmartSpeed and enable Auto MasterSlave
2455                   * resolution as hardware default. */
2456                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2457                         /* Disable SmartSpeed */
2458                         ret_val = e1000_read_phy_reg(hw,
2459                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2460                         if (ret_val)
2461                                 return ret_val;
2462                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2463                         ret_val = e1000_write_phy_reg(hw,
2464                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2465                         if (ret_val)
2466                                 return ret_val;
2467                         /* Set auto Master/Slave resolution process */
2468                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2469                                         &phy_data);
2470                         if (ret_val)
2471                                 return ret_val;
2472                         phy_data &= ~CR_1000T_MS_ENABLE;
2473                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2474                                         phy_data);
2475                         if (ret_val)
2476                                 return ret_val;
2477                 }
2478
2479                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2480                 if (ret_val)
2481                         return ret_val;
2482
2483                 /* load defaults for future use */
2484                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2485                                 ((phy_data & CR_1000T_MS_VALUE) ?
2486                                 e1000_ms_force_master :
2487                                 e1000_ms_force_slave) :
2488                                 e1000_ms_auto;
2489
2490                 switch (phy_ms_setting) {
2491                 case e1000_ms_force_master:
2492                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2493                         break;
2494                 case e1000_ms_force_slave:
2495                         phy_data |= CR_1000T_MS_ENABLE;
2496                         phy_data &= ~(CR_1000T_MS_VALUE);
2497                         break;
2498                 case e1000_ms_auto:
2499                         phy_data &= ~CR_1000T_MS_ENABLE;
2500                 default:
2501                         break;
2502                 }
2503                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2504                 if (ret_val)
2505                         return ret_val;
2506         }
2507
2508         return E1000_SUCCESS;
2509 }
2510
2511 /*****************************************************************************
2512  * This function checks the mode of the firmware.
2513  *
2514  * returns  - TRUE when the mode is IAMT or FALSE.
2515  ****************************************************************************/
2516 boolean_t
2517 e1000_check_mng_mode(struct e1000_hw *hw)
2518 {
2519         uint32_t fwsm;
2520         DEBUGFUNC();
2521
2522         fwsm = E1000_READ_REG(hw, FWSM);
2523
2524         if (hw->mac_type == e1000_ich8lan) {
2525                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2526                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2527                         return TRUE;
2528         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2529                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2530                         return TRUE;
2531
2532         return FALSE;
2533 }
2534
2535 static int32_t
2536 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2537 {
2538         uint32_t reg_val;
2539         uint16_t swfw;
2540         DEBUGFUNC();
2541
2542         if ((hw->mac_type == e1000_80003es2lan) &&
2543                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2544                 swfw = E1000_SWFW_PHY1_SM;
2545         } else {
2546                 swfw = E1000_SWFW_PHY0_SM;
2547         }
2548         if (e1000_swfw_sync_acquire(hw, swfw))
2549                 return -E1000_ERR_SWFW_SYNC;
2550
2551         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2552                         & E1000_KUMCTRLSTA_OFFSET) | data;
2553         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2554         udelay(2);
2555
2556         return E1000_SUCCESS;
2557 }
2558
2559 static int32_t
2560 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2561 {
2562         uint32_t reg_val;
2563         uint16_t swfw;
2564         DEBUGFUNC();
2565
2566         if ((hw->mac_type == e1000_80003es2lan) &&
2567             (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2568                 swfw = E1000_SWFW_PHY1_SM;
2569         } else {
2570                 swfw = E1000_SWFW_PHY0_SM;
2571         }
2572         if (e1000_swfw_sync_acquire(hw, swfw))
2573                 return -E1000_ERR_SWFW_SYNC;
2574
2575         /* Write register address */
2576         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2577                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2578         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2579         udelay(2);
2580
2581         /* Read the data returned */
2582         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2583         *data = (uint16_t)reg_val;
2584
2585         return E1000_SUCCESS;
2586 }
2587
2588 /********************************************************************
2589 * Copper link setup for e1000_phy_gg82563 series.
2590 *
2591 * hw - Struct containing variables accessed by shared code
2592 *********************************************************************/
2593 static int32_t
2594 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2595 {
2596         int32_t ret_val;
2597         uint16_t phy_data;
2598         uint32_t reg_data;
2599
2600         DEBUGFUNC();
2601
2602         if (!hw->phy_reset_disable) {
2603                 /* Enable CRS on TX for half-duplex operation. */
2604                 ret_val = e1000_read_phy_reg(hw,
2605                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2606                 if (ret_val)
2607                         return ret_val;
2608
2609                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2610                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2611                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2612
2613                 ret_val = e1000_write_phy_reg(hw,
2614                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2615                 if (ret_val)
2616                         return ret_val;
2617
2618                 /* Options:
2619                  *   MDI/MDI-X = 0 (default)
2620                  *   0 - Auto for all speeds
2621                  *   1 - MDI mode
2622                  *   2 - MDI-X mode
2623                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2624                  */
2625                 ret_val = e1000_read_phy_reg(hw,
2626                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2627                 if (ret_val)
2628                         return ret_val;
2629
2630                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2631
2632                 switch (hw->mdix) {
2633                 case 1:
2634                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2635                         break;
2636                 case 2:
2637                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2638                         break;
2639                 case 0:
2640                 default:
2641                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2642                         break;
2643                 }
2644
2645                 /* Options:
2646                  *   disable_polarity_correction = 0 (default)
2647                  *       Automatic Correction for Reversed Cable Polarity
2648                  *   0 - Disabled
2649                  *   1 - Enabled
2650                  */
2651                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2652                 ret_val = e1000_write_phy_reg(hw,
2653                                 GG82563_PHY_SPEC_CTRL, phy_data);
2654
2655                 if (ret_val)
2656                         return ret_val;
2657
2658                 /* SW Reset the PHY so all changes take effect */
2659                 ret_val = e1000_phy_reset(hw);
2660                 if (ret_val) {
2661                         DEBUGOUT("Error Resetting the PHY\n");
2662                         return ret_val;
2663                 }
2664         } /* phy_reset_disable */
2665
2666         if (hw->mac_type == e1000_80003es2lan) {
2667                 /* Bypass RX and TX FIFO's */
2668                 ret_val = e1000_write_kmrn_reg(hw,
2669                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2670                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2671                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2672                 if (ret_val)
2673                         return ret_val;
2674
2675                 ret_val = e1000_read_phy_reg(hw,
2676                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2677                 if (ret_val)
2678                         return ret_val;
2679
2680                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2681                 ret_val = e1000_write_phy_reg(hw,
2682                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2683
2684                 if (ret_val)
2685                         return ret_val;
2686
2687                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2688                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2689                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2690
2691                 ret_val = e1000_read_phy_reg(hw,
2692                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2693                 if (ret_val)
2694                         return ret_val;
2695
2696         /* Do not init these registers when the HW is in IAMT mode, since the
2697          * firmware will have already initialized them.  We only initialize
2698          * them if the HW is not in IAMT mode.
2699          */
2700                 if (e1000_check_mng_mode(hw) == FALSE) {
2701                         /* Enable Electrical Idle on the PHY */
2702                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2703                         ret_val = e1000_write_phy_reg(hw,
2704                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2705                         if (ret_val)
2706                                 return ret_val;
2707
2708                         ret_val = e1000_read_phy_reg(hw,
2709                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2710                         if (ret_val)
2711                                 return ret_val;
2712
2713                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2714                         ret_val = e1000_write_phy_reg(hw,
2715                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2716
2717                         if (ret_val)
2718                                 return ret_val;
2719                 }
2720
2721                 /* Workaround: Disable padding in Kumeran interface in the MAC
2722                  * and in the PHY to avoid CRC errors.
2723                  */
2724                 ret_val = e1000_read_phy_reg(hw,
2725                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2726                 if (ret_val)
2727                         return ret_val;
2728                 phy_data |= GG82563_ICR_DIS_PADDING;
2729                 ret_val = e1000_write_phy_reg(hw,
2730                                 GG82563_PHY_INBAND_CTRL, phy_data);
2731                 if (ret_val)
2732                         return ret_val;
2733         }
2734         return E1000_SUCCESS;
2735 }
2736
2737 /********************************************************************
2738 * Copper link setup for e1000_phy_m88 series.
2739 *
2740 * hw - Struct containing variables accessed by shared code
2741 *********************************************************************/
2742 static int32_t
2743 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2744 {
2745         int32_t ret_val;
2746         uint16_t phy_data;
2747
2748         DEBUGFUNC();
2749
2750         if (hw->phy_reset_disable)
2751                 return E1000_SUCCESS;
2752
2753         /* Enable CRS on TX. This must be set for half-duplex operation. */
2754         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2755         if (ret_val)
2756                 return ret_val;
2757
2758         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2759
2760         /* Options:
2761          *   MDI/MDI-X = 0 (default)
2762          *   0 - Auto for all speeds
2763          *   1 - MDI mode
2764          *   2 - MDI-X mode
2765          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2766          */
2767         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2768
2769         switch (hw->mdix) {
2770         case 1:
2771                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2772                 break;
2773         case 2:
2774                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2775                 break;
2776         case 3:
2777                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2778                 break;
2779         case 0:
2780         default:
2781                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2782                 break;
2783         }
2784
2785         /* Options:
2786          *   disable_polarity_correction = 0 (default)
2787          *       Automatic Correction for Reversed Cable Polarity
2788          *   0 - Disabled
2789          *   1 - Enabled
2790          */
2791         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2792         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2793         if (ret_val)
2794                 return ret_val;
2795
2796         if (hw->phy_revision < M88E1011_I_REV_4) {
2797                 /* Force TX_CLK in the Extended PHY Specific Control Register
2798                  * to 25MHz clock.
2799                  */
2800                 ret_val = e1000_read_phy_reg(hw,
2801                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2802                 if (ret_val)
2803                         return ret_val;
2804
2805                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2806
2807                 if ((hw->phy_revision == E1000_REVISION_2) &&
2808                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2809                         /* Vidalia Phy, set the downshift counter to 5x */
2810                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2811                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2812                         ret_val = e1000_write_phy_reg(hw,
2813                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2814                         if (ret_val)
2815                                 return ret_val;
2816                 } else {
2817                         /* Configure Master and Slave downshift values */
2818                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2819                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2820                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2821                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2822                         ret_val = e1000_write_phy_reg(hw,
2823                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2824                         if (ret_val)
2825                                 return ret_val;
2826                 }
2827         }
2828
2829         /* SW Reset the PHY so all changes take effect */
2830         ret_val = e1000_phy_reset(hw);
2831         if (ret_val) {
2832                 DEBUGOUT("Error Resetting the PHY\n");
2833                 return ret_val;
2834         }
2835
2836         return E1000_SUCCESS;
2837 }
2838
2839 /********************************************************************
2840 * Setup auto-negotiation and flow control advertisements,
2841 * and then perform auto-negotiation.
2842 *
2843 * hw - Struct containing variables accessed by shared code
2844 *********************************************************************/
2845 static int32_t
2846 e1000_copper_link_autoneg(struct e1000_hw *hw)
2847 {
2848         int32_t ret_val;
2849         uint16_t phy_data;
2850
2851         DEBUGFUNC();
2852
2853         /* Perform some bounds checking on the hw->autoneg_advertised
2854          * parameter.  If this variable is zero, then set it to the default.
2855          */
2856         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2857
2858         /* If autoneg_advertised is zero, we assume it was not defaulted
2859          * by the calling code so we set to advertise full capability.
2860          */
2861         if (hw->autoneg_advertised == 0)
2862                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2863
2864         /* IFE phy only supports 10/100 */
2865         if (hw->phy_type == e1000_phy_ife)
2866                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2867
2868         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2869         ret_val = e1000_phy_setup_autoneg(hw);
2870         if (ret_val) {
2871                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2872                 return ret_val;
2873         }
2874         DEBUGOUT("Restarting Auto-Neg\n");
2875
2876         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2877          * the Auto Neg Restart bit in the PHY control register.
2878          */
2879         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2880         if (ret_val)
2881                 return ret_val;
2882
2883         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2884         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2885         if (ret_val)
2886                 return ret_val;
2887
2888         /* Does the user want to wait for Auto-Neg to complete here, or
2889          * check at a later time (for example, callback routine).
2890          */
2891         /* If we do not wait for autonegtation to complete I
2892          * do not see a valid link status.
2893          * wait_autoneg_complete = 1 .
2894          */
2895         if (hw->wait_autoneg_complete) {
2896                 ret_val = e1000_wait_autoneg(hw);
2897                 if (ret_val) {
2898                         DEBUGOUT("Error while waiting for autoneg"
2899                                         "to complete\n");
2900                         return ret_val;
2901                 }
2902         }
2903
2904         hw->get_link_status = TRUE;
2905
2906         return E1000_SUCCESS;
2907 }
2908
2909 /******************************************************************************
2910 * Config the MAC and the PHY after link is up.
2911 *   1) Set up the MAC to the current PHY speed/duplex
2912 *      if we are on 82543.  If we
2913 *      are on newer silicon, we only need to configure
2914 *      collision distance in the Transmit Control Register.
2915 *   2) Set up flow control on the MAC to that established with
2916 *      the link partner.
2917 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
2918 *
2919 * hw - Struct containing variables accessed by shared code
2920 ******************************************************************************/
2921 static int32_t
2922 e1000_copper_link_postconfig(struct e1000_hw *hw)
2923 {
2924         int32_t ret_val;
2925         DEBUGFUNC();
2926
2927         if (hw->mac_type >= e1000_82544) {
2928                 e1000_config_collision_dist(hw);
2929         } else {
2930                 ret_val = e1000_config_mac_to_phy(hw);
2931                 if (ret_val) {
2932                         DEBUGOUT("Error configuring MAC to PHY settings\n");
2933                         return ret_val;
2934                 }
2935         }
2936         ret_val = e1000_config_fc_after_link_up(hw);
2937         if (ret_val) {
2938                 DEBUGOUT("Error Configuring Flow Control\n");
2939                 return ret_val;
2940         }
2941         return E1000_SUCCESS;
2942 }
2943
2944 /******************************************************************************
2945 * Detects which PHY is present and setup the speed and duplex
2946 *
2947 * hw - Struct containing variables accessed by shared code
2948 ******************************************************************************/
2949 static int
2950 e1000_setup_copper_link(struct eth_device *nic)
2951 {
2952         struct e1000_hw *hw = nic->priv;
2953         int32_t ret_val;
2954         uint16_t i;
2955         uint16_t phy_data;
2956         uint16_t reg_data;
2957
2958         DEBUGFUNC();
2959
2960         switch (hw->mac_type) {
2961         case e1000_80003es2lan:
2962         case e1000_ich8lan:
2963                 /* Set the mac to wait the maximum time between each
2964                  * iteration and increase the max iterations when
2965                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2966                 ret_val = e1000_write_kmrn_reg(hw,
2967                                 GG82563_REG(0x34, 4), 0xFFFF);
2968                 if (ret_val)
2969                         return ret_val;
2970                 ret_val = e1000_read_kmrn_reg(hw,
2971                                 GG82563_REG(0x34, 9), &reg_data);
2972                 if (ret_val)
2973                         return ret_val;
2974                 reg_data |= 0x3F;
2975                 ret_val = e1000_write_kmrn_reg(hw,
2976                                 GG82563_REG(0x34, 9), reg_data);
2977                 if (ret_val)
2978                         return ret_val;
2979         default:
2980                 break;
2981         }
2982
2983         /* Check if it is a valid PHY and set PHY mode if necessary. */
2984         ret_val = e1000_copper_link_preconfig(hw);
2985         if (ret_val)
2986                 return ret_val;
2987         switch (hw->mac_type) {
2988         case e1000_80003es2lan:
2989                 /* Kumeran registers are written-only */
2990                 reg_data =
2991                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2992                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2993                 ret_val = e1000_write_kmrn_reg(hw,
2994                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
2995                 if (ret_val)
2996                         return ret_val;
2997                 break;
2998         default:
2999                 break;
3000         }
3001
3002         if (hw->phy_type == e1000_phy_igp ||
3003                 hw->phy_type == e1000_phy_igp_3 ||
3004                 hw->phy_type == e1000_phy_igp_2) {
3005                 ret_val = e1000_copper_link_igp_setup(hw);
3006                 if (ret_val)
3007                         return ret_val;
3008         } else if (hw->phy_type == e1000_phy_m88) {
3009                 ret_val = e1000_copper_link_mgp_setup(hw);
3010                 if (ret_val)
3011                         return ret_val;
3012         } else if (hw->phy_type == e1000_phy_gg82563) {
3013                 ret_val = e1000_copper_link_ggp_setup(hw);
3014                 if (ret_val)
3015                         return ret_val;
3016         }
3017
3018         /* always auto */
3019         /* Setup autoneg and flow control advertisement
3020           * and perform autonegotiation */
3021         ret_val = e1000_copper_link_autoneg(hw);
3022         if (ret_val)
3023                 return ret_val;
3024
3025         /* Check link status. Wait up to 100 microseconds for link to become
3026          * valid.
3027          */
3028         for (i = 0; i < 10; i++) {
3029                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3030                 if (ret_val)
3031                         return ret_val;
3032                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3033                 if (ret_val)
3034                         return ret_val;
3035
3036                 if (phy_data & MII_SR_LINK_STATUS) {
3037                         /* Config the MAC and PHY after link is up */
3038                         ret_val = e1000_copper_link_postconfig(hw);
3039                         if (ret_val)
3040                                 return ret_val;
3041
3042                         DEBUGOUT("Valid link established!!!\n");
3043                         return E1000_SUCCESS;
3044                 }
3045                 udelay(10);
3046         }
3047
3048         DEBUGOUT("Unable to establish link!!!\n");
3049         return E1000_SUCCESS;
3050 }
3051
3052 /******************************************************************************
3053 * Configures PHY autoneg and flow control advertisement settings
3054 *
3055 * hw - Struct containing variables accessed by shared code
3056 ******************************************************************************/
3057 int32_t
3058 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3059 {
3060         int32_t ret_val;
3061         uint16_t mii_autoneg_adv_reg;
3062         uint16_t mii_1000t_ctrl_reg;
3063
3064         DEBUGFUNC();
3065
3066         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3067         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3068         if (ret_val)
3069                 return ret_val;
3070
3071         if (hw->phy_type != e1000_phy_ife) {
3072                 /* Read the MII 1000Base-T Control Register (Address 9). */
3073                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3074                                 &mii_1000t_ctrl_reg);
3075                 if (ret_val)
3076                         return ret_val;
3077         } else
3078                 mii_1000t_ctrl_reg = 0;
3079
3080         /* Need to parse both autoneg_advertised and fc and set up
3081          * the appropriate PHY registers.  First we will parse for
3082          * autoneg_advertised software override.  Since we can advertise
3083          * a plethora of combinations, we need to check each bit
3084          * individually.
3085          */
3086
3087         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3088          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3089          * the  1000Base-T Control Register (Address 9).
3090          */
3091         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3092         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3093
3094         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3095
3096         /* Do we want to advertise 10 Mb Half Duplex? */
3097         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3098                 DEBUGOUT("Advertise 10mb Half duplex\n");
3099                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3100         }
3101
3102         /* Do we want to advertise 10 Mb Full Duplex? */
3103         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3104                 DEBUGOUT("Advertise 10mb Full duplex\n");
3105                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3106         }
3107
3108         /* Do we want to advertise 100 Mb Half Duplex? */
3109         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3110                 DEBUGOUT("Advertise 100mb Half duplex\n");
3111                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3112         }
3113
3114         /* Do we want to advertise 100 Mb Full Duplex? */
3115         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3116                 DEBUGOUT("Advertise 100mb Full duplex\n");
3117                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3118         }
3119
3120         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3121         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3122                 DEBUGOUT
3123                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3124         }
3125
3126         /* Do we want to advertise 1000 Mb Full Duplex? */
3127         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3128                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3129                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3130         }
3131
3132         /* Check for a software override of the flow control settings, and
3133          * setup the PHY advertisement registers accordingly.  If
3134          * auto-negotiation is enabled, then software will have to set the
3135          * "PAUSE" bits to the correct value in the Auto-Negotiation
3136          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3137          *
3138          * The possible values of the "fc" parameter are:
3139          *      0:  Flow control is completely disabled
3140          *      1:  Rx flow control is enabled (we can receive pause frames
3141          *          but not send pause frames).
3142          *      2:  Tx flow control is enabled (we can send pause frames
3143          *          but we do not support receiving pause frames).
3144          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3145          *  other:  No software override.  The flow control configuration
3146          *          in the EEPROM is used.
3147          */
3148         switch (hw->fc) {
3149         case e1000_fc_none:     /* 0 */
3150                 /* Flow control (RX & TX) is completely disabled by a
3151                  * software over-ride.
3152                  */
3153                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3154                 break;
3155         case e1000_fc_rx_pause: /* 1 */
3156                 /* RX Flow control is enabled, and TX Flow control is
3157                  * disabled, by a software over-ride.
3158                  */
3159                 /* Since there really isn't a way to advertise that we are
3160                  * capable of RX Pause ONLY, we will advertise that we
3161                  * support both symmetric and asymmetric RX PAUSE.  Later
3162                  * (in e1000_config_fc_after_link_up) we will disable the
3163                  *hw's ability to send PAUSE frames.
3164                  */
3165                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3166                 break;
3167         case e1000_fc_tx_pause: /* 2 */
3168                 /* TX Flow control is enabled, and RX Flow control is
3169                  * disabled, by a software over-ride.
3170                  */
3171                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3172                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3173                 break;
3174         case e1000_fc_full:     /* 3 */
3175                 /* Flow control (both RX and TX) is enabled by a software
3176                  * over-ride.
3177                  */
3178                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3179                 break;
3180         default:
3181                 DEBUGOUT("Flow control param set incorrectly\n");
3182                 return -E1000_ERR_CONFIG;
3183         }
3184
3185         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3186         if (ret_val)
3187                 return ret_val;
3188
3189         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3190
3191         if (hw->phy_type != e1000_phy_ife) {
3192                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3193                                 mii_1000t_ctrl_reg);
3194                 if (ret_val)
3195                         return ret_val;
3196         }
3197
3198         return E1000_SUCCESS;
3199 }
3200
3201 /******************************************************************************
3202 * Sets the collision distance in the Transmit Control register
3203 *
3204 * hw - Struct containing variables accessed by shared code
3205 *
3206 * Link should have been established previously. Reads the speed and duplex
3207 * information from the Device Status register.
3208 ******************************************************************************/
3209 static void
3210 e1000_config_collision_dist(struct e1000_hw *hw)
3211 {
3212         uint32_t tctl, coll_dist;
3213
3214         DEBUGFUNC();
3215
3216         if (hw->mac_type < e1000_82543)
3217                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3218         else
3219                 coll_dist = E1000_COLLISION_DISTANCE;
3220
3221         tctl = E1000_READ_REG(hw, TCTL);
3222
3223         tctl &= ~E1000_TCTL_COLD;
3224         tctl |= coll_dist << E1000_COLD_SHIFT;
3225
3226         E1000_WRITE_REG(hw, TCTL, tctl);
3227         E1000_WRITE_FLUSH(hw);
3228 }
3229
3230 /******************************************************************************
3231 * Sets MAC speed and duplex settings to reflect the those in the PHY
3232 *
3233 * hw - Struct containing variables accessed by shared code
3234 * mii_reg - data to write to the MII control register
3235 *
3236 * The contents of the PHY register containing the needed information need to
3237 * be passed in.
3238 ******************************************************************************/
3239 static int
3240 e1000_config_mac_to_phy(struct e1000_hw *hw)
3241 {
3242         uint32_t ctrl;
3243         uint16_t phy_data;
3244
3245         DEBUGFUNC();
3246
3247         /* Read the Device Control Register and set the bits to Force Speed
3248          * and Duplex.
3249          */
3250         ctrl = E1000_READ_REG(hw, CTRL);
3251         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3252         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3253
3254         /* Set up duplex in the Device Control and Transmit Control
3255          * registers depending on negotiated values.
3256          */
3257         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3258                 DEBUGOUT("PHY Read Error\n");
3259                 return -E1000_ERR_PHY;
3260         }
3261         if (phy_data & M88E1000_PSSR_DPLX)
3262                 ctrl |= E1000_CTRL_FD;
3263         else
3264                 ctrl &= ~E1000_CTRL_FD;
3265
3266         e1000_config_collision_dist(hw);
3267
3268         /* Set up speed in the Device Control register depending on
3269          * negotiated values.
3270          */
3271         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3272                 ctrl |= E1000_CTRL_SPD_1000;
3273         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3274                 ctrl |= E1000_CTRL_SPD_100;
3275         /* Write the configured values back to the Device Control Reg. */
3276         E1000_WRITE_REG(hw, CTRL, ctrl);
3277         return 0;
3278 }
3279
3280 /******************************************************************************
3281  * Forces the MAC's flow control settings.
3282  *
3283  * hw - Struct containing variables accessed by shared code
3284  *
3285  * Sets the TFCE and RFCE bits in the device control register to reflect
3286  * the adapter settings. TFCE and RFCE need to be explicitly set by
3287  * software when a Copper PHY is used because autonegotiation is managed
3288  * by the PHY rather than the MAC. Software must also configure these
3289  * bits when link is forced on a fiber connection.
3290  *****************************************************************************/
3291 static int
3292 e1000_force_mac_fc(struct e1000_hw *hw)
3293 {
3294         uint32_t ctrl;
3295
3296         DEBUGFUNC();
3297
3298         /* Get the current configuration of the Device Control Register */
3299         ctrl = E1000_READ_REG(hw, CTRL);
3300
3301         /* Because we didn't get link via the internal auto-negotiation
3302          * mechanism (we either forced link or we got link via PHY
3303          * auto-neg), we have to manually enable/disable transmit an
3304          * receive flow control.
3305          *
3306          * The "Case" statement below enables/disable flow control
3307          * according to the "hw->fc" parameter.
3308          *
3309          * The possible values of the "fc" parameter are:
3310          *      0:  Flow control is completely disabled
3311          *      1:  Rx flow control is enabled (we can receive pause
3312          *          frames but not send pause frames).
3313          *      2:  Tx flow control is enabled (we can send pause frames
3314          *          frames but we do not receive pause frames).
3315          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3316          *  other:  No other values should be possible at this point.
3317          */
3318
3319         switch (hw->fc) {
3320         case e1000_fc_none:
3321                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3322                 break;
3323         case e1000_fc_rx_pause:
3324                 ctrl &= (~E1000_CTRL_TFCE);
3325                 ctrl |= E1000_CTRL_RFCE;
3326                 break;
3327         case e1000_fc_tx_pause:
3328                 ctrl &= (~E1000_CTRL_RFCE);
3329                 ctrl |= E1000_CTRL_TFCE;
3330                 break;
3331         case e1000_fc_full:
3332                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3333                 break;
3334         default:
3335                 DEBUGOUT("Flow control param set incorrectly\n");
3336                 return -E1000_ERR_CONFIG;
3337         }
3338
3339         /* Disable TX Flow Control for 82542 (rev 2.0) */
3340         if (hw->mac_type == e1000_82542_rev2_0)
3341                 ctrl &= (~E1000_CTRL_TFCE);
3342
3343         E1000_WRITE_REG(hw, CTRL, ctrl);
3344         return 0;
3345 }
3346
3347 /******************************************************************************
3348  * Configures flow control settings after link is established
3349  *
3350  * hw - Struct containing variables accessed by shared code
3351  *
3352  * Should be called immediately after a valid link has been established.
3353  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3354  * and autonegotiation is enabled, the MAC flow control settings will be set
3355  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3356  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3357  *****************************************************************************/
3358 static int32_t
3359 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3360 {
3361         int32_t ret_val;
3362         uint16_t mii_status_reg;
3363         uint16_t mii_nway_adv_reg;
3364         uint16_t mii_nway_lp_ability_reg;
3365         uint16_t speed;
3366         uint16_t duplex;
3367
3368         DEBUGFUNC();
3369
3370         /* Check for the case where we have fiber media and auto-neg failed
3371          * so we had to force link.  In this case, we need to force the
3372          * configuration of the MAC to match the "fc" parameter.
3373          */
3374         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3375                 || ((hw->media_type == e1000_media_type_internal_serdes)
3376                 && (hw->autoneg_failed))
3377                 || ((hw->media_type == e1000_media_type_copper)
3378                 && (!hw->autoneg))) {
3379                 ret_val = e1000_force_mac_fc(hw);
3380                 if (ret_val < 0) {
3381                         DEBUGOUT("Error forcing flow control settings\n");
3382                         return ret_val;
3383                 }
3384         }
3385
3386         /* Check for the case where we have copper media and auto-neg is
3387          * enabled.  In this case, we need to check and see if Auto-Neg
3388          * has completed, and if so, how the PHY and link partner has
3389          * flow control configured.
3390          */
3391         if (hw->media_type == e1000_media_type_copper) {
3392                 /* Read the MII Status Register and check to see if AutoNeg
3393                  * has completed.  We read this twice because this reg has
3394                  * some "sticky" (latched) bits.
3395                  */
3396                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3397                         DEBUGOUT("PHY Read Error \n");
3398                         return -E1000_ERR_PHY;
3399                 }
3400                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3401                         DEBUGOUT("PHY Read Error \n");
3402                         return -E1000_ERR_PHY;
3403                 }
3404
3405                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3406                         /* The AutoNeg process has completed, so we now need to
3407                          * read both the Auto Negotiation Advertisement Register
3408                          * (Address 4) and the Auto_Negotiation Base Page Ability
3409                          * Register (Address 5) to determine how flow control was
3410                          * negotiated.
3411                          */
3412                         if (e1000_read_phy_reg
3413                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3414                                 DEBUGOUT("PHY Read Error\n");
3415                                 return -E1000_ERR_PHY;
3416                         }
3417                         if (e1000_read_phy_reg
3418                             (hw, PHY_LP_ABILITY,
3419                              &mii_nway_lp_ability_reg) < 0) {
3420                                 DEBUGOUT("PHY Read Error\n");
3421                                 return -E1000_ERR_PHY;
3422                         }
3423
3424                         /* Two bits in the Auto Negotiation Advertisement Register
3425                          * (Address 4) and two bits in the Auto Negotiation Base
3426                          * Page Ability Register (Address 5) determine flow control
3427                          * for both the PHY and the link partner.  The following
3428                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3429                          * 1999, describes these PAUSE resolution bits and how flow
3430                          * control is determined based upon these settings.
3431                          * NOTE:  DC = Don't Care
3432                          *
3433                          *   LOCAL DEVICE  |   LINK PARTNER
3434                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3435                          *-------|---------|-------|---------|--------------------
3436                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3437                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3438                          *   0   |    1    |   1   |    0    | e1000_fc_none
3439                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3440                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3441                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3442                          *   1   |    1    |   0   |    0    | e1000_fc_none
3443                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3444                          *
3445                          */
3446                         /* Are both PAUSE bits set to 1?  If so, this implies
3447                          * Symmetric Flow Control is enabled at both ends.  The
3448                          * ASM_DIR bits are irrelevant per the spec.
3449                          *
3450                          * For Symmetric Flow Control:
3451                          *
3452                          *   LOCAL DEVICE  |   LINK PARTNER
3453                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3454                          *-------|---------|-------|---------|--------------------
3455                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3456                          *
3457                          */
3458                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3459                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3460                                 /* Now we need to check if the user selected RX ONLY
3461                                  * of pause frames.  In this case, we had to advertise
3462                                  * FULL flow control because we could not advertise RX
3463                                  * ONLY. Hence, we must now check to see if we need to
3464                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3465                                  */
3466                                 if (hw->original_fc == e1000_fc_full) {
3467                                         hw->fc = e1000_fc_full;
3468                                         DEBUGOUT("Flow Control = FULL.\r\n");
3469                                 } else {
3470                                         hw->fc = e1000_fc_rx_pause;
3471                                         DEBUGOUT
3472                                             ("Flow Control = RX PAUSE frames only.\r\n");
3473                                 }
3474                         }
3475                         /* For receiving PAUSE frames ONLY.
3476                          *
3477                          *   LOCAL DEVICE  |   LINK PARTNER
3478                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3479                          *-------|---------|-------|---------|--------------------
3480                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3481                          *
3482                          */
3483                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3484                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3485                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3486                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3487                         {
3488                                 hw->fc = e1000_fc_tx_pause;
3489                                 DEBUGOUT
3490                                     ("Flow Control = TX PAUSE frames only.\r\n");
3491                         }
3492                         /* For transmitting PAUSE frames ONLY.
3493                          *
3494                          *   LOCAL DEVICE  |   LINK PARTNER
3495                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3496                          *-------|---------|-------|---------|--------------------
3497                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3498                          *
3499                          */
3500                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3501                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3502                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3503                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3504                         {
3505                                 hw->fc = e1000_fc_rx_pause;
3506                                 DEBUGOUT
3507                                     ("Flow Control = RX PAUSE frames only.\r\n");
3508                         }
3509                         /* Per the IEEE spec, at this point flow control should be
3510                          * disabled.  However, we want to consider that we could
3511                          * be connected to a legacy switch that doesn't advertise
3512                          * desired flow control, but can be forced on the link
3513                          * partner.  So if we advertised no flow control, that is
3514                          * what we will resolve to.  If we advertised some kind of
3515                          * receive capability (Rx Pause Only or Full Flow Control)
3516                          * and the link partner advertised none, we will configure
3517                          * ourselves to enable Rx Flow Control only.  We can do
3518                          * this safely for two reasons:  If the link partner really
3519                          * didn't want flow control enabled, and we enable Rx, no
3520                          * harm done since we won't be receiving any PAUSE frames
3521                          * anyway.  If the intent on the link partner was to have
3522                          * flow control enabled, then by us enabling RX only, we
3523                          * can at least receive pause frames and process them.
3524                          * This is a good idea because in most cases, since we are
3525                          * predominantly a server NIC, more times than not we will
3526                          * be asked to delay transmission of packets than asking
3527                          * our link partner to pause transmission of frames.
3528                          */
3529                         else if (hw->original_fc == e1000_fc_none ||
3530                                  hw->original_fc == e1000_fc_tx_pause) {
3531                                 hw->fc = e1000_fc_none;
3532                                 DEBUGOUT("Flow Control = NONE.\r\n");
3533                         } else {
3534                                 hw->fc = e1000_fc_rx_pause;
3535                                 DEBUGOUT
3536                                     ("Flow Control = RX PAUSE frames only.\r\n");
3537                         }
3538
3539                         /* Now we need to do one last check...  If we auto-
3540                          * negotiated to HALF DUPLEX, flow control should not be
3541                          * enabled per IEEE 802.3 spec.
3542                          */
3543                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3544
3545                         if (duplex == HALF_DUPLEX)
3546                                 hw->fc = e1000_fc_none;
3547
3548                         /* Now we call a subroutine to actually force the MAC
3549                          * controller to use the correct flow control settings.
3550                          */
3551                         ret_val = e1000_force_mac_fc(hw);
3552                         if (ret_val < 0) {
3553                                 DEBUGOUT
3554                                     ("Error forcing flow control settings\n");
3555                                 return ret_val;
3556                         }
3557                 } else {
3558                         DEBUGOUT
3559                             ("Copper PHY and Auto Neg has not completed.\r\n");
3560                 }
3561         }
3562         return E1000_SUCCESS;
3563 }
3564
3565 /******************************************************************************
3566  * Checks to see if the link status of the hardware has changed.
3567  *
3568  * hw - Struct containing variables accessed by shared code
3569  *
3570  * Called by any function that needs to check the link status of the adapter.
3571  *****************************************************************************/
3572 static int
3573 e1000_check_for_link(struct eth_device *nic)
3574 {
3575         struct e1000_hw *hw = nic->priv;
3576         uint32_t rxcw;
3577         uint32_t ctrl;
3578         uint32_t status;
3579         uint32_t rctl;
3580         uint32_t signal;
3581         int32_t ret_val;
3582         uint16_t phy_data;
3583         uint16_t lp_capability;
3584
3585         DEBUGFUNC();
3586
3587         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3588          * set when the optics detect a signal. On older adapters, it will be
3589          * cleared when there is a signal
3590          */
3591         ctrl = E1000_READ_REG(hw, CTRL);
3592         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3593                 signal = E1000_CTRL_SWDPIN1;
3594         else
3595                 signal = 0;
3596
3597         status = E1000_READ_REG(hw, STATUS);
3598         rxcw = E1000_READ_REG(hw, RXCW);
3599         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3600
3601         /* If we have a copper PHY then we only want to go out to the PHY
3602          * registers to see if Auto-Neg has completed and/or if our link
3603          * status has changed.  The get_link_status flag will be set if we
3604          * receive a Link Status Change interrupt or we have Rx Sequence
3605          * Errors.
3606          */
3607         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3608                 /* First we want to see if the MII Status Register reports
3609                  * link.  If so, then we want to get the current speed/duplex
3610                  * of the PHY.
3611                  * Read the register twice since the link bit is sticky.
3612                  */
3613                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3614                         DEBUGOUT("PHY Read Error\n");
3615                         return -E1000_ERR_PHY;
3616                 }
3617                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3618                         DEBUGOUT("PHY Read Error\n");
3619                         return -E1000_ERR_PHY;
3620                 }
3621
3622                 if (phy_data & MII_SR_LINK_STATUS) {
3623                         hw->get_link_status = FALSE;
3624                 } else {
3625                         /* No link detected */
3626                         return -E1000_ERR_NOLINK;
3627                 }
3628
3629                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3630                  * have Si on board that is 82544 or newer, Auto
3631                  * Speed Detection takes care of MAC speed/duplex
3632                  * configuration.  So we only need to configure Collision
3633                  * Distance in the MAC.  Otherwise, we need to force
3634                  * speed/duplex on the MAC to the current PHY speed/duplex
3635                  * settings.
3636                  */
3637                 if (hw->mac_type >= e1000_82544)
3638                         e1000_config_collision_dist(hw);
3639                 else {
3640                         ret_val = e1000_config_mac_to_phy(hw);
3641                         if (ret_val < 0) {
3642                                 DEBUGOUT
3643                                     ("Error configuring MAC to PHY settings\n");
3644                                 return ret_val;
3645                         }
3646                 }
3647
3648                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3649                  * need to restore the desired flow control settings because we may
3650                  * have had to re-autoneg with a different link partner.
3651                  */
3652                 ret_val = e1000_config_fc_after_link_up(hw);
3653                 if (ret_val < 0) {
3654                         DEBUGOUT("Error configuring flow control\n");
3655                         return ret_val;
3656                 }
3657
3658                 /* At this point we know that we are on copper and we have
3659                  * auto-negotiated link.  These are conditions for checking the link
3660                  * parter capability register.  We use the link partner capability to
3661                  * determine if TBI Compatibility needs to be turned on or off.  If
3662                  * the link partner advertises any speed in addition to Gigabit, then
3663                  * we assume that they are GMII-based, and TBI compatibility is not
3664                  * needed. If no other speeds are advertised, we assume the link
3665                  * partner is TBI-based, and we turn on TBI Compatibility.
3666                  */
3667                 if (hw->tbi_compatibility_en) {
3668                         if (e1000_read_phy_reg
3669                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3670                                 DEBUGOUT("PHY Read Error\n");
3671                                 return -E1000_ERR_PHY;
3672                         }
3673                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3674                                              NWAY_LPAR_10T_FD_CAPS |
3675                                              NWAY_LPAR_100TX_HD_CAPS |
3676                                              NWAY_LPAR_100TX_FD_CAPS |
3677                                              NWAY_LPAR_100T4_CAPS)) {
3678                                 /* If our link partner advertises anything in addition to
3679                                  * gigabit, we do not need to enable TBI compatibility.
3680                                  */
3681                                 if (hw->tbi_compatibility_on) {
3682                                         /* If we previously were in the mode, turn it off. */
3683                                         rctl = E1000_READ_REG(hw, RCTL);
3684                                         rctl &= ~E1000_RCTL_SBP;
3685                                         E1000_WRITE_REG(hw, RCTL, rctl);
3686                                         hw->tbi_compatibility_on = FALSE;
3687                                 }
3688                         } else {
3689                                 /* If TBI compatibility is was previously off, turn it on. For
3690                                  * compatibility with a TBI link partner, we will store bad
3691                                  * packets. Some frames have an additional byte on the end and
3692                                  * will look like CRC errors to to the hardware.
3693                                  */
3694                                 if (!hw->tbi_compatibility_on) {
3695                                         hw->tbi_compatibility_on = TRUE;
3696                                         rctl = E1000_READ_REG(hw, RCTL);
3697                                         rctl |= E1000_RCTL_SBP;
3698                                         E1000_WRITE_REG(hw, RCTL, rctl);
3699                                 }
3700                         }
3701                 }
3702         }
3703         /* If we don't have link (auto-negotiation failed or link partner cannot
3704          * auto-negotiate), the cable is plugged in (we have signal), and our
3705          * link partner is not trying to auto-negotiate with us (we are receiving
3706          * idles or data), we need to force link up. We also need to give
3707          * auto-negotiation time to complete, in case the cable was just plugged
3708          * in. The autoneg_failed flag does this.
3709          */
3710         else if ((hw->media_type == e1000_media_type_fiber) &&
3711                  (!(status & E1000_STATUS_LU)) &&
3712                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3713                  (!(rxcw & E1000_RXCW_C))) {
3714                 if (hw->autoneg_failed == 0) {
3715                         hw->autoneg_failed = 1;
3716                         return 0;
3717                 }
3718                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3719
3720                 /* Disable auto-negotiation in the TXCW register */
3721                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3722
3723                 /* Force link-up and also force full-duplex. */
3724                 ctrl = E1000_READ_REG(hw, CTRL);
3725                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3726                 E1000_WRITE_REG(hw, CTRL, ctrl);
3727
3728                 /* Configure Flow Control after forcing link up. */
3729                 ret_val = e1000_config_fc_after_link_up(hw);
3730                 if (ret_val < 0) {
3731                         DEBUGOUT("Error configuring flow control\n");
3732                         return ret_val;
3733                 }
3734         }
3735         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3736          * auto-negotiation in the TXCW register and disable forced link in the
3737          * Device Control register in an attempt to auto-negotiate with our link
3738          * partner.
3739          */
3740         else if ((hw->media_type == e1000_media_type_fiber) &&
3741                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3742                 DEBUGOUT
3743                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3744                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3745                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3746         }
3747         return 0;
3748 }
3749
3750 /******************************************************************************
3751 * Configure the MAC-to-PHY interface for 10/100Mbps
3752 *
3753 * hw - Struct containing variables accessed by shared code
3754 ******************************************************************************/
3755 static int32_t
3756 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3757 {
3758         int32_t ret_val = E1000_SUCCESS;
3759         uint32_t tipg;
3760         uint16_t reg_data;
3761
3762         DEBUGFUNC();
3763
3764         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3765         ret_val = e1000_write_kmrn_reg(hw,
3766                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3767         if (ret_val)
3768                 return ret_val;
3769
3770         /* Configure Transmit Inter-Packet Gap */
3771         tipg = E1000_READ_REG(hw, TIPG);
3772         tipg &= ~E1000_TIPG_IPGT_MASK;
3773         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3774         E1000_WRITE_REG(hw, TIPG, tipg);
3775
3776         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3777
3778         if (ret_val)
3779                 return ret_val;
3780
3781         if (duplex == HALF_DUPLEX)
3782                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3783         else
3784                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3785
3786         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3787
3788         return ret_val;
3789 }
3790
3791 static int32_t
3792 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3793 {
3794         int32_t ret_val = E1000_SUCCESS;
3795         uint16_t reg_data;
3796         uint32_t tipg;
3797
3798         DEBUGFUNC();
3799
3800         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3801         ret_val = e1000_write_kmrn_reg(hw,
3802                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3803         if (ret_val)
3804                 return ret_val;
3805
3806         /* Configure Transmit Inter-Packet Gap */
3807         tipg = E1000_READ_REG(hw, TIPG);
3808         tipg &= ~E1000_TIPG_IPGT_MASK;
3809         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3810         E1000_WRITE_REG(hw, TIPG, tipg);
3811
3812         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3813
3814         if (ret_val)
3815                 return ret_val;
3816
3817         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3818         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3819
3820         return ret_val;
3821 }
3822
3823 /******************************************************************************
3824  * Detects the current speed and duplex settings of the hardware.
3825  *
3826  * hw - Struct containing variables accessed by shared code
3827  * speed - Speed of the connection
3828  * duplex - Duplex setting of the connection
3829  *****************************************************************************/
3830 static int
3831 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3832                 uint16_t *duplex)
3833 {
3834         uint32_t status;
3835         int32_t ret_val;
3836         uint16_t phy_data;
3837
3838         DEBUGFUNC();
3839
3840         if (hw->mac_type >= e1000_82543) {
3841                 status = E1000_READ_REG(hw, STATUS);
3842                 if (status & E1000_STATUS_SPEED_1000) {
3843                         *speed = SPEED_1000;
3844                         DEBUGOUT("1000 Mbs, ");
3845                 } else if (status & E1000_STATUS_SPEED_100) {
3846                         *speed = SPEED_100;
3847                         DEBUGOUT("100 Mbs, ");
3848                 } else {
3849                         *speed = SPEED_10;
3850                         DEBUGOUT("10 Mbs, ");
3851                 }
3852
3853                 if (status & E1000_STATUS_FD) {
3854                         *duplex = FULL_DUPLEX;
3855                         DEBUGOUT("Full Duplex\r\n");
3856                 } else {
3857                         *duplex = HALF_DUPLEX;
3858                         DEBUGOUT(" Half Duplex\r\n");
3859                 }
3860         } else {
3861                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3862                 *speed = SPEED_1000;
3863                 *duplex = FULL_DUPLEX;
3864         }
3865
3866         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3867          * even if it is operating at half duplex.  Here we set the duplex
3868          * settings to match the duplex in the link partner's capabilities.
3869          */
3870         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3871                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3872                 if (ret_val)
3873                         return ret_val;
3874
3875                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3876                         *duplex = HALF_DUPLEX;
3877                 else {
3878                         ret_val = e1000_read_phy_reg(hw,
3879                                         PHY_LP_ABILITY, &phy_data);
3880                         if (ret_val)
3881                                 return ret_val;
3882                         if ((*speed == SPEED_100 &&
3883                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3884                                 || (*speed == SPEED_10
3885                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3886                                 *duplex = HALF_DUPLEX;
3887                 }
3888         }
3889
3890         if ((hw->mac_type == e1000_80003es2lan) &&
3891                 (hw->media_type == e1000_media_type_copper)) {
3892                 if (*speed == SPEED_1000)
3893                         ret_val = e1000_configure_kmrn_for_1000(hw);
3894                 else
3895                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3896                 if (ret_val)
3897                         return ret_val;
3898         }
3899         return E1000_SUCCESS;
3900 }
3901
3902 /******************************************************************************
3903 * Blocks until autoneg completes or times out (~4.5 seconds)
3904 *
3905 * hw - Struct containing variables accessed by shared code
3906 ******************************************************************************/
3907 static int
3908 e1000_wait_autoneg(struct e1000_hw *hw)
3909 {
3910         uint16_t i;
3911         uint16_t phy_data;
3912
3913         DEBUGFUNC();
3914         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3915
3916         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3917         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3918                 /* Read the MII Status Register and wait for Auto-Neg
3919                  * Complete bit to be set.
3920                  */
3921                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3922                         DEBUGOUT("PHY Read Error\n");
3923                         return -E1000_ERR_PHY;
3924                 }
3925                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3926                         DEBUGOUT("PHY Read Error\n");
3927                         return -E1000_ERR_PHY;
3928                 }
3929                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3930                         DEBUGOUT("Auto-Neg complete.\n");
3931                         return 0;
3932                 }
3933                 mdelay(100);
3934         }
3935         DEBUGOUT("Auto-Neg timedout.\n");
3936         return -E1000_ERR_TIMEOUT;
3937 }
3938
3939 /******************************************************************************
3940 * Raises the Management Data Clock
3941 *
3942 * hw - Struct containing variables accessed by shared code
3943 * ctrl - Device control register's current value
3944 ******************************************************************************/
3945 static void
3946 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3947 {
3948         /* Raise the clock input to the Management Data Clock (by setting the MDC
3949          * bit), and then delay 2 microseconds.
3950          */
3951         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3952         E1000_WRITE_FLUSH(hw);
3953         udelay(2);
3954 }
3955
3956 /******************************************************************************
3957 * Lowers the Management Data Clock
3958 *
3959 * hw - Struct containing variables accessed by shared code
3960 * ctrl - Device control register's current value
3961 ******************************************************************************/
3962 static void
3963 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3964 {
3965         /* Lower the clock input to the Management Data Clock (by clearing the MDC
3966          * bit), and then delay 2 microseconds.
3967          */
3968         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3969         E1000_WRITE_FLUSH(hw);
3970         udelay(2);
3971 }
3972
3973 /******************************************************************************
3974 * Shifts data bits out to the PHY
3975 *
3976 * hw - Struct containing variables accessed by shared code
3977 * data - Data to send out to the PHY
3978 * count - Number of bits to shift out
3979 *
3980 * Bits are shifted out in MSB to LSB order.
3981 ******************************************************************************/
3982 static void
3983 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3984 {
3985         uint32_t ctrl;
3986         uint32_t mask;
3987
3988         /* We need to shift "count" number of bits out to the PHY. So, the value
3989          * in the "data" parameter will be shifted out to the PHY one bit at a
3990          * time. In order to do this, "data" must be broken down into bits.
3991          */
3992         mask = 0x01;
3993         mask <<= (count - 1);
3994
3995         ctrl = E1000_READ_REG(hw, CTRL);
3996
3997         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3998         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3999
4000         while (mask) {
4001                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4002                  * then raising and lowering the Management Data Clock. A "0" is
4003                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4004                  * raising and lowering the clock.
4005                  */
4006                 if (data & mask)
4007                         ctrl |= E1000_CTRL_MDIO;
4008                 else
4009                         ctrl &= ~E1000_CTRL_MDIO;
4010
4011                 E1000_WRITE_REG(hw, CTRL, ctrl);
4012                 E1000_WRITE_FLUSH(hw);
4013
4014                 udelay(2);
4015
4016                 e1000_raise_mdi_clk(hw, &ctrl);
4017                 e1000_lower_mdi_clk(hw, &ctrl);
4018
4019                 mask = mask >> 1;
4020         }
4021 }
4022
4023 /******************************************************************************
4024 * Shifts data bits in from the PHY
4025 *
4026 * hw - Struct containing variables accessed by shared code
4027 *
4028 * Bits are shifted in in MSB to LSB order.
4029 ******************************************************************************/
4030 static uint16_t
4031 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4032 {
4033         uint32_t ctrl;
4034         uint16_t data = 0;
4035         uint8_t i;
4036
4037         /* In order to read a register from the PHY, we need to shift in a total
4038          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4039          * to avoid contention on the MDIO pin when a read operation is performed.
4040          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4041          * by raising the input to the Management Data Clock (setting the MDC bit),
4042          * and then reading the value of the MDIO bit.
4043          */
4044         ctrl = E1000_READ_REG(hw, CTRL);
4045
4046         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4047         ctrl &= ~E1000_CTRL_MDIO_DIR;
4048         ctrl &= ~E1000_CTRL_MDIO;
4049
4050         E1000_WRITE_REG(hw, CTRL, ctrl);
4051         E1000_WRITE_FLUSH(hw);
4052
4053         /* Raise and Lower the clock before reading in the data. This accounts for
4054          * the turnaround bits. The first clock occurred when we clocked out the
4055          * last bit of the Register Address.
4056          */
4057         e1000_raise_mdi_clk(hw, &ctrl);
4058         e1000_lower_mdi_clk(hw, &ctrl);
4059
4060         for (data = 0, i = 0; i < 16; i++) {
4061                 data = data << 1;
4062                 e1000_raise_mdi_clk(hw, &ctrl);
4063                 ctrl = E1000_READ_REG(hw, CTRL);
4064                 /* Check to see if we shifted in a "1". */
4065                 if (ctrl & E1000_CTRL_MDIO)
4066                         data |= 1;
4067                 e1000_lower_mdi_clk(hw, &ctrl);
4068         }
4069
4070         e1000_raise_mdi_clk(hw, &ctrl);
4071         e1000_lower_mdi_clk(hw, &ctrl);
4072
4073         return data;
4074 }
4075
4076 /*****************************************************************************
4077 * Reads the value from a PHY register
4078 *
4079 * hw - Struct containing variables accessed by shared code
4080 * reg_addr - address of the PHY register to read
4081 ******************************************************************************/
4082 static int
4083 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4084 {
4085         uint32_t i;
4086         uint32_t mdic = 0;
4087         const uint32_t phy_addr = 1;
4088
4089         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4090                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4091                 return -E1000_ERR_PARAM;
4092         }
4093
4094         if (hw->mac_type > e1000_82543) {
4095                 /* Set up Op-code, Phy Address, and register address in the MDI
4096                  * Control register.  The MAC will take care of interfacing with the
4097                  * PHY to retrieve the desired data.
4098                  */
4099                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4100                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4101                         (E1000_MDIC_OP_READ));
4102
4103                 E1000_WRITE_REG(hw, MDIC, mdic);
4104
4105                 /* Poll the ready bit to see if the MDI read completed */
4106                 for (i = 0; i < 64; i++) {
4107                         udelay(10);
4108                         mdic = E1000_READ_REG(hw, MDIC);
4109                         if (mdic & E1000_MDIC_READY)
4110                                 break;
4111                 }
4112                 if (!(mdic & E1000_MDIC_READY)) {
4113                         DEBUGOUT("MDI Read did not complete\n");
4114                         return -E1000_ERR_PHY;
4115                 }
4116                 if (mdic & E1000_MDIC_ERROR) {
4117                         DEBUGOUT("MDI Error\n");
4118                         return -E1000_ERR_PHY;
4119                 }
4120                 *phy_data = (uint16_t) mdic;
4121         } else {
4122                 /* We must first send a preamble through the MDIO pin to signal the
4123                  * beginning of an MII instruction.  This is done by sending 32
4124                  * consecutive "1" bits.
4125                  */
4126                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4127
4128                 /* Now combine the next few fields that are required for a read
4129                  * operation.  We use this method instead of calling the
4130                  * e1000_shift_out_mdi_bits routine five different times. The format of
4131                  * a MII read instruction consists of a shift out of 14 bits and is
4132                  * defined as follows:
4133                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4134                  * followed by a shift in of 18 bits.  This first two bits shifted in
4135                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4136                  * READ operation is performed.  These two bits are thrown away
4137                  * followed by a shift in of 16 bits which contains the desired data.
4138                  */
4139                 mdic = ((reg_addr) | (phy_addr << 5) |
4140                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4141
4142                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4143
4144                 /* Now that we've shifted out the read command to the MII, we need to
4145                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4146                  * register address.
4147                  */
4148                 *phy_data = e1000_shift_in_mdi_bits(hw);
4149         }
4150         return 0;
4151 }
4152
4153 /******************************************************************************
4154 * Writes a value to a PHY register
4155 *
4156 * hw - Struct containing variables accessed by shared code
4157 * reg_addr - address of the PHY register to write
4158 * data - data to write to the PHY
4159 ******************************************************************************/
4160 static int
4161 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4162 {
4163         uint32_t i;
4164         uint32_t mdic = 0;
4165         const uint32_t phy_addr = 1;
4166
4167         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4168                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4169                 return -E1000_ERR_PARAM;
4170         }
4171
4172         if (hw->mac_type > e1000_82543) {
4173                 /* Set up Op-code, Phy Address, register address, and data intended
4174                  * for the PHY register in the MDI Control register.  The MAC will take
4175                  * care of interfacing with the PHY to send the desired data.
4176                  */
4177                 mdic = (((uint32_t) phy_data) |
4178                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4179                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4180                         (E1000_MDIC_OP_WRITE));
4181
4182                 E1000_WRITE_REG(hw, MDIC, mdic);
4183
4184                 /* Poll the ready bit to see if the MDI read completed */
4185                 for (i = 0; i < 64; i++) {
4186                         udelay(10);
4187                         mdic = E1000_READ_REG(hw, MDIC);
4188                         if (mdic & E1000_MDIC_READY)
4189                                 break;
4190                 }
4191                 if (!(mdic & E1000_MDIC_READY)) {
4192                         DEBUGOUT("MDI Write did not complete\n");
4193                         return -E1000_ERR_PHY;
4194                 }
4195         } else {
4196                 /* We'll need to use the SW defined pins to shift the write command
4197                  * out to the PHY. We first send a preamble to the PHY to signal the
4198                  * beginning of the MII instruction.  This is done by sending 32
4199                  * consecutive "1" bits.
4200                  */
4201                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4202
4203                 /* Now combine the remaining required fields that will indicate a
4204                  * write operation. We use this method instead of calling the
4205                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4206                  * format of a MII write instruction is as follows:
4207                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4208                  */
4209                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4210                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4211                 mdic <<= 16;
4212                 mdic |= (uint32_t) phy_data;
4213
4214                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4215         }
4216         return 0;
4217 }
4218
4219 /******************************************************************************
4220  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4221  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4222  * the caller to figure out how to deal with it.
4223  *
4224  * hw - Struct containing variables accessed by shared code
4225  *
4226  * returns: - E1000_BLK_PHY_RESET
4227  *            E1000_SUCCESS
4228  *
4229  *****************************************************************************/
4230 int32_t
4231 e1000_check_phy_reset_block(struct e1000_hw *hw)
4232 {
4233         uint32_t manc = 0;
4234         uint32_t fwsm = 0;
4235
4236         if (hw->mac_type == e1000_ich8lan) {
4237                 fwsm = E1000_READ_REG(hw, FWSM);
4238                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4239                                                 : E1000_BLK_PHY_RESET;
4240         }
4241
4242         if (hw->mac_type > e1000_82547_rev_2)
4243                 manc = E1000_READ_REG(hw, MANC);
4244         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4245                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4246 }
4247
4248 /***************************************************************************
4249  * Checks if the PHY configuration is done
4250  *
4251  * hw: Struct containing variables accessed by shared code
4252  *
4253  * returns: - E1000_ERR_RESET if fail to reset MAC
4254  *            E1000_SUCCESS at any other case.
4255  *
4256  ***************************************************************************/
4257 static int32_t
4258 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4259 {
4260         int32_t timeout = PHY_CFG_TIMEOUT;
4261         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4262
4263         DEBUGFUNC();
4264
4265         switch (hw->mac_type) {
4266         default:
4267                 mdelay(10);
4268                 break;
4269         case e1000_80003es2lan:
4270                 /* Separate *_CFG_DONE_* bit for each port */
4271                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4272                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4273         /* Fall Through */
4274         case e1000_82571:
4275         case e1000_82572:
4276                 while (timeout) {
4277                         if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4278                                 break;
4279                         else
4280                                 mdelay(1);
4281                         timeout--;
4282                 }
4283                 if (!timeout) {
4284                         DEBUGOUT("MNG configuration cycle has not "
4285                                         "completed.\n");
4286                         return -E1000_ERR_RESET;
4287                 }
4288                 break;
4289         }
4290
4291         return E1000_SUCCESS;
4292 }
4293
4294 /******************************************************************************
4295 * Returns the PHY to the power-on reset state
4296 *
4297 * hw - Struct containing variables accessed by shared code
4298 ******************************************************************************/
4299 int32_t
4300 e1000_phy_hw_reset(struct e1000_hw *hw)
4301 {
4302         uint32_t ctrl, ctrl_ext;
4303         uint32_t led_ctrl;
4304         int32_t ret_val;
4305         uint16_t swfw;
4306
4307         DEBUGFUNC();
4308
4309         /* In the case of the phy reset being blocked, it's not an error, we
4310          * simply return success without performing the reset. */
4311         ret_val = e1000_check_phy_reset_block(hw);
4312         if (ret_val)
4313                 return E1000_SUCCESS;
4314
4315         DEBUGOUT("Resetting Phy...\n");
4316
4317         if (hw->mac_type > e1000_82543) {
4318                 if ((hw->mac_type == e1000_80003es2lan) &&
4319                         (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
4320                         swfw = E1000_SWFW_PHY1_SM;
4321                 } else {
4322                         swfw = E1000_SWFW_PHY0_SM;
4323                 }
4324                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4325                         DEBUGOUT("Unable to acquire swfw sync\n");
4326                         return -E1000_ERR_SWFW_SYNC;
4327                 }
4328                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4329                  * bit. Then, take it out of reset.
4330                  */
4331                 ctrl = E1000_READ_REG(hw, CTRL);
4332                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4333                 E1000_WRITE_FLUSH(hw);
4334
4335                 if (hw->mac_type < e1000_82571)
4336                         udelay(10);
4337                 else
4338                         udelay(100);
4339
4340                 E1000_WRITE_REG(hw, CTRL, ctrl);
4341                 E1000_WRITE_FLUSH(hw);
4342
4343                 if (hw->mac_type >= e1000_82571)
4344                         mdelay(10);
4345
4346         } else {
4347                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4348                  * bit to put the PHY into reset. Then, take it out of reset.
4349                  */
4350                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4351                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4352                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4353                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4354                 E1000_WRITE_FLUSH(hw);
4355                 mdelay(10);
4356                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4357                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4358                 E1000_WRITE_FLUSH(hw);
4359         }
4360         udelay(150);
4361
4362         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4363                 /* Configure activity LED after PHY reset */
4364                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4365                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4366                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4367                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4368         }
4369
4370         /* Wait for FW to finish PHY configuration. */
4371         ret_val = e1000_get_phy_cfg_done(hw);
4372         if (ret_val != E1000_SUCCESS)
4373                 return ret_val;
4374
4375         return ret_val;
4376 }
4377
4378 /******************************************************************************
4379  * IGP phy init script - initializes the GbE PHY
4380  *
4381  * hw - Struct containing variables accessed by shared code
4382  *****************************************************************************/
4383 static void
4384 e1000_phy_init_script(struct e1000_hw *hw)
4385 {
4386         uint32_t ret_val;
4387         uint16_t phy_saved_data;
4388         DEBUGFUNC();
4389
4390         if (hw->phy_init_script) {
4391                 mdelay(20);
4392
4393                 /* Save off the current value of register 0x2F5B to be
4394                  * restored at the end of this routine. */
4395                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4396
4397                 /* Disabled the PHY transmitter */
4398                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4399
4400                 mdelay(20);
4401
4402                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4403
4404                 mdelay(5);
4405
4406                 switch (hw->mac_type) {
4407                 case e1000_82541:
4408                 case e1000_82547:
4409                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4410
4411                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4412
4413                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4414
4415                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4416
4417                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4418
4419                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4420
4421                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4422
4423                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4424
4425                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4426                         break;
4427
4428                 case e1000_82541_rev_2:
4429                 case e1000_82547_rev_2:
4430                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4431                         break;
4432                 default:
4433                         break;
4434                 }
4435
4436                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4437
4438                 mdelay(20);
4439
4440                 /* Now enable the transmitter */
4441                 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4442
4443                 if (hw->mac_type == e1000_82547) {
4444                         uint16_t fused, fine, coarse;
4445
4446                         /* Move to analog registers page */
4447                         e1000_read_phy_reg(hw,
4448                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4449
4450                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4451                                 e1000_read_phy_reg(hw,
4452                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4453
4454                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4455                                 coarse = fused
4456                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4457
4458                                 if (coarse >
4459                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4460                                         coarse -=
4461                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4462                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4463                                 } else if (coarse
4464                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4465                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4466
4467                                 fused = (fused
4468                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4469                                         (fine
4470                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4471                                         (coarse
4472                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4473
4474                                 e1000_write_phy_reg(hw,
4475                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4476                                 e1000_write_phy_reg(hw,
4477                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4478                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4479                         }
4480                 }
4481         }
4482 }
4483
4484 /******************************************************************************
4485 * Resets the PHY
4486 *
4487 * hw - Struct containing variables accessed by shared code
4488 *
4489 * Sets bit 15 of the MII Control register
4490 ******************************************************************************/
4491 int32_t
4492 e1000_phy_reset(struct e1000_hw *hw)
4493 {
4494         int32_t ret_val;
4495         uint16_t phy_data;
4496
4497         DEBUGFUNC();
4498
4499         /* In the case of the phy reset being blocked, it's not an error, we
4500          * simply return success without performing the reset. */
4501         ret_val = e1000_check_phy_reset_block(hw);
4502         if (ret_val)
4503                 return E1000_SUCCESS;
4504
4505         switch (hw->phy_type) {
4506         case e1000_phy_igp:
4507         case e1000_phy_igp_2:
4508         case e1000_phy_igp_3:
4509         case e1000_phy_ife:
4510                 ret_val = e1000_phy_hw_reset(hw);
4511                 if (ret_val)
4512                         return ret_val;
4513                 break;
4514         default:
4515                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4516                 if (ret_val)
4517                         return ret_val;
4518
4519                 phy_data |= MII_CR_RESET;
4520                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4521                 if (ret_val)
4522                         return ret_val;
4523
4524                 udelay(1);
4525                 break;
4526         }
4527
4528         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4529                 e1000_phy_init_script(hw);
4530
4531         return E1000_SUCCESS;
4532 }
4533
4534 static int e1000_set_phy_type (struct e1000_hw *hw)
4535 {
4536         DEBUGFUNC ();
4537
4538         if (hw->mac_type == e1000_undefined)
4539                 return -E1000_ERR_PHY_TYPE;
4540
4541         switch (hw->phy_id) {
4542         case M88E1000_E_PHY_ID:
4543         case M88E1000_I_PHY_ID:
4544         case M88E1011_I_PHY_ID:
4545         case M88E1111_I_PHY_ID:
4546                 hw->phy_type = e1000_phy_m88;
4547                 break;
4548         case IGP01E1000_I_PHY_ID:
4549                 if (hw->mac_type == e1000_82541 ||
4550                         hw->mac_type == e1000_82541_rev_2 ||
4551                         hw->mac_type == e1000_82547 ||
4552                         hw->mac_type == e1000_82547_rev_2) {
4553                         hw->phy_type = e1000_phy_igp;
4554                         hw->phy_type = e1000_phy_igp;
4555                         break;
4556                 }
4557         case IGP03E1000_E_PHY_ID:
4558                 hw->phy_type = e1000_phy_igp_3;
4559                 break;
4560         case IFE_E_PHY_ID:
4561         case IFE_PLUS_E_PHY_ID:
4562         case IFE_C_E_PHY_ID:
4563                 hw->phy_type = e1000_phy_ife;
4564                 break;
4565         case GG82563_E_PHY_ID:
4566                 if (hw->mac_type == e1000_80003es2lan) {
4567                         hw->phy_type = e1000_phy_gg82563;
4568                         break;
4569                 }
4570         case BME1000_E_PHY_ID:
4571                 hw->phy_type = e1000_phy_bm;
4572                 break;
4573                 /* Fall Through */
4574         default:
4575                 /* Should never have loaded on this device */
4576                 hw->phy_type = e1000_phy_undefined;
4577                 return -E1000_ERR_PHY_TYPE;
4578         }
4579
4580         return E1000_SUCCESS;
4581 }
4582
4583 /******************************************************************************
4584 * Probes the expected PHY address for known PHY IDs
4585 *
4586 * hw - Struct containing variables accessed by shared code
4587 ******************************************************************************/
4588 static int32_t
4589 e1000_detect_gig_phy(struct e1000_hw *hw)
4590 {
4591         int32_t phy_init_status, ret_val;
4592         uint16_t phy_id_high, phy_id_low;
4593         boolean_t match = FALSE;
4594
4595         DEBUGFUNC();
4596
4597         /* The 82571 firmware may still be configuring the PHY.  In this
4598          * case, we cannot access the PHY until the configuration is done.  So
4599          * we explicitly set the PHY values. */
4600         if (hw->mac_type == e1000_82571 ||
4601                 hw->mac_type == e1000_82572) {
4602                 hw->phy_id = IGP01E1000_I_PHY_ID;
4603                 hw->phy_type = e1000_phy_igp_2;
4604                 return E1000_SUCCESS;
4605         }
4606
4607         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4608          * work- around that forces PHY page 0 to be set or the reads fail.
4609          * The rest of the code in this routine uses e1000_read_phy_reg to
4610          * read the PHY ID.  So for ESB-2 we need to have this set so our
4611          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4612          * the routines below will figure this out as well. */
4613         if (hw->mac_type == e1000_80003es2lan)
4614                 hw->phy_type = e1000_phy_gg82563;
4615
4616         /* Read the PHY ID Registers to identify which PHY is onboard. */
4617         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4618         if (ret_val)
4619                 return ret_val;
4620
4621         hw->phy_id = (uint32_t) (phy_id_high << 16);
4622         udelay(20);
4623         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4624         if (ret_val)
4625                 return ret_val;
4626
4627         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4628         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4629
4630         switch (hw->mac_type) {
4631         case e1000_82543:
4632                 if (hw->phy_id == M88E1000_E_PHY_ID)
4633                         match = TRUE;
4634                 break;
4635         case e1000_82544:
4636                 if (hw->phy_id == M88E1000_I_PHY_ID)
4637                         match = TRUE;
4638                 break;
4639         case e1000_82540:
4640         case e1000_82545:
4641         case e1000_82545_rev_3:
4642         case e1000_82546:
4643         case e1000_82546_rev_3:
4644                 if (hw->phy_id == M88E1011_I_PHY_ID)
4645                         match = TRUE;
4646                 break;
4647         case e1000_82541:
4648         case e1000_82541_rev_2:
4649         case e1000_82547:
4650         case e1000_82547_rev_2:
4651                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4652                         match = TRUE;
4653
4654                 break;
4655         case e1000_82573:
4656                 if (hw->phy_id == M88E1111_I_PHY_ID)
4657                         match = TRUE;
4658                 break;
4659         case e1000_82574:
4660                 if (hw->phy_id == BME1000_E_PHY_ID)
4661                         match = TRUE;
4662                 break;
4663         case e1000_80003es2lan:
4664                 if (hw->phy_id == GG82563_E_PHY_ID)
4665                         match = TRUE;
4666                 break;
4667         case e1000_ich8lan:
4668                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4669                         match = TRUE;
4670                 if (hw->phy_id == IFE_E_PHY_ID)
4671                         match = TRUE;
4672                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4673                         match = TRUE;
4674                 if (hw->phy_id == IFE_C_E_PHY_ID)
4675                         match = TRUE;
4676                 break;
4677         default:
4678                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4679                 return -E1000_ERR_CONFIG;
4680         }
4681
4682         phy_init_status = e1000_set_phy_type(hw);
4683
4684         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4685                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4686                 return 0;
4687         }
4688         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4689         return -E1000_ERR_PHY;
4690 }
4691
4692 /*****************************************************************************
4693  * Set media type and TBI compatibility.
4694  *
4695  * hw - Struct containing variables accessed by shared code
4696  * **************************************************************************/
4697 void
4698 e1000_set_media_type(struct e1000_hw *hw)
4699 {
4700         uint32_t status;
4701
4702         DEBUGFUNC();
4703
4704         if (hw->mac_type != e1000_82543) {
4705                 /* tbi_compatibility is only valid on 82543 */
4706                 hw->tbi_compatibility_en = FALSE;
4707         }
4708
4709         switch (hw->device_id) {
4710         case E1000_DEV_ID_82545GM_SERDES:
4711         case E1000_DEV_ID_82546GB_SERDES:
4712         case E1000_DEV_ID_82571EB_SERDES:
4713         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4714         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4715         case E1000_DEV_ID_82572EI_SERDES:
4716         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4717                 hw->media_type = e1000_media_type_internal_serdes;
4718                 break;
4719         default:
4720                 switch (hw->mac_type) {
4721                 case e1000_82542_rev2_0:
4722                 case e1000_82542_rev2_1:
4723                         hw->media_type = e1000_media_type_fiber;
4724                         break;
4725                 case e1000_ich8lan:
4726                 case e1000_82573:
4727                 case e1000_82574:
4728                         /* The STATUS_TBIMODE bit is reserved or reused
4729                          * for the this device.
4730                          */
4731                         hw->media_type = e1000_media_type_copper;
4732                         break;
4733                 default:
4734                         status = E1000_READ_REG(hw, STATUS);
4735                         if (status & E1000_STATUS_TBIMODE) {
4736                                 hw->media_type = e1000_media_type_fiber;
4737                                 /* tbi_compatibility not valid on fiber */
4738                                 hw->tbi_compatibility_en = FALSE;
4739                         } else {
4740                                 hw->media_type = e1000_media_type_copper;
4741                         }
4742                         break;
4743                 }
4744         }
4745 }
4746
4747 /**
4748  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4749  *
4750  * e1000_sw_init initializes the Adapter private data structure.
4751  * Fields are initialized based on PCI device information and
4752  * OS network device settings (MTU size).
4753  **/
4754
4755 static int
4756 e1000_sw_init(struct eth_device *nic, int cardnum)
4757 {
4758         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4759         int result;
4760
4761         /* PCI config space info */
4762         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4763         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4764         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4765                              &hw->subsystem_vendor_id);
4766         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4767
4768         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4769         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4770
4771         /* identify the MAC */
4772         result = e1000_set_mac_type(hw);
4773         if (result) {
4774                 E1000_ERR("Unknown MAC Type\n");
4775                 return result;
4776         }
4777
4778         switch (hw->mac_type) {
4779         default:
4780                 break;
4781         case e1000_82541:
4782         case e1000_82547:
4783         case e1000_82541_rev_2:
4784         case e1000_82547_rev_2:
4785                 hw->phy_init_script = 1;
4786                 break;
4787         }
4788
4789         /* lan a vs. lan b settings */
4790         if (hw->mac_type == e1000_82546)
4791                 /*this also works w/ multiple 82546 cards */
4792                 /*but not if they're intermingled /w other e1000s */
4793                 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
4794         else
4795                 hw->lan_loc = e1000_lan_a;
4796
4797         /* flow control settings */
4798         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4799         hw->fc_low_water = E1000_FC_LOW_THRESH;
4800         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4801         hw->fc_send_xon = 1;
4802
4803         /* Media type - copper or fiber */
4804         e1000_set_media_type(hw);
4805
4806         if (hw->mac_type >= e1000_82543) {
4807                 uint32_t status = E1000_READ_REG(hw, STATUS);
4808
4809                 if (status & E1000_STATUS_TBIMODE) {
4810                         DEBUGOUT("fiber interface\n");
4811                         hw->media_type = e1000_media_type_fiber;
4812                 } else {
4813                         DEBUGOUT("copper interface\n");
4814                         hw->media_type = e1000_media_type_copper;
4815                 }
4816         } else {
4817                 hw->media_type = e1000_media_type_fiber;
4818         }
4819
4820         hw->tbi_compatibility_en = TRUE;
4821         hw->wait_autoneg_complete = TRUE;
4822         if (hw->mac_type < e1000_82543)
4823                 hw->report_tx_early = 0;
4824         else
4825                 hw->report_tx_early = 1;
4826
4827         return E1000_SUCCESS;
4828 }
4829
4830 void
4831 fill_rx(struct e1000_hw *hw)
4832 {
4833         struct e1000_rx_desc *rd;
4834
4835         rx_last = rx_tail;
4836         rd = rx_base + rx_tail;
4837         rx_tail = (rx_tail + 1) % 8;
4838         memset(rd, 0, 16);
4839         rd->buffer_addr = cpu_to_le64((u32) & packet);
4840         E1000_WRITE_REG(hw, RDT, rx_tail);
4841 }
4842
4843 /**
4844  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4845  * @adapter: board private structure
4846  *
4847  * Configure the Tx unit of the MAC after a reset.
4848  **/
4849
4850 static void
4851 e1000_configure_tx(struct e1000_hw *hw)
4852 {
4853         unsigned long ptr;
4854         unsigned long tctl;
4855         unsigned long tipg, tarc;
4856         uint32_t ipgr1, ipgr2;
4857
4858         ptr = (u32) tx_pool;
4859         if (ptr & 0xf)
4860                 ptr = (ptr + 0x10) & (~0xf);
4861
4862         tx_base = (typeof(tx_base)) ptr;
4863
4864         E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4865         E1000_WRITE_REG(hw, TDBAH, 0);
4866
4867         E1000_WRITE_REG(hw, TDLEN, 128);
4868
4869         /* Setup the HW Tx Head and Tail descriptor pointers */
4870         E1000_WRITE_REG(hw, TDH, 0);
4871         E1000_WRITE_REG(hw, TDT, 0);
4872         tx_tail = 0;
4873
4874         /* Set the default values for the Tx Inter Packet Gap timer */
4875         if (hw->mac_type <= e1000_82547_rev_2 &&
4876             (hw->media_type == e1000_media_type_fiber ||
4877              hw->media_type == e1000_media_type_internal_serdes))
4878                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4879         else
4880                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4881
4882         /* Set the default values for the Tx Inter Packet Gap timer */
4883         switch (hw->mac_type) {
4884         case e1000_82542_rev2_0:
4885         case e1000_82542_rev2_1:
4886                 tipg = DEFAULT_82542_TIPG_IPGT;
4887                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4888                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4889                 break;
4890         case e1000_80003es2lan:
4891                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4892                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4893                 break;
4894         default:
4895                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4896                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4897                 break;
4898         }
4899         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4900         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4901         E1000_WRITE_REG(hw, TIPG, tipg);
4902         /* Program the Transmit Control Register */
4903         tctl = E1000_READ_REG(hw, TCTL);
4904         tctl &= ~E1000_TCTL_CT;
4905         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4906             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4907
4908         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4909                 tarc = E1000_READ_REG(hw, TARC0);
4910                 /* set the speed mode bit, we'll clear it if we're not at
4911                  * gigabit link later */
4912                 /* git bit can be set to 1*/
4913         } else if (hw->mac_type == e1000_80003es2lan) {
4914                 tarc = E1000_READ_REG(hw, TARC0);
4915                 tarc |= 1;
4916                 E1000_WRITE_REG(hw, TARC0, tarc);
4917                 tarc = E1000_READ_REG(hw, TARC1);
4918                 tarc |= 1;
4919                 E1000_WRITE_REG(hw, TARC1, tarc);
4920         }
4921
4922
4923         e1000_config_collision_dist(hw);
4924         /* Setup Transmit Descriptor Settings for eop descriptor */
4925         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4926
4927         /* Need to set up RS bit */
4928         if (hw->mac_type < e1000_82543)
4929                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4930         else
4931                 hw->txd_cmd |= E1000_TXD_CMD_RS;
4932         E1000_WRITE_REG(hw, TCTL, tctl);
4933 }
4934
4935 /**
4936  * e1000_setup_rctl - configure the receive control register
4937  * @adapter: Board private structure
4938  **/
4939 static void
4940 e1000_setup_rctl(struct e1000_hw *hw)
4941 {
4942         uint32_t rctl;
4943
4944         rctl = E1000_READ_REG(hw, RCTL);
4945
4946         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4947
4948         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4949                 | E1000_RCTL_RDMTS_HALF;        /* |
4950                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4951
4952         if (hw->tbi_compatibility_on == 1)
4953                 rctl |= E1000_RCTL_SBP;
4954         else
4955                 rctl &= ~E1000_RCTL_SBP;
4956
4957         rctl &= ~(E1000_RCTL_SZ_4096);
4958                 rctl |= E1000_RCTL_SZ_2048;
4959                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4960         E1000_WRITE_REG(hw, RCTL, rctl);
4961 }
4962
4963 /**
4964  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4965  * @adapter: board private structure
4966  *
4967  * Configure the Rx unit of the MAC after a reset.
4968  **/
4969 static void
4970 e1000_configure_rx(struct e1000_hw *hw)
4971 {
4972         unsigned long ptr;
4973         unsigned long rctl, ctrl_ext;
4974         rx_tail = 0;
4975         /* make sure receives are disabled while setting up the descriptors */
4976         rctl = E1000_READ_REG(hw, RCTL);
4977         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4978         if (hw->mac_type >= e1000_82540) {
4979                 /* Set the interrupt throttling rate.  Value is calculated
4980                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4981 #define MAX_INTS_PER_SEC        8000
4982 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
4983                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4984         }
4985
4986         if (hw->mac_type >= e1000_82571) {
4987                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4988                 /* Reset delay timers after every interrupt */
4989                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4990                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4991                 E1000_WRITE_FLUSH(hw);
4992         }
4993         /* Setup the Base and Length of the Rx Descriptor Ring */
4994         ptr = (u32) rx_pool;
4995         if (ptr & 0xf)
4996                 ptr = (ptr + 0x10) & (~0xf);
4997         rx_base = (typeof(rx_base)) ptr;
4998         E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
4999         E1000_WRITE_REG(hw, RDBAH, 0);
5000
5001         E1000_WRITE_REG(hw, RDLEN, 128);
5002
5003         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5004         E1000_WRITE_REG(hw, RDH, 0);
5005         E1000_WRITE_REG(hw, RDT, 0);
5006         /* Enable Receives */
5007
5008         E1000_WRITE_REG(hw, RCTL, rctl);
5009         fill_rx(hw);
5010 }
5011
5012 /**************************************************************************
5013 POLL - Wait for a frame
5014 ***************************************************************************/
5015 static int
5016 e1000_poll(struct eth_device *nic)
5017 {
5018         struct e1000_hw *hw = nic->priv;
5019         struct e1000_rx_desc *rd;
5020         /* return true if there's an ethernet packet ready to read */
5021         rd = rx_base + rx_last;
5022         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5023                 return 0;
5024         /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5025         NetReceive((uchar *)packet, le32_to_cpu(rd->length));
5026         fill_rx(hw);
5027         return 1;
5028 }
5029
5030 /**************************************************************************
5031 TRANSMIT - Transmit a frame
5032 ***************************************************************************/
5033 static int
5034 e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
5035 {
5036         void * nv_packet = (void *)packet;
5037         struct e1000_hw *hw = nic->priv;
5038         struct e1000_tx_desc *txp;
5039         int i = 0;
5040
5041         txp = tx_base + tx_tail;
5042         tx_tail = (tx_tail + 1) % 8;
5043
5044         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5045         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5046         txp->upper.data = 0;
5047         E1000_WRITE_REG(hw, TDT, tx_tail);
5048
5049         E1000_WRITE_FLUSH(hw);
5050         while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5051                 if (i++ > TOUT_LOOP) {
5052                         DEBUGOUT("e1000: tx timeout\n");
5053                         return 0;
5054                 }
5055                 udelay(10);     /* give the nic a chance to write to the register */
5056         }
5057         return 1;
5058 }
5059
5060 /*reset function*/
5061 static inline int
5062 e1000_reset(struct eth_device *nic)
5063 {
5064         struct e1000_hw *hw = nic->priv;
5065
5066         e1000_reset_hw(hw);
5067         if (hw->mac_type >= e1000_82544) {
5068                 E1000_WRITE_REG(hw, WUC, 0);
5069         }
5070         return e1000_init_hw(nic);
5071 }
5072
5073 /**************************************************************************
5074 DISABLE - Turn off ethernet interface
5075 ***************************************************************************/
5076 static void
5077 e1000_disable(struct eth_device *nic)
5078 {
5079         struct e1000_hw *hw = nic->priv;
5080
5081         /* Turn off the ethernet interface */
5082         E1000_WRITE_REG(hw, RCTL, 0);
5083         E1000_WRITE_REG(hw, TCTL, 0);
5084
5085         /* Clear the transmit ring */
5086         E1000_WRITE_REG(hw, TDH, 0);
5087         E1000_WRITE_REG(hw, TDT, 0);
5088
5089         /* Clear the receive ring */
5090         E1000_WRITE_REG(hw, RDH, 0);
5091         E1000_WRITE_REG(hw, RDT, 0);
5092
5093         /* put the card in its initial state */
5094 #if 0
5095         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5096 #endif
5097         mdelay(10);
5098
5099 }
5100
5101 /**************************************************************************
5102 INIT - set up ethernet interface(s)
5103 ***************************************************************************/
5104 static int
5105 e1000_init(struct eth_device *nic, bd_t * bis)
5106 {
5107         struct e1000_hw *hw = nic->priv;
5108         int ret_val = 0;
5109
5110         ret_val = e1000_reset(nic);
5111         if (ret_val < 0) {
5112                 if ((ret_val == -E1000_ERR_NOLINK) ||
5113                     (ret_val == -E1000_ERR_TIMEOUT)) {
5114                         E1000_ERR("Valid Link not detected\n");
5115                 } else {
5116                         E1000_ERR("Hardware Initialization Failed\n");
5117                 }
5118                 return 0;
5119         }
5120         e1000_configure_tx(hw);
5121         e1000_setup_rctl(hw);
5122         e1000_configure_rx(hw);
5123         return 1;
5124 }
5125
5126 /******************************************************************************
5127  * Gets the current PCI bus type of hardware
5128  *
5129  * hw - Struct containing variables accessed by shared code
5130  *****************************************************************************/
5131 void e1000_get_bus_type(struct e1000_hw *hw)
5132 {
5133         uint32_t status;
5134
5135         switch (hw->mac_type) {
5136         case e1000_82542_rev2_0:
5137         case e1000_82542_rev2_1:
5138                 hw->bus_type = e1000_bus_type_pci;
5139                 break;
5140         case e1000_82571:
5141         case e1000_82572:
5142         case e1000_82573:
5143         case e1000_82574:
5144         case e1000_80003es2lan:
5145                 hw->bus_type = e1000_bus_type_pci_express;
5146                 break;
5147         case e1000_ich8lan:
5148                 hw->bus_type = e1000_bus_type_pci_express;
5149                 break;
5150         default:
5151                 status = E1000_READ_REG(hw, STATUS);
5152                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5153                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5154                 break;
5155         }
5156 }
5157
5158 /**************************************************************************
5159 PROBE - Look for an adapter, this routine's visible to the outside
5160 You should omit the last argument struct pci_device * for a non-PCI NIC
5161 ***************************************************************************/
5162 int
5163 e1000_initialize(bd_t * bis)
5164 {
5165         pci_dev_t devno;
5166         int card_number = 0;
5167         struct eth_device *nic = NULL;
5168         struct e1000_hw *hw = NULL;
5169         u32 iobase;
5170         int idx = 0;
5171         u32 PciCommandWord;
5172
5173         DEBUGFUNC();
5174
5175         while (1) {             /* Find PCI device(s) */
5176                 if ((devno = pci_find_devices(supported, idx++)) < 0) {
5177                         break;
5178                 }
5179
5180                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
5181                 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
5182                 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
5183
5184                 pci_write_config_dword(devno, PCI_COMMAND,
5185                                        PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
5186                 /* Check if I/O accesses and Bus Mastering are enabled. */
5187                 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
5188                 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
5189                         printf("Error: Can not enable MEM access.\n");
5190                         continue;
5191                 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
5192                         printf("Error: Can not enable Bus Mastering.\n");
5193                         continue;
5194                 }
5195
5196                 nic = (struct eth_device *) malloc(sizeof (*nic));
5197                 if (!nic) {
5198                         printf("Error: e1000 - Can not alloc memory\n");
5199                         return 0;
5200                 }
5201
5202                 hw = (struct e1000_hw *) malloc(sizeof (*hw));
5203                 if (!hw) {
5204                         free(nic);
5205                         printf("Error: e1000 - Can not alloc memory\n");
5206                         return 0;
5207                 }
5208
5209                 memset(nic, 0, sizeof(*nic));
5210                 memset(hw, 0, sizeof(*hw));
5211
5212                 hw->pdev = devno;
5213                 nic->priv = hw;
5214
5215                 sprintf(nic->name, "e1000#%d", card_number);
5216
5217                 /* Are these variables needed? */
5218                 hw->fc = e1000_fc_default;
5219                 hw->original_fc = e1000_fc_default;
5220                 hw->autoneg_failed = 0;
5221                 hw->autoneg = 1;
5222                 hw->get_link_status = TRUE;
5223                 hw->hw_addr =
5224                         pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
5225                 hw->mac_type = e1000_undefined;
5226
5227                 /* MAC and Phy settings */
5228                 if (e1000_sw_init(nic, card_number) < 0) {
5229                         free(hw);
5230                         free(nic);
5231                         return 0;
5232                 }
5233                 if (e1000_check_phy_reset_block(hw))
5234                         printf("phy reset block error \n");
5235                 e1000_reset_hw(hw);
5236 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
5237                 if (e1000_init_eeprom_params(hw)) {
5238                         printf("The EEPROM Checksum Is Not Valid\n");
5239                         free(hw);
5240                         free(nic);
5241                         return 0;
5242                 }
5243                 if (e1000_validate_eeprom_checksum(nic) < 0) {
5244                         printf("The EEPROM Checksum Is Not Valid\n");
5245                         free(hw);
5246                         free(nic);
5247                         return 0;
5248                 }
5249 #endif
5250                 e1000_read_mac_addr(nic);
5251
5252                 /* get the bus type information */
5253                 e1000_get_bus_type(hw);
5254
5255                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
5256                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5257                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5258
5259                 nic->init = e1000_init;
5260                 nic->recv = e1000_poll;
5261                 nic->send = e1000_transmit;
5262                 nic->halt = e1000_disable;
5263
5264                 eth_register(nic);
5265
5266                 card_number++;
5267         }
5268         return card_number;
5269 }