drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms of the GNU General Public License as published by the Free
  14   Software Foundation; either version 2 of the License, or (at your option)
  15   any later version.
  16
  17   This program is distributed in the hope that it will be useful, but WITHOUT
  18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20   more details.
  21
  22   You should have received a copy of the GNU General Public License along with
  23   this program; if not, write to the Free Software Foundation, Inc., 59
  24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25
  26   The full GNU General Public License is included in this distribution in the
  27   file called LICENSE.
  28
  29   Contact Information:
  30   Linux NICS <linux.nics@intel.com>
  31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32
  33 *******************************************************************************/
  34 /*
  35  *  Copyright (C) Archway Digital Solutions.
  36  *
  37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  38  *  2/9/2002
  39  *
  40  *  Copyright (C) Linux Networx.
  41  *  Massive upgrade to work with the new intel gigabit NICs.
  42  *  <ebiederman at lnxi dot com>
  43  *
  44  *  Copyright 2011 Freescale Semiconductor, Inc.
  45  */
  46
  47 #include "e1000.h"
  48
  49 #define TOUT_LOOP   100000
  50
  51 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  52 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  53
  54 #define E1000_DEFAULT_PCI_PBA   0x00000030
  55 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  56
  57 /* NIC specific static variables go here */
  58
  59 static char tx_pool[128 + 16];
  60 static char rx_pool[128 + 16];
  61 static char packet[2096];
  62
  63 static struct e1000_tx_desc *tx_base;
  64 static struct e1000_rx_desc *rx_base;
  65
  66 static int tx_tail;
  67 static int rx_tail, rx_last;
  68
  69 static struct pci_device_id e1000_supported[] = {
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  72         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  87         /* E1000 PCIe card */
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
 103         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
 104         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
 105         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
 106         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
 107         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
 108         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
 109         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
 110         {}
 111 };
 112
 113 /* Function forward declarations */
 114 static int e1000_setup_link(struct eth_device *nic);
 115 static int e1000_setup_fiber_link(struct eth_device *nic);
 116 static int e1000_setup_copper_link(struct eth_device *nic);
 117 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 118 static void e1000_config_collision_dist(struct e1000_hw *hw);
 119 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 120 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 121 static int e1000_check_for_link(struct eth_device *nic);
 122 static int e1000_wait_autoneg(struct e1000_hw *hw);
 123 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 124                                        uint16_t * duplex);
 125 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 126                               uint16_t * phy_data);
 127 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 128                                uint16_t phy_data);
 129 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 130 static int e1000_phy_reset(struct e1000_hw *hw);
 131 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 132 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 133 static void e1000_set_media_type(struct e1000_hw *hw);
 134
 135 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 136 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 137
 138 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 139                 uint16_t words,
 140                 uint16_t *data);
 141 /******************************************************************************
 142  * Raises the EEPROM's clock input.
 143  *
 144  * hw - Struct containing variables accessed by shared code
 145  * eecd - EECD's current value
 146  *****************************************************************************/
 147 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 148 {
 149         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 150          * wait 50 microseconds.
 151          */
 152         *eecd = *eecd | E1000_EECD_SK;
 153         E1000_WRITE_REG(hw, EECD, *eecd);
 154         E1000_WRITE_FLUSH(hw);
 155         udelay(50);
 156 }
 157
 158 /******************************************************************************
 159  * Lowers the EEPROM's clock input.
 160  *
 161  * hw - Struct containing variables accessed by shared code
 162  * eecd - EECD's current value
 163  *****************************************************************************/
 164 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 165 {
 166         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 167          * wait 50 microseconds.
 168          */
 169         *eecd = *eecd & ~E1000_EECD_SK;
 170         E1000_WRITE_REG(hw, EECD, *eecd);
 171         E1000_WRITE_FLUSH(hw);
 172         udelay(50);
 173 }
 174
 175 /******************************************************************************
 176  * Shift data bits out to the EEPROM.
 177  *
 178  * hw - Struct containing variables accessed by shared code
 179  * data - data to send to the EEPROM
 180  * count - number of bits to shift out
 181  *****************************************************************************/
 182 static void
 183 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 184 {
 185         uint32_t eecd;
 186         uint32_t mask;
 187
 188         /* We need to shift "count" bits out to the EEPROM. So, value in the
 189          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 190          * In order to do this, "data" must be broken down into bits.
 191          */
 192         mask = 0x01 << (count - 1);
 193         eecd = E1000_READ_REG(hw, EECD);
 194         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 195         do {
 196                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 197                  * and then raising and then lowering the clock (the SK bit controls
 198                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 199                  * by setting "DI" to "0" and then raising and then lowering the clock.
 200                  */
 201                 eecd &= ~E1000_EECD_DI;
 202
 203                 if (data & mask)
 204                         eecd |= E1000_EECD_DI;
 205
 206                 E1000_WRITE_REG(hw, EECD, eecd);
 207                 E1000_WRITE_FLUSH(hw);
 208
 209                 udelay(50);
 210
 211                 e1000_raise_ee_clk(hw, &eecd);
 212                 e1000_lower_ee_clk(hw, &eecd);
 213
 214                 mask = mask >> 1;
 215
 216         } while (mask);
 217
 218         /* We leave the "DI" bit set to "0" when we leave this routine. */
 219         eecd &= ~E1000_EECD_DI;
 220         E1000_WRITE_REG(hw, EECD, eecd);
 221 }
 222
 223 /******************************************************************************
 224  * Shift data bits in from the EEPROM
 225  *
 226  * hw - Struct containing variables accessed by shared code
 227  *****************************************************************************/
 228 static uint16_t
 229 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 230 {
 231         uint32_t eecd;
 232         uint32_t i;
 233         uint16_t data;
 234
 235         /* In order to read a register from the EEPROM, we need to shift 'count'
 236          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 237          * input to the EEPROM (setting the SK bit), and then reading the
 238          * value of the "DO" bit.  During this "shifting in" process the
 239          * "DI" bit should always be clear.
 240          */
 241
 242         eecd = E1000_READ_REG(hw, EECD);
 243
 244         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 245         data = 0;
 246
 247         for (i = 0; i < count; i++) {
 248                 data = data << 1;
 249                 e1000_raise_ee_clk(hw, &eecd);
 250
 251                 eecd = E1000_READ_REG(hw, EECD);
 252
 253                 eecd &= ~(E1000_EECD_DI);
 254                 if (eecd & E1000_EECD_DO)
 255                         data |= 1;
 256
 257                 e1000_lower_ee_clk(hw, &eecd);
 258         }
 259
 260         return data;
 261 }
 262
 263 /******************************************************************************
 264  * Returns EEPROM to a "standby" state
 265  *
 266  * hw - Struct containing variables accessed by shared code
 267  *****************************************************************************/
 268 void e1000_standby_eeprom(struct e1000_hw *hw)
 269 {
 270         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 271         uint32_t eecd;
 272
 273         eecd = E1000_READ_REG(hw, EECD);
 274
 275         if (eeprom->type == e1000_eeprom_microwire) {
 276                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 277                 E1000_WRITE_REG(hw, EECD, eecd);
 278                 E1000_WRITE_FLUSH(hw);
 279                 udelay(eeprom->delay_usec);
 280
 281                 /* Clock high */
 282                 eecd |= E1000_EECD_SK;
 283                 E1000_WRITE_REG(hw, EECD, eecd);
 284                 E1000_WRITE_FLUSH(hw);
 285                 udelay(eeprom->delay_usec);
 286
 287                 /* Select EEPROM */
 288                 eecd |= E1000_EECD_CS;
 289                 E1000_WRITE_REG(hw, EECD, eecd);
 290                 E1000_WRITE_FLUSH(hw);
 291                 udelay(eeprom->delay_usec);
 292
 293                 /* Clock low */
 294                 eecd &= ~E1000_EECD_SK;
 295                 E1000_WRITE_REG(hw, EECD, eecd);
 296                 E1000_WRITE_FLUSH(hw);
 297                 udelay(eeprom->delay_usec);
 298         } else if (eeprom->type == e1000_eeprom_spi) {
 299                 /* Toggle CS to flush commands */
 300                 eecd |= E1000_EECD_CS;
 301                 E1000_WRITE_REG(hw, EECD, eecd);
 302                 E1000_WRITE_FLUSH(hw);
 303                 udelay(eeprom->delay_usec);
 304                 eecd &= ~E1000_EECD_CS;
 305                 E1000_WRITE_REG(hw, EECD, eecd);
 306                 E1000_WRITE_FLUSH(hw);
 307                 udelay(eeprom->delay_usec);
 308         }
 309 }
 310
 311 /***************************************************************************
 312 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 313 *
 314 * hw - Struct containing variables accessed by shared code
 315 ****************************************************************************/
 316 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 317 {
 318         uint32_t eecd = 0;
 319
 320         DEBUGFUNC();
 321
 322         if (hw->mac_type == e1000_ich8lan)
 323                 return FALSE;
 324
 325         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 326                 eecd = E1000_READ_REG(hw, EECD);
 327
 328                 /* Isolate bits 15 & 16 */
 329                 eecd = ((eecd >> 15) & 0x03);
 330
 331                 /* If both bits are set, device is Flash type */
 332                 if (eecd == 0x03)
 333                         return FALSE;
 334         }
 335         return TRUE;
 336 }
 337
 338 /******************************************************************************
 339  * Prepares EEPROM for access
 340  *
 341  * hw - Struct containing variables accessed by shared code
 342  *
 343  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 344  * function should be called before issuing a command to the EEPROM.
 345  *****************************************************************************/
 346 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 347 {
 348         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 349         uint32_t eecd, i = 0;
 350
 351         DEBUGFUNC();
 352
 353         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 354                 return -E1000_ERR_SWFW_SYNC;
 355         eecd = E1000_READ_REG(hw, EECD);
 356
 357         if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
 358                 /* Request EEPROM Access */
 359                 if (hw->mac_type > e1000_82544) {
 360                         eecd |= E1000_EECD_REQ;
 361                         E1000_WRITE_REG(hw, EECD, eecd);
 362                         eecd = E1000_READ_REG(hw, EECD);
 363                         while ((!(eecd & E1000_EECD_GNT)) &&
 364                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 365                                 i++;
 366                                 udelay(5);
 367                                 eecd = E1000_READ_REG(hw, EECD);
 368                         }
 369                         if (!(eecd & E1000_EECD_GNT)) {
 370                                 eecd &= ~E1000_EECD_REQ;
 371                                 E1000_WRITE_REG(hw, EECD, eecd);
 372                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 373                                 return -E1000_ERR_EEPROM;
 374                         }
 375                 }
 376         }
 377
 378         /* Setup EEPROM for Read/Write */
 379
 380         if (eeprom->type == e1000_eeprom_microwire) {
 381                 /* Clear SK and DI */
 382                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 383                 E1000_WRITE_REG(hw, EECD, eecd);
 384
 385                 /* Set CS */
 386                 eecd |= E1000_EECD_CS;
 387                 E1000_WRITE_REG(hw, EECD, eecd);
 388         } else if (eeprom->type == e1000_eeprom_spi) {
 389                 /* Clear SK and CS */
 390                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 391                 E1000_WRITE_REG(hw, EECD, eecd);
 392                 udelay(1);
 393         }
 394
 395         return E1000_SUCCESS;
 396 }
 397
 398 /******************************************************************************
 399  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 400  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 401  * registers must be mapped, or this will crash.
 402  *
 403  * hw - Struct containing variables accessed by shared code
 404  *****************************************************************************/
 405 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 406 {
 407         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 408         uint32_t eecd = E1000_READ_REG(hw, EECD);
 409         int32_t ret_val = E1000_SUCCESS;
 410         uint16_t eeprom_size;
 411
 412         DEBUGFUNC();
 413
 414         switch (hw->mac_type) {
 415         case e1000_82542_rev2_0:
 416         case e1000_82542_rev2_1:
 417         case e1000_82543:
 418         case e1000_82544:
 419                 eeprom->type = e1000_eeprom_microwire;
 420                 eeprom->word_size = 64;
 421                 eeprom->opcode_bits = 3;
 422                 eeprom->address_bits = 6;
 423                 eeprom->delay_usec = 50;
 424                 eeprom->use_eerd = FALSE;
 425                 eeprom->use_eewr = FALSE;
 426         break;
 427         case e1000_82540:
 428         case e1000_82545:
 429         case e1000_82545_rev_3:
 430         case e1000_82546:
 431         case e1000_82546_rev_3:
 432                 eeprom->type = e1000_eeprom_microwire;
 433                 eeprom->opcode_bits = 3;
 434                 eeprom->delay_usec = 50;
 435                 if (eecd & E1000_EECD_SIZE) {
 436                         eeprom->word_size = 256;
 437                         eeprom->address_bits = 8;
 438                 } else {
 439                         eeprom->word_size = 64;
 440                         eeprom->address_bits = 6;
 441                 }
 442                 eeprom->use_eerd = FALSE;
 443                 eeprom->use_eewr = FALSE;
 444                 break;
 445         case e1000_82541:
 446         case e1000_82541_rev_2:
 447         case e1000_82547:
 448         case e1000_82547_rev_2:
 449                 if (eecd & E1000_EECD_TYPE) {
 450                         eeprom->type = e1000_eeprom_spi;
 451                         eeprom->opcode_bits = 8;
 452                         eeprom->delay_usec = 1;
 453                         if (eecd & E1000_EECD_ADDR_BITS) {
 454                                 eeprom->page_size = 32;
 455                                 eeprom->address_bits = 16;
 456                         } else {
 457                                 eeprom->page_size = 8;
 458                                 eeprom->address_bits = 8;
 459                         }
 460                 } else {
 461                         eeprom->type = e1000_eeprom_microwire;
 462                         eeprom->opcode_bits = 3;
 463                         eeprom->delay_usec = 50;
 464                         if (eecd & E1000_EECD_ADDR_BITS) {
 465                                 eeprom->word_size = 256;
 466                                 eeprom->address_bits = 8;
 467                         } else {
 468                                 eeprom->word_size = 64;
 469                                 eeprom->address_bits = 6;
 470                         }
 471                 }
 472                 eeprom->use_eerd = FALSE;
 473                 eeprom->use_eewr = FALSE;
 474                 break;
 475         case e1000_82571:
 476         case e1000_82572:
 477                 eeprom->type = e1000_eeprom_spi;
 478                 eeprom->opcode_bits = 8;
 479                 eeprom->delay_usec = 1;
 480                 if (eecd & E1000_EECD_ADDR_BITS) {
 481                         eeprom->page_size = 32;
 482                         eeprom->address_bits = 16;
 483                 } else {
 484                         eeprom->page_size = 8;
 485                         eeprom->address_bits = 8;
 486                 }
 487                 eeprom->use_eerd = FALSE;
 488                 eeprom->use_eewr = FALSE;
 489                 break;
 490         case e1000_82573:
 491         case e1000_82574:
 492                 eeprom->type = e1000_eeprom_spi;
 493                 eeprom->opcode_bits = 8;
 494                 eeprom->delay_usec = 1;
 495                 if (eecd & E1000_EECD_ADDR_BITS) {
 496                         eeprom->page_size = 32;
 497                         eeprom->address_bits = 16;
 498                 } else {
 499                         eeprom->page_size = 8;
 500                         eeprom->address_bits = 8;
 501                 }
 502                 eeprom->use_eerd = TRUE;
 503                 eeprom->use_eewr = TRUE;
 504                 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
 505                         eeprom->type = e1000_eeprom_flash;
 506                         eeprom->word_size = 2048;
 507
 508                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 509                  * Flash update issue on parts which use a FLASH for NVM. */
 510                         eecd &= ~E1000_EECD_AUPDEN;
 511                         E1000_WRITE_REG(hw, EECD, eecd);
 512                 }
 513                 break;
 514         case e1000_80003es2lan:
 515                 eeprom->type = e1000_eeprom_spi;
 516                 eeprom->opcode_bits = 8;
 517                 eeprom->delay_usec = 1;
 518                 if (eecd & E1000_EECD_ADDR_BITS) {
 519                         eeprom->page_size = 32;
 520                         eeprom->address_bits = 16;
 521                 } else {
 522                         eeprom->page_size = 8;
 523                         eeprom->address_bits = 8;
 524                 }
 525                 eeprom->use_eerd = TRUE;
 526                 eeprom->use_eewr = FALSE;
 527                 break;
 528
 529         /* ich8lan does not support currently. if needed, please
 530          * add corresponding code and functions.
 531          */
 532 #if 0
 533         case e1000_ich8lan:
 534                 {
 535                 int32_t  i = 0;
 536
 537                 eeprom->type = e1000_eeprom_ich8;
 538                 eeprom->use_eerd = FALSE;
 539                 eeprom->use_eewr = FALSE;
 540                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 541                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 542                                 ICH_FLASH_GFPREG);
 543                 /* Zero the shadow RAM structure. But don't load it from NVM
 544                  * so as to save time for driver init */
 545                 if (hw->eeprom_shadow_ram != NULL) {
 546                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 547                                 hw->eeprom_shadow_ram[i].modified = FALSE;
 548                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 549                         }
 550                 }
 551
 552                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 553                                 ICH_FLASH_SECTOR_SIZE;
 554
 555                 hw->flash_bank_size = ((flash_size >> 16)
 556                                 & ICH_GFPREG_BASE_MASK) + 1;
 557                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 558
 559                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 560
 561                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 562                 break;
 563                 }
 564 #endif
 565         default:
 566                 break;
 567         }
 568
 569         if (eeprom->type == e1000_eeprom_spi) {
 570                 /* eeprom_size will be an enum [0..8] that maps
 571                  * to eeprom sizes 128B to
 572                  * 32KB (incremented by powers of 2).
 573                  */
 574                 if (hw->mac_type <= e1000_82547_rev_2) {
 575                         /* Set to default value for initial eeprom read. */
 576                         eeprom->word_size = 64;
 577                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 578                                         &eeprom_size);
 579                         if (ret_val)
 580                                 return ret_val;
 581                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 582                                 >> EEPROM_SIZE_SHIFT;
 583                         /* 256B eeprom size was not supported in earlier
 584                          * hardware, so we bump eeprom_size up one to
 585                          * ensure that "1" (which maps to 256B) is never
 586                          * the result used in the shifting logic below. */
 587                         if (eeprom_size)
 588                                 eeprom_size++;
 589                 } else {
 590                         eeprom_size = (uint16_t)((eecd &
 591                                 E1000_EECD_SIZE_EX_MASK) >>
 592                                 E1000_EECD_SIZE_EX_SHIFT);
 593                 }
 594
 595                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 596         }
 597         return ret_val;
 598 }
 599
 600 /******************************************************************************
 601  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 602  *
 603  * hw - Struct containing variables accessed by shared code
 604  *****************************************************************************/
 605 static int32_t
 606 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 607 {
 608         uint32_t attempts = 100000;
 609         uint32_t i, reg = 0;
 610         int32_t done = E1000_ERR_EEPROM;
 611
 612         for (i = 0; i < attempts; i++) {
 613                 if (eerd == E1000_EEPROM_POLL_READ)
 614                         reg = E1000_READ_REG(hw, EERD);
 615                 else
 616                         reg = E1000_READ_REG(hw, EEWR);
 617
 618                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 619                         done = E1000_SUCCESS;
 620                         break;
 621                 }
 622                 udelay(5);
 623         }
 624
 625         return done;
 626 }
 627
 628 /******************************************************************************
 629  * Reads a 16 bit word from the EEPROM using the EERD register.
 630  *
 631  * hw - Struct containing variables accessed by shared code
 632  * offset - offset of  word in the EEPROM to read
 633  * data - word read from the EEPROM
 634  * words - number of words to read
 635  *****************************************************************************/
 636 static int32_t
 637 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 638                         uint16_t offset,
 639                         uint16_t words,
 640                         uint16_t *data)
 641 {
 642         uint32_t i, eerd = 0;
 643         int32_t error = 0;
 644
 645         for (i = 0; i < words; i++) {
 646                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 647                         E1000_EEPROM_RW_REG_START;
 648
 649                 E1000_WRITE_REG(hw, EERD, eerd);
 650                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 651
 652                 if (error)
 653                         break;
 654                 data[i] = (E1000_READ_REG(hw, EERD) >>
 655                                 E1000_EEPROM_RW_REG_DATA);
 656
 657         }
 658
 659         return error;
 660 }
 661
 662 void e1000_release_eeprom(struct e1000_hw *hw)
 663 {
 664         uint32_t eecd;
 665
 666         DEBUGFUNC();
 667
 668         eecd = E1000_READ_REG(hw, EECD);
 669
 670         if (hw->eeprom.type == e1000_eeprom_spi) {
 671                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 672                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 673
 674                 E1000_WRITE_REG(hw, EECD, eecd);
 675
 676                 udelay(hw->eeprom.delay_usec);
 677         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 678                 /* cleanup eeprom */
 679
 680                 /* CS on Microwire is active-high */
 681                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 682
 683                 E1000_WRITE_REG(hw, EECD, eecd);
 684
 685                 /* Rising edge of clock */
 686                 eecd |= E1000_EECD_SK;
 687                 E1000_WRITE_REG(hw, EECD, eecd);
 688                 E1000_WRITE_FLUSH(hw);
 689                 udelay(hw->eeprom.delay_usec);
 690
 691                 /* Falling edge of clock */
 692                 eecd &= ~E1000_EECD_SK;
 693                 E1000_WRITE_REG(hw, EECD, eecd);
 694                 E1000_WRITE_FLUSH(hw);
 695                 udelay(hw->eeprom.delay_usec);
 696         }
 697
 698         /* Stop requesting EEPROM access */
 699         if (hw->mac_type > e1000_82544) {
 700                 eecd &= ~E1000_EECD_REQ;
 701                 E1000_WRITE_REG(hw, EECD, eecd);
 702         }
 703 }
 704 /******************************************************************************
 705  * Reads a 16 bit word from the EEPROM.
 706  *
 707  * hw - Struct containing variables accessed by shared code
 708  *****************************************************************************/
 709 static int32_t
 710 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 711 {
 712         uint16_t retry_count = 0;
 713         uint8_t spi_stat_reg;
 714
 715         DEBUGFUNC();
 716
 717         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 718          * EEPROM will signal that the command has been completed by clearing
 719          * bit 0 of the internal status register.  If it's not cleared within
 720          * 5 milliseconds, then error out.
 721          */
 722         retry_count = 0;
 723         do {
 724                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 725                         hw->eeprom.opcode_bits);
 726                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 727                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 728                         break;
 729
 730                 udelay(5);
 731                 retry_count += 5;
 732
 733                 e1000_standby_eeprom(hw);
 734         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 735
 736         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 737          * only 0-5mSec on 5V devices)
 738          */
 739         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 740                 DEBUGOUT("SPI EEPROM Status error\n");
 741                 return -E1000_ERR_EEPROM;
 742         }
 743
 744         return E1000_SUCCESS;
 745 }
 746
 747 /******************************************************************************
 748  * Reads a 16 bit word from the EEPROM.
 749  *
 750  * hw - Struct containing variables accessed by shared code
 751  * offset - offset of  word in the EEPROM to read
 752  * data - word read from the EEPROM
 753  *****************************************************************************/
 754 static int32_t
 755 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 756                 uint16_t words, uint16_t *data)
 757 {
 758         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 759         uint32_t i = 0;
 760
 761         DEBUGFUNC();
 762
 763         /* If eeprom is not yet detected, do so now */
 764         if (eeprom->word_size == 0)
 765                 e1000_init_eeprom_params(hw);
 766
 767         /* A check for invalid values:  offset too large, too many words,
 768          * and not enough words.
 769          */
 770         if ((offset >= eeprom->word_size) ||
 771                 (words > eeprom->word_size - offset) ||
 772                 (words == 0)) {
 773                 DEBUGOUT("\"words\" parameter out of bounds."
 774                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 775                 return -E1000_ERR_EEPROM;
 776         }
 777
 778         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 779          * directly. In this case, we need to acquire the EEPROM so that
 780          * FW or other port software does not interrupt.
 781          */
 782         if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
 783                 hw->eeprom.use_eerd == FALSE) {
 784
 785                 /* Prepare the EEPROM for bit-bang reading */
 786                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 787                         return -E1000_ERR_EEPROM;
 788         }
 789
 790         /* Eerd register EEPROM access requires no eeprom aquire/release */
 791         if (eeprom->use_eerd == TRUE)
 792                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 793
 794         /* ich8lan does not support currently. if needed, please
 795          * add corresponding code and functions.
 796          */
 797 #if 0
 798         /* ICH EEPROM access is done via the ICH flash controller */
 799         if (eeprom->type == e1000_eeprom_ich8)
 800                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 801 #endif
 802         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 803          * acquired the EEPROM at this point, so any returns should relase it */
 804         if (eeprom->type == e1000_eeprom_spi) {
 805                 uint16_t word_in;
 806                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 807
 808                 if (e1000_spi_eeprom_ready(hw)) {
 809                         e1000_release_eeprom(hw);
 810                         return -E1000_ERR_EEPROM;
 811                 }
 812
 813                 e1000_standby_eeprom(hw);
 814
 815                 /* Some SPI eeproms use the 8th address bit embedded in
 816                  * the opcode */
 817                 if ((eeprom->address_bits == 8) && (offset >= 128))
 818                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 819
 820                 /* Send the READ command (opcode + addr)  */
 821                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 822                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 823                                 eeprom->address_bits);
 824
 825                 /* Read the data.  The address of the eeprom internally
 826                  * increments with each byte (spi) being read, saving on the
 827                  * overhead of eeprom setup and tear-down.  The address
 828                  * counter will roll over if reading beyond the size of
 829                  * the eeprom, thus allowing the entire memory to be read
 830                  * starting from any offset. */
 831                 for (i = 0; i < words; i++) {
 832                         word_in = e1000_shift_in_ee_bits(hw, 16);
 833                         data[i] = (word_in >> 8) | (word_in << 8);
 834                 }
 835         } else if (eeprom->type == e1000_eeprom_microwire) {
 836                 for (i = 0; i < words; i++) {
 837                         /* Send the READ command (opcode + addr)  */
 838                         e1000_shift_out_ee_bits(hw,
 839                                 EEPROM_READ_OPCODE_MICROWIRE,
 840                                 eeprom->opcode_bits);
 841                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 842                                 eeprom->address_bits);
 843
 844                         /* Read the data.  For microwire, each word requires
 845                          * the overhead of eeprom setup and tear-down. */
 846                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 847                         e1000_standby_eeprom(hw);
 848                 }
 849         }
 850
 851         /* End this read operation */
 852         e1000_release_eeprom(hw);
 853
 854         return E1000_SUCCESS;
 855 }
 856
 857 /******************************************************************************
 858  * Verifies that the EEPROM has a valid checksum
 859  *
 860  * hw - Struct containing variables accessed by shared code
 861  *
 862  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 863  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 864  * valid.
 865  *****************************************************************************/
 866 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 867 {
 868         uint16_t i, checksum, checksum_reg, *buf;
 869
 870         DEBUGFUNC();
 871
 872         /* Allocate a temporary buffer */
 873         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
 874         if (!buf) {
 875                 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
 876                 return -E1000_ERR_EEPROM;
 877         }
 878
 879         /* Read the EEPROM */
 880         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
 881                 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
 882                 return -E1000_ERR_EEPROM;
 883         }
 884
 885         /* Compute the checksum */
 886         checksum = 0;
 887         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
 888                 checksum += buf[i];
 889         checksum = ((uint16_t)EEPROM_SUM) - checksum;
 890         checksum_reg = buf[i];
 891
 892         /* Verify it! */
 893         if (checksum == checksum_reg)
 894                 return 0;
 895
 896         /* Hrm, verification failed, print an error */
 897         E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
 898         E1000_ERR(hw->nic, "  ...register was 0x%04hx, calculated 0x%04hx\n",
 899                         checksum_reg, checksum);
 900
 901         return -E1000_ERR_EEPROM;
 902 }
 903
 904 /*****************************************************************************
 905  * Set PHY to class A mode
 906  * Assumes the following operations will follow to enable the new class mode.
 907  *  1. Do a PHY soft reset
 908  *  2. Restart auto-negotiation or force link.
 909  *
 910  * hw - Struct containing variables accessed by shared code
 911  ****************************************************************************/
 912 static int32_t
 913 e1000_set_phy_mode(struct e1000_hw *hw)
 914 {
 915         int32_t ret_val;
 916         uint16_t eeprom_data;
 917
 918         DEBUGFUNC();
 919
 920         if ((hw->mac_type == e1000_82545_rev_3) &&
 921                 (hw->media_type == e1000_media_type_copper)) {
 922                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 923                                 1, &eeprom_data);
 924                 if (ret_val)
 925                         return ret_val;
 926
 927                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 928                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 929                         ret_val = e1000_write_phy_reg(hw,
 930                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 931                         if (ret_val)
 932                                 return ret_val;
 933                         ret_val = e1000_write_phy_reg(hw,
 934                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 935                         if (ret_val)
 936                                 return ret_val;
 937
 938                         hw->phy_reset_disable = FALSE;
 939                 }
 940         }
 941
 942         return E1000_SUCCESS;
 943 }
 944
 945 /***************************************************************************
 946  *
 947  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 948  *
 949  * hw: Struct containing variables accessed by shared code
 950  *
 951  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 952  *            E1000_SUCCESS at any other case.
 953  *
 954  ***************************************************************************/
 955 static int32_t
 956 e1000_get_software_semaphore(struct e1000_hw *hw)
 957 {
 958          int32_t timeout = hw->eeprom.word_size + 1;
 959          uint32_t swsm;
 960
 961         DEBUGFUNC();
 962
 963         if (hw->mac_type != e1000_80003es2lan)
 964                 return E1000_SUCCESS;
 965
 966         while (timeout) {
 967                 swsm = E1000_READ_REG(hw, SWSM);
 968                 /* If SMBI bit cleared, it is now set and we hold
 969                  * the semaphore */
 970                 if (!(swsm & E1000_SWSM_SMBI))
 971                         break;
 972                 mdelay(1);
 973                 timeout--;
 974         }
 975
 976         if (!timeout) {
 977                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 978                 return -E1000_ERR_RESET;
 979         }
 980
 981         return E1000_SUCCESS;
 982 }
 983
 984 /***************************************************************************
 985  * This function clears HW semaphore bits.
 986  *
 987  * hw: Struct containing variables accessed by shared code
 988  *
 989  * returns: - None.
 990  *
 991  ***************************************************************************/
 992 static void
 993 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 994 {
 995          uint32_t swsm;
 996
 997         DEBUGFUNC();
 998
 999         if (!hw->eeprom_semaphore_present)
1000                 return;
1001
1002         swsm = E1000_READ_REG(hw, SWSM);
1003         if (hw->mac_type == e1000_80003es2lan) {
1004                 /* Release both semaphores. */
1005                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1006         } else
1007                 swsm &= ~(E1000_SWSM_SWESMBI);
1008         E1000_WRITE_REG(hw, SWSM, swsm);
1009 }
1010
1011 /***************************************************************************
1012  *
1013  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1014  * adapter or Eeprom access.
1015  *
1016  * hw: Struct containing variables accessed by shared code
1017  *
1018  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1019  *            E1000_SUCCESS at any other case.
1020  *
1021  ***************************************************************************/
1022 static int32_t
1023 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1024 {
1025         int32_t timeout;
1026         uint32_t swsm;
1027
1028         DEBUGFUNC();
1029
1030         if (!hw->eeprom_semaphore_present)
1031                 return E1000_SUCCESS;
1032
1033         if (hw->mac_type == e1000_80003es2lan) {
1034                 /* Get the SW semaphore. */
1035                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1036                         return -E1000_ERR_EEPROM;
1037         }
1038
1039         /* Get the FW semaphore. */
1040         timeout = hw->eeprom.word_size + 1;
1041         while (timeout) {
1042                 swsm = E1000_READ_REG(hw, SWSM);
1043                 swsm |= E1000_SWSM_SWESMBI;
1044                 E1000_WRITE_REG(hw, SWSM, swsm);
1045                 /* if we managed to set the bit we got the semaphore. */
1046                 swsm = E1000_READ_REG(hw, SWSM);
1047                 if (swsm & E1000_SWSM_SWESMBI)
1048                         break;
1049
1050                 udelay(50);
1051                 timeout--;
1052         }
1053
1054         if (!timeout) {
1055                 /* Release semaphores */
1056                 e1000_put_hw_eeprom_semaphore(hw);
1057                 DEBUGOUT("Driver can't access the Eeprom - "
1058                                 "SWESMBI bit is set.\n");
1059                 return -E1000_ERR_EEPROM;
1060         }
1061
1062         return E1000_SUCCESS;
1063 }
1064
1065 static int32_t
1066 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1067 {
1068         uint32_t swfw_sync = 0;
1069         uint32_t swmask = mask;
1070         uint32_t fwmask = mask << 16;
1071         int32_t timeout = 200;
1072
1073         DEBUGFUNC();
1074         while (timeout) {
1075                 if (e1000_get_hw_eeprom_semaphore(hw))
1076                         return -E1000_ERR_SWFW_SYNC;
1077
1078                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1079                 if (!(swfw_sync & (fwmask | swmask)))
1080                         break;
1081
1082                 /* firmware currently using resource (fwmask) */
1083                 /* or other software thread currently using resource (swmask) */
1084                 e1000_put_hw_eeprom_semaphore(hw);
1085                 mdelay(5);
1086                 timeout--;
1087         }
1088
1089         if (!timeout) {
1090                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1091                 return -E1000_ERR_SWFW_SYNC;
1092         }
1093
1094         swfw_sync |= swmask;
1095         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1096
1097         e1000_put_hw_eeprom_semaphore(hw);
1098         return E1000_SUCCESS;
1099 }
1100
1101 static boolean_t e1000_is_second_port(struct e1000_hw *hw)
1102 {
1103         switch (hw->mac_type) {
1104         case e1000_80003es2lan:
1105         case e1000_82546:
1106         case e1000_82571:
1107                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1108                         return TRUE;
1109                 /* Fallthrough */
1110         default:
1111                 return FALSE;
1112         }
1113 }
1114
1115 /******************************************************************************
1116  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1117  * second function of dual function devices
1118  *
1119  * nic - Struct containing variables accessed by shared code
1120  *****************************************************************************/
1121 static int
1122 e1000_read_mac_addr(struct eth_device *nic)
1123 {
1124         struct e1000_hw *hw = nic->priv;
1125         uint16_t offset;
1126         uint16_t eeprom_data;
1127         int i;
1128
1129         DEBUGFUNC();
1130
1131         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1132                 offset = i >> 1;
1133                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1134                         DEBUGOUT("EEPROM Read Error\n");
1135                         return -E1000_ERR_EEPROM;
1136                 }
1137                 nic->enetaddr[i] = eeprom_data & 0xff;
1138                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1139         }
1140
1141         /* Invert the last bit if this is the second device */
1142         if (e1000_is_second_port(hw))
1143                 nic->enetaddr[5] ^= 1;
1144
1145 #ifdef CONFIG_E1000_FALLBACK_MAC
1146         if (!is_valid_ether_addr(nic->enetaddr)) {
1147                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1148
1149                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1150         }
1151 #endif
1152         return 0;
1153 }
1154
1155 /******************************************************************************
1156  * Initializes receive address filters.
1157  *
1158  * hw - Struct containing variables accessed by shared code
1159  *
1160  * Places the MAC address in receive address register 0 and clears the rest
1161  * of the receive addresss registers. Clears the multicast table. Assumes
1162  * the receiver is in reset when the routine is called.
1163  *****************************************************************************/
1164 static void
1165 e1000_init_rx_addrs(struct eth_device *nic)
1166 {
1167         struct e1000_hw *hw = nic->priv;
1168         uint32_t i;
1169         uint32_t addr_low;
1170         uint32_t addr_high;
1171
1172         DEBUGFUNC();
1173
1174         /* Setup the receive address. */
1175         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1176         addr_low = (nic->enetaddr[0] |
1177                     (nic->enetaddr[1] << 8) |
1178                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1179
1180         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1181
1182         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1183         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1184
1185         /* Zero out the other 15 receive addresses. */
1186         DEBUGOUT("Clearing RAR[1-15]\n");
1187         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1188                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1189                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1190         }
1191 }
1192
1193 /******************************************************************************
1194  * Clears the VLAN filer table
1195  *
1196  * hw - Struct containing variables accessed by shared code
1197  *****************************************************************************/
1198 static void
1199 e1000_clear_vfta(struct e1000_hw *hw)
1200 {
1201         uint32_t offset;
1202
1203         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1204                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1205 }
1206
1207 /******************************************************************************
1208  * Set the mac type member in the hw struct.
1209  *
1210  * hw - Struct containing variables accessed by shared code
1211  *****************************************************************************/
1212 int32_t
1213 e1000_set_mac_type(struct e1000_hw *hw)
1214 {
1215         DEBUGFUNC();
1216
1217         switch (hw->device_id) {
1218         case E1000_DEV_ID_82542:
1219                 switch (hw->revision_id) {
1220                 case E1000_82542_2_0_REV_ID:
1221                         hw->mac_type = e1000_82542_rev2_0;
1222                         break;
1223                 case E1000_82542_2_1_REV_ID:
1224                         hw->mac_type = e1000_82542_rev2_1;
1225                         break;
1226                 default:
1227                         /* Invalid 82542 revision ID */
1228                         return -E1000_ERR_MAC_TYPE;
1229                 }
1230                 break;
1231         case E1000_DEV_ID_82543GC_FIBER:
1232         case E1000_DEV_ID_82543GC_COPPER:
1233                 hw->mac_type = e1000_82543;
1234                 break;
1235         case E1000_DEV_ID_82544EI_COPPER:
1236         case E1000_DEV_ID_82544EI_FIBER:
1237         case E1000_DEV_ID_82544GC_COPPER:
1238         case E1000_DEV_ID_82544GC_LOM:
1239                 hw->mac_type = e1000_82544;
1240                 break;
1241         case E1000_DEV_ID_82540EM:
1242         case E1000_DEV_ID_82540EM_LOM:
1243         case E1000_DEV_ID_82540EP:
1244         case E1000_DEV_ID_82540EP_LOM:
1245         case E1000_DEV_ID_82540EP_LP:
1246                 hw->mac_type = e1000_82540;
1247                 break;
1248         case E1000_DEV_ID_82545EM_COPPER:
1249         case E1000_DEV_ID_82545EM_FIBER:
1250                 hw->mac_type = e1000_82545;
1251                 break;
1252         case E1000_DEV_ID_82545GM_COPPER:
1253         case E1000_DEV_ID_82545GM_FIBER:
1254         case E1000_DEV_ID_82545GM_SERDES:
1255                 hw->mac_type = e1000_82545_rev_3;
1256                 break;
1257         case E1000_DEV_ID_82546EB_COPPER:
1258         case E1000_DEV_ID_82546EB_FIBER:
1259         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1260                 hw->mac_type = e1000_82546;
1261                 break;
1262         case E1000_DEV_ID_82546GB_COPPER:
1263         case E1000_DEV_ID_82546GB_FIBER:
1264         case E1000_DEV_ID_82546GB_SERDES:
1265         case E1000_DEV_ID_82546GB_PCIE:
1266         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1267         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1268                 hw->mac_type = e1000_82546_rev_3;
1269                 break;
1270         case E1000_DEV_ID_82541EI:
1271         case E1000_DEV_ID_82541EI_MOBILE:
1272         case E1000_DEV_ID_82541ER_LOM:
1273                 hw->mac_type = e1000_82541;
1274                 break;
1275         case E1000_DEV_ID_82541ER:
1276         case E1000_DEV_ID_82541GI:
1277         case E1000_DEV_ID_82541GI_LF:
1278         case E1000_DEV_ID_82541GI_MOBILE:
1279                 hw->mac_type = e1000_82541_rev_2;
1280                 break;
1281         case E1000_DEV_ID_82547EI:
1282         case E1000_DEV_ID_82547EI_MOBILE:
1283                 hw->mac_type = e1000_82547;
1284                 break;
1285         case E1000_DEV_ID_82547GI:
1286                 hw->mac_type = e1000_82547_rev_2;
1287                 break;
1288         case E1000_DEV_ID_82571EB_COPPER:
1289         case E1000_DEV_ID_82571EB_FIBER:
1290         case E1000_DEV_ID_82571EB_SERDES:
1291         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1292         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1293         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1294         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1295         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1296         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1297                 hw->mac_type = e1000_82571;
1298                 break;
1299         case E1000_DEV_ID_82572EI_COPPER:
1300         case E1000_DEV_ID_82572EI_FIBER:
1301         case E1000_DEV_ID_82572EI_SERDES:
1302         case E1000_DEV_ID_82572EI:
1303                 hw->mac_type = e1000_82572;
1304                 break;
1305         case E1000_DEV_ID_82573E:
1306         case E1000_DEV_ID_82573E_IAMT:
1307         case E1000_DEV_ID_82573L:
1308                 hw->mac_type = e1000_82573;
1309                 break;
1310         case E1000_DEV_ID_82574L:
1311                 hw->mac_type = e1000_82574;
1312                 break;
1313         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1314         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1315         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1316         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1317                 hw->mac_type = e1000_80003es2lan;
1318                 break;
1319         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1320         case E1000_DEV_ID_ICH8_IGP_AMT:
1321         case E1000_DEV_ID_ICH8_IGP_C:
1322         case E1000_DEV_ID_ICH8_IFE:
1323         case E1000_DEV_ID_ICH8_IFE_GT:
1324         case E1000_DEV_ID_ICH8_IFE_G:
1325         case E1000_DEV_ID_ICH8_IGP_M:
1326                 hw->mac_type = e1000_ich8lan;
1327                 break;
1328         default:
1329                 /* Should never have loaded on this device */
1330                 return -E1000_ERR_MAC_TYPE;
1331         }
1332         return E1000_SUCCESS;
1333 }
1334
1335 /******************************************************************************
1336  * Reset the transmit and receive units; mask and clear all interrupts.
1337  *
1338  * hw - Struct containing variables accessed by shared code
1339  *****************************************************************************/
1340 void
1341 e1000_reset_hw(struct e1000_hw *hw)
1342 {
1343         uint32_t ctrl;
1344         uint32_t ctrl_ext;
1345         uint32_t manc;
1346         uint32_t pba = 0;
1347
1348         DEBUGFUNC();
1349
1350         /* get the correct pba value for both PCI and PCIe*/
1351         if (hw->mac_type <  e1000_82571)
1352                 pba = E1000_DEFAULT_PCI_PBA;
1353         else
1354                 pba = E1000_DEFAULT_PCIE_PBA;
1355
1356         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1357         if (hw->mac_type == e1000_82542_rev2_0) {
1358                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1359                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1360                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1361         }
1362
1363         /* Clear interrupt mask to stop board from generating interrupts */
1364         DEBUGOUT("Masking off all interrupts\n");
1365         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1366
1367         /* Disable the Transmit and Receive units.  Then delay to allow
1368          * any pending transactions to complete before we hit the MAC with
1369          * the global reset.
1370          */
1371         E1000_WRITE_REG(hw, RCTL, 0);
1372         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1373         E1000_WRITE_FLUSH(hw);
1374
1375         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1376         hw->tbi_compatibility_on = FALSE;
1377
1378         /* Delay to allow any outstanding PCI transactions to complete before
1379          * resetting the device
1380          */
1381         mdelay(10);
1382
1383         /* Issue a global reset to the MAC.  This will reset the chip's
1384          * transmit, receive, DMA, and link units.  It will not effect
1385          * the current PCI configuration.  The global reset bit is self-
1386          * clearing, and should clear within a microsecond.
1387          */
1388         DEBUGOUT("Issuing a global reset to MAC\n");
1389         ctrl = E1000_READ_REG(hw, CTRL);
1390
1391         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1392
1393         /* Force a reload from the EEPROM if necessary */
1394         if (hw->mac_type < e1000_82540) {
1395                 /* Wait for reset to complete */
1396                 udelay(10);
1397                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1398                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1399                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1400                 E1000_WRITE_FLUSH(hw);
1401                 /* Wait for EEPROM reload */
1402                 mdelay(2);
1403         } else {
1404                 /* Wait for EEPROM reload (it happens automatically) */
1405                 mdelay(4);
1406                 /* Dissable HW ARPs on ASF enabled adapters */
1407                 manc = E1000_READ_REG(hw, MANC);
1408                 manc &= ~(E1000_MANC_ARP_EN);
1409                 E1000_WRITE_REG(hw, MANC, manc);
1410         }
1411
1412         /* Clear interrupt mask to stop board from generating interrupts */
1413         DEBUGOUT("Masking off all interrupts\n");
1414         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1415
1416         /* Clear any pending interrupt events. */
1417         E1000_READ_REG(hw, ICR);
1418
1419         /* If MWI was previously enabled, reenable it. */
1420         if (hw->mac_type == e1000_82542_rev2_0) {
1421                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1422         }
1423         E1000_WRITE_REG(hw, PBA, pba);
1424 }
1425
1426 /******************************************************************************
1427  *
1428  * Initialize a number of hardware-dependent bits
1429  *
1430  * hw: Struct containing variables accessed by shared code
1431  *
1432  * This function contains hardware limitation workarounds for PCI-E adapters
1433  *
1434  *****************************************************************************/
1435 static void
1436 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1437 {
1438         if ((hw->mac_type >= e1000_82571) &&
1439                         (!hw->initialize_hw_bits_disable)) {
1440                 /* Settings common to all PCI-express silicon */
1441                 uint32_t reg_ctrl, reg_ctrl_ext;
1442                 uint32_t reg_tarc0, reg_tarc1;
1443                 uint32_t reg_tctl;
1444                 uint32_t reg_txdctl, reg_txdctl1;
1445
1446                 /* link autonegotiation/sync workarounds */
1447                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1448                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1449
1450                 /* Enable not-done TX descriptor counting */
1451                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1452                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1453                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1454
1455                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1456                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1457                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1458
1459                 switch (hw->mac_type) {
1460                 case e1000_82571:
1461                 case e1000_82572:
1462                         /* Clear PHY TX compatible mode bits */
1463                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1464                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1465
1466                         /* link autonegotiation/sync workarounds */
1467                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1468
1469                         /* TX ring control fixes */
1470                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1471
1472                         /* Multiple read bit is reversed polarity */
1473                         reg_tctl = E1000_READ_REG(hw, TCTL);
1474                         if (reg_tctl & E1000_TCTL_MULR)
1475                                 reg_tarc1 &= ~(1 << 28);
1476                         else
1477                                 reg_tarc1 |= (1 << 28);
1478
1479                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1480                         break;
1481                 case e1000_82573:
1482                 case e1000_82574:
1483                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1484                         reg_ctrl_ext &= ~(1 << 23);
1485                         reg_ctrl_ext |= (1 << 22);
1486
1487                         /* TX byte count fix */
1488                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1489                         reg_ctrl &= ~(1 << 29);
1490
1491                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1492                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1493                         break;
1494                 case e1000_80003es2lan:
1495         /* improve small packet performace for fiber/serdes */
1496                         if ((hw->media_type == e1000_media_type_fiber)
1497                         || (hw->media_type ==
1498                                 e1000_media_type_internal_serdes)) {
1499                                 reg_tarc0 &= ~(1 << 20);
1500                         }
1501
1502                 /* Multiple read bit is reversed polarity */
1503                         reg_tctl = E1000_READ_REG(hw, TCTL);
1504                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1505                         if (reg_tctl & E1000_TCTL_MULR)
1506                                 reg_tarc1 &= ~(1 << 28);
1507                         else
1508                                 reg_tarc1 |= (1 << 28);
1509
1510                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1511                         break;
1512                 case e1000_ich8lan:
1513                         /* Reduce concurrent DMA requests to 3 from 4 */
1514                         if ((hw->revision_id < 3) ||
1515                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1516                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1517                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1518
1519                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1520                         reg_ctrl_ext |= (1 << 22);
1521                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1522
1523                         /* workaround TX hang with TSO=on */
1524                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1525
1526                         /* Multiple read bit is reversed polarity */
1527                         reg_tctl = E1000_READ_REG(hw, TCTL);
1528                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1529                         if (reg_tctl & E1000_TCTL_MULR)
1530                                 reg_tarc1 &= ~(1 << 28);
1531                         else
1532                                 reg_tarc1 |= (1 << 28);
1533
1534                         /* workaround TX hang with TSO=on */
1535                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1536
1537                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1538                         break;
1539                 default:
1540                         break;
1541                 }
1542
1543                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1544         }
1545 }
1546
1547 /******************************************************************************
1548  * Performs basic configuration of the adapter.
1549  *
1550  * hw - Struct containing variables accessed by shared code
1551  *
1552  * Assumes that the controller has previously been reset and is in a
1553  * post-reset uninitialized state. Initializes the receive address registers,
1554  * multicast table, and VLAN filter table. Calls routines to setup link
1555  * configuration and flow control settings. Clears all on-chip counters. Leaves
1556  * the transmit and receive units disabled and uninitialized.
1557  *****************************************************************************/
1558 static int
1559 e1000_init_hw(struct eth_device *nic)
1560 {
1561         struct e1000_hw *hw = nic->priv;
1562         uint32_t ctrl;
1563         uint32_t i;
1564         int32_t ret_val;
1565         uint16_t pcix_cmd_word;
1566         uint16_t pcix_stat_hi_word;
1567         uint16_t cmd_mmrbc;
1568         uint16_t stat_mmrbc;
1569         uint32_t mta_size;
1570         uint32_t reg_data;
1571         uint32_t ctrl_ext;
1572         DEBUGFUNC();
1573         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1574         if ((hw->mac_type == e1000_ich8lan) &&
1575                 ((hw->revision_id < 3) ||
1576                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1577                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1578                         reg_data = E1000_READ_REG(hw, STATUS);
1579                         reg_data &= ~0x80000000;
1580                         E1000_WRITE_REG(hw, STATUS, reg_data);
1581         }
1582         /* Do not need initialize Identification LED */
1583
1584         /* Set the media type and TBI compatibility */
1585         e1000_set_media_type(hw);
1586
1587         /* Must be called after e1000_set_media_type
1588          * because media_type is used */
1589         e1000_initialize_hardware_bits(hw);
1590
1591         /* Disabling VLAN filtering. */
1592         DEBUGOUT("Initializing the IEEE VLAN\n");
1593         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1594         if (hw->mac_type != e1000_ich8lan) {
1595                 if (hw->mac_type < e1000_82545_rev_3)
1596                         E1000_WRITE_REG(hw, VET, 0);
1597                 e1000_clear_vfta(hw);
1598         }
1599
1600         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1601         if (hw->mac_type == e1000_82542_rev2_0) {
1602                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1603                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1604                                       hw->
1605                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1606                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1607                 E1000_WRITE_FLUSH(hw);
1608                 mdelay(5);
1609         }
1610
1611         /* Setup the receive address. This involves initializing all of the Receive
1612          * Address Registers (RARs 0 - 15).
1613          */
1614         e1000_init_rx_addrs(nic);
1615
1616         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1617         if (hw->mac_type == e1000_82542_rev2_0) {
1618                 E1000_WRITE_REG(hw, RCTL, 0);
1619                 E1000_WRITE_FLUSH(hw);
1620                 mdelay(1);
1621                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1622         }
1623
1624         /* Zero out the Multicast HASH table */
1625         DEBUGOUT("Zeroing the MTA\n");
1626         mta_size = E1000_MC_TBL_SIZE;
1627         if (hw->mac_type == e1000_ich8lan)
1628                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1629         for (i = 0; i < mta_size; i++) {
1630                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1631                 /* use write flush to prevent Memory Write Block (MWB) from
1632                  * occuring when accessing our register space */
1633                 E1000_WRITE_FLUSH(hw);
1634         }
1635 #if 0
1636         /* Set the PCI priority bit correctly in the CTRL register.  This
1637          * determines if the adapter gives priority to receives, or if it
1638          * gives equal priority to transmits and receives.  Valid only on
1639          * 82542 and 82543 silicon.
1640          */
1641         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1642                 ctrl = E1000_READ_REG(hw, CTRL);
1643                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1644         }
1645 #endif
1646         switch (hw->mac_type) {
1647         case e1000_82545_rev_3:
1648         case e1000_82546_rev_3:
1649                 break;
1650         default:
1651         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1652         if (hw->bus_type == e1000_bus_type_pcix) {
1653                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1654                                      &pcix_cmd_word);
1655                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1656                                      &pcix_stat_hi_word);
1657                 cmd_mmrbc =
1658                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1659                     PCIX_COMMAND_MMRBC_SHIFT;
1660                 stat_mmrbc =
1661                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1662                     PCIX_STATUS_HI_MMRBC_SHIFT;
1663                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1664                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1665                 if (cmd_mmrbc > stat_mmrbc) {
1666                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1667                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1668                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1669                                               pcix_cmd_word);
1670                 }
1671         }
1672                 break;
1673         }
1674
1675         /* More time needed for PHY to initialize */
1676         if (hw->mac_type == e1000_ich8lan)
1677                 mdelay(15);
1678
1679         /* Call a subroutine to configure the link and setup flow control. */
1680         ret_val = e1000_setup_link(nic);
1681
1682         /* Set the transmit descriptor write-back policy */
1683         if (hw->mac_type > e1000_82544) {
1684                 ctrl = E1000_READ_REG(hw, TXDCTL);
1685                 ctrl =
1686                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1687                     E1000_TXDCTL_FULL_TX_DESC_WB;
1688                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1689         }
1690
1691         switch (hw->mac_type) {
1692         default:
1693                 break;
1694         case e1000_80003es2lan:
1695                 /* Enable retransmit on late collisions */
1696                 reg_data = E1000_READ_REG(hw, TCTL);
1697                 reg_data |= E1000_TCTL_RTLC;
1698                 E1000_WRITE_REG(hw, TCTL, reg_data);
1699
1700                 /* Configure Gigabit Carry Extend Padding */
1701                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1702                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1703                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1704                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1705
1706                 /* Configure Transmit Inter-Packet Gap */
1707                 reg_data = E1000_READ_REG(hw, TIPG);
1708                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1709                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1710                 E1000_WRITE_REG(hw, TIPG, reg_data);
1711
1712                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1713                 reg_data &= ~0x00100000;
1714                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1715                 /* Fall through */
1716         case e1000_82571:
1717         case e1000_82572:
1718         case e1000_ich8lan:
1719                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1720                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1721                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1722                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1723                 break;
1724         case e1000_82573:
1725         case e1000_82574:
1726                 reg_data = E1000_READ_REG(hw, GCR);
1727                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1728                 E1000_WRITE_REG(hw, GCR, reg_data);
1729         }
1730
1731 #if 0
1732         /* Clear all of the statistics registers (clear on read).  It is
1733          * important that we do this after we have tried to establish link
1734          * because the symbol error count will increment wildly if there
1735          * is no link.
1736          */
1737         e1000_clear_hw_cntrs(hw);
1738
1739         /* ICH8 No-snoop bits are opposite polarity.
1740          * Set to snoop by default after reset. */
1741         if (hw->mac_type == e1000_ich8lan)
1742                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1743 #endif
1744
1745         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1746                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1747                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1748                 /* Relaxed ordering must be disabled to avoid a parity
1749                  * error crash in a PCI slot. */
1750                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1751                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1752         }
1753
1754         return ret_val;
1755 }
1756
1757 /******************************************************************************
1758  * Configures flow control and link settings.
1759  *
1760  * hw - Struct containing variables accessed by shared code
1761  *
1762  * Determines which flow control settings to use. Calls the apropriate media-
1763  * specific link configuration function. Configures the flow control settings.
1764  * Assuming the adapter has a valid link partner, a valid link should be
1765  * established. Assumes the hardware has previously been reset and the
1766  * transmitter and receiver are not enabled.
1767  *****************************************************************************/
1768 static int
1769 e1000_setup_link(struct eth_device *nic)
1770 {
1771         struct e1000_hw *hw = nic->priv;
1772         uint32_t ctrl_ext;
1773         int32_t ret_val;
1774         uint16_t eeprom_data;
1775
1776         DEBUGFUNC();
1777
1778         /* In the case of the phy reset being blocked, we already have a link.
1779          * We do not have to set it up again. */
1780         if (e1000_check_phy_reset_block(hw))
1781                 return E1000_SUCCESS;
1782
1783         /* Read and store word 0x0F of the EEPROM. This word contains bits
1784          * that determine the hardware's default PAUSE (flow control) mode,
1785          * a bit that determines whether the HW defaults to enabling or
1786          * disabling auto-negotiation, and the direction of the
1787          * SW defined pins. If there is no SW over-ride of the flow
1788          * control setting, then the variable hw->fc will
1789          * be initialized based on a value in the EEPROM.
1790          */
1791         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1792                                 &eeprom_data) < 0) {
1793                 DEBUGOUT("EEPROM Read Error\n");
1794                 return -E1000_ERR_EEPROM;
1795         }
1796
1797         if (hw->fc == e1000_fc_default) {
1798                 switch (hw->mac_type) {
1799                 case e1000_ich8lan:
1800                 case e1000_82573:
1801                 case e1000_82574:
1802                         hw->fc = e1000_fc_full;
1803                         break;
1804                 default:
1805                         ret_val = e1000_read_eeprom(hw,
1806                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1807                         if (ret_val) {
1808                                 DEBUGOUT("EEPROM Read Error\n");
1809                                 return -E1000_ERR_EEPROM;
1810                         }
1811                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1812                                 hw->fc = e1000_fc_none;
1813                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1814                                     EEPROM_WORD0F_ASM_DIR)
1815                                 hw->fc = e1000_fc_tx_pause;
1816                         else
1817                                 hw->fc = e1000_fc_full;
1818                         break;
1819                 }
1820         }
1821
1822         /* We want to save off the original Flow Control configuration just
1823          * in case we get disconnected and then reconnected into a different
1824          * hub or switch with different Flow Control capabilities.
1825          */
1826         if (hw->mac_type == e1000_82542_rev2_0)
1827                 hw->fc &= (~e1000_fc_tx_pause);
1828
1829         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1830                 hw->fc &= (~e1000_fc_rx_pause);
1831
1832         hw->original_fc = hw->fc;
1833
1834         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1835
1836         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1837          * polarity value for the SW controlled pins, and setup the
1838          * Extended Device Control reg with that info.
1839          * This is needed because one of the SW controlled pins is used for
1840          * signal detection.  So this should be done before e1000_setup_pcs_link()
1841          * or e1000_phy_setup() is called.
1842          */
1843         if (hw->mac_type == e1000_82543) {
1844                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1845                             SWDPIO__EXT_SHIFT);
1846                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1847         }
1848
1849         /* Call the necessary subroutine to configure the link. */
1850         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1851             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1852         if (ret_val < 0) {
1853                 return ret_val;
1854         }
1855
1856         /* Initialize the flow control address, type, and PAUSE timer
1857          * registers to their default values.  This is done even if flow
1858          * control is disabled, because it does not hurt anything to
1859          * initialize these registers.
1860          */
1861         DEBUGOUT("Initializing the Flow Control address, type"
1862                         "and timer regs\n");
1863
1864         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1865         if (hw->mac_type != e1000_ich8lan) {
1866                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1867                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1868                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1869         }
1870
1871         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1872
1873         /* Set the flow control receive threshold registers.  Normally,
1874          * these registers will be set to a default threshold that may be
1875          * adjusted later by the driver's runtime code.  However, if the
1876          * ability to transmit pause frames in not enabled, then these
1877          * registers will be set to 0.
1878          */
1879         if (!(hw->fc & e1000_fc_tx_pause)) {
1880                 E1000_WRITE_REG(hw, FCRTL, 0);
1881                 E1000_WRITE_REG(hw, FCRTH, 0);
1882         } else {
1883                 /* We need to set up the Receive Threshold high and low water marks
1884                  * as well as (optionally) enabling the transmission of XON frames.
1885                  */
1886                 if (hw->fc_send_xon) {
1887                         E1000_WRITE_REG(hw, FCRTL,
1888                                         (hw->fc_low_water | E1000_FCRTL_XONE));
1889                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1890                 } else {
1891                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1892                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1893                 }
1894         }
1895         return ret_val;
1896 }
1897
1898 /******************************************************************************
1899  * Sets up link for a fiber based adapter
1900  *
1901  * hw - Struct containing variables accessed by shared code
1902  *
1903  * Manipulates Physical Coding Sublayer functions in order to configure
1904  * link. Assumes the hardware has been previously reset and the transmitter
1905  * and receiver are not enabled.
1906  *****************************************************************************/
1907 static int
1908 e1000_setup_fiber_link(struct eth_device *nic)
1909 {
1910         struct e1000_hw *hw = nic->priv;
1911         uint32_t ctrl;
1912         uint32_t status;
1913         uint32_t txcw = 0;
1914         uint32_t i;
1915         uint32_t signal;
1916         int32_t ret_val;
1917
1918         DEBUGFUNC();
1919         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1920          * set when the optics detect a signal. On older adapters, it will be
1921          * cleared when there is a signal
1922          */
1923         ctrl = E1000_READ_REG(hw, CTRL);
1924         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1925                 signal = E1000_CTRL_SWDPIN1;
1926         else
1927                 signal = 0;
1928
1929         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1930                ctrl);
1931         /* Take the link out of reset */
1932         ctrl &= ~(E1000_CTRL_LRST);
1933
1934         e1000_config_collision_dist(hw);
1935
1936         /* Check for a software override of the flow control settings, and setup
1937          * the device accordingly.  If auto-negotiation is enabled, then software
1938          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1939          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1940          * auto-negotiation is disabled, then software will have to manually
1941          * configure the two flow control enable bits in the CTRL register.
1942          *
1943          * The possible values of the "fc" parameter are:
1944          *      0:  Flow control is completely disabled
1945          *      1:  Rx flow control is enabled (we can receive pause frames, but
1946          *          not send pause frames).
1947          *      2:  Tx flow control is enabled (we can send pause frames but we do
1948          *          not support receiving pause frames).
1949          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1950          */
1951         switch (hw->fc) {
1952         case e1000_fc_none:
1953                 /* Flow control is completely disabled by a software over-ride. */
1954                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1955                 break;
1956         case e1000_fc_rx_pause:
1957                 /* RX Flow control is enabled and TX Flow control is disabled by a
1958                  * software over-ride. Since there really isn't a way to advertise
1959                  * that we are capable of RX Pause ONLY, we will advertise that we
1960                  * support both symmetric and asymmetric RX PAUSE. Later, we will
1961                  *  disable the adapter's ability to send PAUSE frames.
1962                  */
1963                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1964                 break;
1965         case e1000_fc_tx_pause:
1966                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1967                  * software over-ride.
1968                  */
1969                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1970                 break;
1971         case e1000_fc_full:
1972                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1973                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1974                 break;
1975         default:
1976                 DEBUGOUT("Flow control param set incorrectly\n");
1977                 return -E1000_ERR_CONFIG;
1978                 break;
1979         }
1980
1981         /* Since auto-negotiation is enabled, take the link out of reset (the link
1982          * will be in reset, because we previously reset the chip). This will
1983          * restart auto-negotiation.  If auto-neogtiation is successful then the
1984          * link-up status bit will be set and the flow control enable bits (RFCE
1985          * and TFCE) will be set according to their negotiated value.
1986          */
1987         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
1988
1989         E1000_WRITE_REG(hw, TXCW, txcw);
1990         E1000_WRITE_REG(hw, CTRL, ctrl);
1991         E1000_WRITE_FLUSH(hw);
1992
1993         hw->txcw = txcw;
1994         mdelay(1);
1995
1996         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1997          * indication in the Device Status Register.  Time-out if a link isn't
1998          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1999          * less than 500 milliseconds even if the other end is doing it in SW).
2000          */
2001         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2002                 DEBUGOUT("Looking for Link\n");
2003                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2004                         mdelay(10);
2005                         status = E1000_READ_REG(hw, STATUS);
2006                         if (status & E1000_STATUS_LU)
2007                                 break;
2008                 }
2009                 if (i == (LINK_UP_TIMEOUT / 10)) {
2010                         /* AutoNeg failed to achieve a link, so we'll call
2011                          * e1000_check_for_link. This routine will force the link up if we
2012                          * detect a signal. This will allow us to communicate with
2013                          * non-autonegotiating link partners.
2014                          */
2015                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2016                         hw->autoneg_failed = 1;
2017                         ret_val = e1000_check_for_link(nic);
2018                         if (ret_val < 0) {
2019                                 DEBUGOUT("Error while checking for link\n");
2020                                 return ret_val;
2021                         }
2022                         hw->autoneg_failed = 0;
2023                 } else {
2024                         hw->autoneg_failed = 0;
2025                         DEBUGOUT("Valid Link Found\n");
2026                 }
2027         } else {
2028                 DEBUGOUT("No Signal Detected\n");
2029                 return -E1000_ERR_NOLINK;
2030         }
2031         return 0;
2032 }
2033
2034 /******************************************************************************
2035 * Make sure we have a valid PHY and change PHY mode before link setup.
2036 *
2037 * hw - Struct containing variables accessed by shared code
2038 ******************************************************************************/
2039 static int32_t
2040 e1000_copper_link_preconfig(struct e1000_hw *hw)
2041 {
2042         uint32_t ctrl;
2043         int32_t ret_val;
2044         uint16_t phy_data;
2045
2046         DEBUGFUNC();
2047
2048         ctrl = E1000_READ_REG(hw, CTRL);
2049         /* With 82543, we need to force speed and duplex on the MAC equal to what
2050          * the PHY speed and duplex configuration is. In addition, we need to
2051          * perform a hardware reset on the PHY to take it out of reset.
2052          */
2053         if (hw->mac_type > e1000_82543) {
2054                 ctrl |= E1000_CTRL_SLU;
2055                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2056                 E1000_WRITE_REG(hw, CTRL, ctrl);
2057         } else {
2058                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2059                                 | E1000_CTRL_SLU);
2060                 E1000_WRITE_REG(hw, CTRL, ctrl);
2061                 ret_val = e1000_phy_hw_reset(hw);
2062                 if (ret_val)
2063                         return ret_val;
2064         }
2065
2066         /* Make sure we have a valid PHY */
2067         ret_val = e1000_detect_gig_phy(hw);
2068         if (ret_val) {
2069                 DEBUGOUT("Error, did not detect valid phy.\n");
2070                 return ret_val;
2071         }
2072         DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2073
2074         /* Set PHY to class A mode (if necessary) */
2075         ret_val = e1000_set_phy_mode(hw);
2076         if (ret_val)
2077                 return ret_val;
2078         if ((hw->mac_type == e1000_82545_rev_3) ||
2079                 (hw->mac_type == e1000_82546_rev_3)) {
2080                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2081                                 &phy_data);
2082                 phy_data |= 0x00000008;
2083                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2084                                 phy_data);
2085         }
2086
2087         if (hw->mac_type <= e1000_82543 ||
2088                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2089                 hw->mac_type == e1000_82541_rev_2
2090                 || hw->mac_type == e1000_82547_rev_2)
2091                         hw->phy_reset_disable = FALSE;
2092
2093         return E1000_SUCCESS;
2094 }
2095
2096 /*****************************************************************************
2097  *
2098  * This function sets the lplu state according to the active flag.  When
2099  * activating lplu this function also disables smart speed and vise versa.
2100  * lplu will not be activated unless the device autonegotiation advertisment
2101  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2102  * hw: Struct containing variables accessed by shared code
2103  * active - true to enable lplu false to disable lplu.
2104  *
2105  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2106  *            E1000_SUCCESS at any other case.
2107  *
2108  ****************************************************************************/
2109
2110 static int32_t
2111 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2112 {
2113         uint32_t phy_ctrl = 0;
2114         int32_t ret_val;
2115         uint16_t phy_data;
2116         DEBUGFUNC();
2117
2118         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2119             && hw->phy_type != e1000_phy_igp_3)
2120                 return E1000_SUCCESS;
2121
2122         /* During driver activity LPLU should not be used or it will attain link
2123          * from the lowest speeds starting from 10Mbps. The capability is used
2124          * for Dx transitions and states */
2125         if (hw->mac_type == e1000_82541_rev_2
2126                         || hw->mac_type == e1000_82547_rev_2) {
2127                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2128                                 &phy_data);
2129                 if (ret_val)
2130                         return ret_val;
2131         } else if (hw->mac_type == e1000_ich8lan) {
2132                 /* MAC writes into PHY register based on the state transition
2133                  * and start auto-negotiation. SW driver can overwrite the
2134                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2135                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2136         } else {
2137                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2138                                 &phy_data);
2139                 if (ret_val)
2140                         return ret_val;
2141         }
2142
2143         if (!active) {
2144                 if (hw->mac_type == e1000_82541_rev_2 ||
2145                         hw->mac_type == e1000_82547_rev_2) {
2146                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2147                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2148                                         phy_data);
2149                         if (ret_val)
2150                                 return ret_val;
2151                 } else {
2152                         if (hw->mac_type == e1000_ich8lan) {
2153                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2154                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2155                         } else {
2156                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2157                                 ret_val = e1000_write_phy_reg(hw,
2158                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2159                                 if (ret_val)
2160                                         return ret_val;
2161                         }
2162                 }
2163
2164         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2165          * Dx states where the power conservation is most important.  During
2166          * driver activity we should enable SmartSpeed, so performance is
2167          * maintained. */
2168                 if (hw->smart_speed == e1000_smart_speed_on) {
2169                         ret_val = e1000_read_phy_reg(hw,
2170                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2171                         if (ret_val)
2172                                 return ret_val;
2173
2174                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2175                         ret_val = e1000_write_phy_reg(hw,
2176                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2177                         if (ret_val)
2178                                 return ret_val;
2179                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2180                         ret_val = e1000_read_phy_reg(hw,
2181                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2182                         if (ret_val)
2183                                 return ret_val;
2184
2185                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2186                         ret_val = e1000_write_phy_reg(hw,
2187                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2188                         if (ret_val)
2189                                 return ret_val;
2190                 }
2191
2192         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2193                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2194                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2195
2196                 if (hw->mac_type == e1000_82541_rev_2 ||
2197                     hw->mac_type == e1000_82547_rev_2) {
2198                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2199                         ret_val = e1000_write_phy_reg(hw,
2200                                         IGP01E1000_GMII_FIFO, phy_data);
2201                         if (ret_val)
2202                                 return ret_val;
2203                 } else {
2204                         if (hw->mac_type == e1000_ich8lan) {
2205                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2206                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2207                         } else {
2208                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2209                                 ret_val = e1000_write_phy_reg(hw,
2210                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2211                                 if (ret_val)
2212                                         return ret_val;
2213                         }
2214                 }
2215
2216                 /* When LPLU is enabled we should disable SmartSpeed */
2217                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2218                                 &phy_data);
2219                 if (ret_val)
2220                         return ret_val;
2221
2222                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2223                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2224                                 phy_data);
2225                 if (ret_val)
2226                         return ret_val;
2227         }
2228         return E1000_SUCCESS;
2229 }
2230
2231 /*****************************************************************************
2232  *
2233  * This function sets the lplu d0 state according to the active flag.  When
2234  * activating lplu this function also disables smart speed and vise versa.
2235  * lplu will not be activated unless the device autonegotiation advertisment
2236  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2237  * hw: Struct containing variables accessed by shared code
2238  * active - true to enable lplu false to disable lplu.
2239  *
2240  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2241  *            E1000_SUCCESS at any other case.
2242  *
2243  ****************************************************************************/
2244
2245 static int32_t
2246 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2247 {
2248         uint32_t phy_ctrl = 0;
2249         int32_t ret_val;
2250         uint16_t phy_data;
2251         DEBUGFUNC();
2252
2253         if (hw->mac_type <= e1000_82547_rev_2)
2254                 return E1000_SUCCESS;
2255
2256         if (hw->mac_type == e1000_ich8lan) {
2257                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2258         } else {
2259                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2260                                 &phy_data);
2261                 if (ret_val)
2262                         return ret_val;
2263         }
2264
2265         if (!active) {
2266                 if (hw->mac_type == e1000_ich8lan) {
2267                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2268                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2269                 } else {
2270                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2271                         ret_val = e1000_write_phy_reg(hw,
2272                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2273                         if (ret_val)
2274                                 return ret_val;
2275                 }
2276
2277         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2278          * Dx states where the power conservation is most important.  During
2279          * driver activity we should enable SmartSpeed, so performance is
2280          * maintained. */
2281                 if (hw->smart_speed == e1000_smart_speed_on) {
2282                         ret_val = e1000_read_phy_reg(hw,
2283                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2284                         if (ret_val)
2285                                 return ret_val;
2286
2287                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2288                         ret_val = e1000_write_phy_reg(hw,
2289                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2290                         if (ret_val)
2291                                 return ret_val;
2292                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2293                         ret_val = e1000_read_phy_reg(hw,
2294                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2295                         if (ret_val)
2296                                 return ret_val;
2297
2298                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2299                         ret_val = e1000_write_phy_reg(hw,
2300                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2301                         if (ret_val)
2302                                 return ret_val;
2303                 }
2304
2305
2306         } else {
2307
2308                 if (hw->mac_type == e1000_ich8lan) {
2309                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2310                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2311                 } else {
2312                         phy_data |= IGP02E1000_PM_D0_LPLU;
2313                         ret_val = e1000_write_phy_reg(hw,
2314                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2315                         if (ret_val)
2316                                 return ret_val;
2317                 }
2318
2319                 /* When LPLU is enabled we should disable SmartSpeed */
2320                 ret_val = e1000_read_phy_reg(hw,
2321                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2322                 if (ret_val)
2323                         return ret_val;
2324
2325                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2326                 ret_val = e1000_write_phy_reg(hw,
2327                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2328                 if (ret_val)
2329                         return ret_val;
2330
2331         }
2332         return E1000_SUCCESS;
2333 }
2334
2335 /********************************************************************
2336 * Copper link setup for e1000_phy_igp series.
2337 *
2338 * hw - Struct containing variables accessed by shared code
2339 *********************************************************************/
2340 static int32_t
2341 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2342 {
2343         uint32_t led_ctrl;
2344         int32_t ret_val;
2345         uint16_t phy_data;
2346
2347         DEBUGFUNC();
2348
2349         if (hw->phy_reset_disable)
2350                 return E1000_SUCCESS;
2351
2352         ret_val = e1000_phy_reset(hw);
2353         if (ret_val) {
2354                 DEBUGOUT("Error Resetting the PHY\n");
2355                 return ret_val;
2356         }
2357
2358         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2359         mdelay(15);
2360         if (hw->mac_type != e1000_ich8lan) {
2361                 /* Configure activity LED after PHY reset */
2362                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2363                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2364                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2365                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2366         }
2367
2368         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2369         if (hw->phy_type == e1000_phy_igp) {
2370                 /* disable lplu d3 during driver init */
2371                 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2372                 if (ret_val) {
2373                         DEBUGOUT("Error Disabling LPLU D3\n");
2374                         return ret_val;
2375                 }
2376         }
2377
2378         /* disable lplu d0 during driver init */
2379         ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2380         if (ret_val) {
2381                 DEBUGOUT("Error Disabling LPLU D0\n");
2382                 return ret_val;
2383         }
2384         /* Configure mdi-mdix settings */
2385         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2386         if (ret_val)
2387                 return ret_val;
2388
2389         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2390                 hw->dsp_config_state = e1000_dsp_config_disabled;
2391                 /* Force MDI for earlier revs of the IGP PHY */
2392                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2393                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2394                 hw->mdix = 1;
2395
2396         } else {
2397                 hw->dsp_config_state = e1000_dsp_config_enabled;
2398                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2399
2400                 switch (hw->mdix) {
2401                 case 1:
2402                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2403                         break;
2404                 case 2:
2405                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2406                         break;
2407                 case 0:
2408                 default:
2409                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2410                         break;
2411                 }
2412         }
2413         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2414         if (ret_val)
2415                 return ret_val;
2416
2417         /* set auto-master slave resolution settings */
2418         if (hw->autoneg) {
2419                 e1000_ms_type phy_ms_setting = hw->master_slave;
2420
2421                 if (hw->ffe_config_state == e1000_ffe_config_active)
2422                         hw->ffe_config_state = e1000_ffe_config_enabled;
2423
2424                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2425                         hw->dsp_config_state = e1000_dsp_config_enabled;
2426
2427                 /* when autonegotiation advertisment is only 1000Mbps then we
2428                   * should disable SmartSpeed and enable Auto MasterSlave
2429                   * resolution as hardware default. */
2430                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2431                         /* Disable SmartSpeed */
2432                         ret_val = e1000_read_phy_reg(hw,
2433                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2434                         if (ret_val)
2435                                 return ret_val;
2436                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2437                         ret_val = e1000_write_phy_reg(hw,
2438                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2439                         if (ret_val)
2440                                 return ret_val;
2441                         /* Set auto Master/Slave resolution process */
2442                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2443                                         &phy_data);
2444                         if (ret_val)
2445                                 return ret_val;
2446                         phy_data &= ~CR_1000T_MS_ENABLE;
2447                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2448                                         phy_data);
2449                         if (ret_val)
2450                                 return ret_val;
2451                 }
2452
2453                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2454                 if (ret_val)
2455                         return ret_val;
2456
2457                 /* load defaults for future use */
2458                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2459                                 ((phy_data & CR_1000T_MS_VALUE) ?
2460                                 e1000_ms_force_master :
2461                                 e1000_ms_force_slave) :
2462                                 e1000_ms_auto;
2463
2464                 switch (phy_ms_setting) {
2465                 case e1000_ms_force_master:
2466                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2467                         break;
2468                 case e1000_ms_force_slave:
2469                         phy_data |= CR_1000T_MS_ENABLE;
2470                         phy_data &= ~(CR_1000T_MS_VALUE);
2471                         break;
2472                 case e1000_ms_auto:
2473                         phy_data &= ~CR_1000T_MS_ENABLE;
2474                 default:
2475                         break;
2476                 }
2477                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2478                 if (ret_val)
2479                         return ret_val;
2480         }
2481
2482         return E1000_SUCCESS;
2483 }
2484
2485 /*****************************************************************************
2486  * This function checks the mode of the firmware.
2487  *
2488  * returns  - TRUE when the mode is IAMT or FALSE.
2489  ****************************************************************************/
2490 boolean_t
2491 e1000_check_mng_mode(struct e1000_hw *hw)
2492 {
2493         uint32_t fwsm;
2494         DEBUGFUNC();
2495
2496         fwsm = E1000_READ_REG(hw, FWSM);
2497
2498         if (hw->mac_type == e1000_ich8lan) {
2499                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2500                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2501                         return TRUE;
2502         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2503                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2504                         return TRUE;
2505
2506         return FALSE;
2507 }
2508
2509 static int32_t
2510 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2511 {
2512         uint16_t swfw = E1000_SWFW_PHY0_SM;
2513         uint32_t reg_val;
2514         DEBUGFUNC();
2515
2516         if (e1000_is_second_port(hw))
2517                 swfw = E1000_SWFW_PHY1_SM;
2518
2519         if (e1000_swfw_sync_acquire(hw, swfw))
2520                 return -E1000_ERR_SWFW_SYNC;
2521
2522         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2523                         & E1000_KUMCTRLSTA_OFFSET) | data;
2524         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2525         udelay(2);
2526
2527         return E1000_SUCCESS;
2528 }
2529
2530 static int32_t
2531 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2532 {
2533         uint16_t swfw = E1000_SWFW_PHY0_SM;
2534         uint32_t reg_val;
2535         DEBUGFUNC();
2536
2537         if (e1000_is_second_port(hw))
2538                 swfw = E1000_SWFW_PHY1_SM;
2539
2540         if (e1000_swfw_sync_acquire(hw, swfw))
2541                 return -E1000_ERR_SWFW_SYNC;
2542
2543         /* Write register address */
2544         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2545                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2546         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2547         udelay(2);
2548
2549         /* Read the data returned */
2550         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2551         *data = (uint16_t)reg_val;
2552
2553         return E1000_SUCCESS;
2554 }
2555
2556 /********************************************************************
2557 * Copper link setup for e1000_phy_gg82563 series.
2558 *
2559 * hw - Struct containing variables accessed by shared code
2560 *********************************************************************/
2561 static int32_t
2562 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2563 {
2564         int32_t ret_val;
2565         uint16_t phy_data;
2566         uint32_t reg_data;
2567
2568         DEBUGFUNC();
2569
2570         if (!hw->phy_reset_disable) {
2571                 /* Enable CRS on TX for half-duplex operation. */
2572                 ret_val = e1000_read_phy_reg(hw,
2573                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2574                 if (ret_val)
2575                         return ret_val;
2576
2577                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2578                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2579                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2580
2581                 ret_val = e1000_write_phy_reg(hw,
2582                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2583                 if (ret_val)
2584                         return ret_val;
2585
2586                 /* Options:
2587                  *   MDI/MDI-X = 0 (default)
2588                  *   0 - Auto for all speeds
2589                  *   1 - MDI mode
2590                  *   2 - MDI-X mode
2591                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2592                  */
2593                 ret_val = e1000_read_phy_reg(hw,
2594                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2595                 if (ret_val)
2596                         return ret_val;
2597
2598                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2599
2600                 switch (hw->mdix) {
2601                 case 1:
2602                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2603                         break;
2604                 case 2:
2605                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2606                         break;
2607                 case 0:
2608                 default:
2609                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2610                         break;
2611                 }
2612
2613                 /* Options:
2614                  *   disable_polarity_correction = 0 (default)
2615                  *       Automatic Correction for Reversed Cable Polarity
2616                  *   0 - Disabled
2617                  *   1 - Enabled
2618                  */
2619                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2620                 ret_val = e1000_write_phy_reg(hw,
2621                                 GG82563_PHY_SPEC_CTRL, phy_data);
2622
2623                 if (ret_val)
2624                         return ret_val;
2625
2626                 /* SW Reset the PHY so all changes take effect */
2627                 ret_val = e1000_phy_reset(hw);
2628                 if (ret_val) {
2629                         DEBUGOUT("Error Resetting the PHY\n");
2630                         return ret_val;
2631                 }
2632         } /* phy_reset_disable */
2633
2634         if (hw->mac_type == e1000_80003es2lan) {
2635                 /* Bypass RX and TX FIFO's */
2636                 ret_val = e1000_write_kmrn_reg(hw,
2637                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2638                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2639                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2640                 if (ret_val)
2641                         return ret_val;
2642
2643                 ret_val = e1000_read_phy_reg(hw,
2644                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2645                 if (ret_val)
2646                         return ret_val;
2647
2648                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2649                 ret_val = e1000_write_phy_reg(hw,
2650                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2651
2652                 if (ret_val)
2653                         return ret_val;
2654
2655                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2656                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2657                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2658
2659                 ret_val = e1000_read_phy_reg(hw,
2660                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2661                 if (ret_val)
2662                         return ret_val;
2663
2664         /* Do not init these registers when the HW is in IAMT mode, since the
2665          * firmware will have already initialized them.  We only initialize
2666          * them if the HW is not in IAMT mode.
2667          */
2668                 if (e1000_check_mng_mode(hw) == FALSE) {
2669                         /* Enable Electrical Idle on the PHY */
2670                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2671                         ret_val = e1000_write_phy_reg(hw,
2672                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2673                         if (ret_val)
2674                                 return ret_val;
2675
2676                         ret_val = e1000_read_phy_reg(hw,
2677                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2678                         if (ret_val)
2679                                 return ret_val;
2680
2681                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2682                         ret_val = e1000_write_phy_reg(hw,
2683                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2684
2685                         if (ret_val)
2686                                 return ret_val;
2687                 }
2688
2689                 /* Workaround: Disable padding in Kumeran interface in the MAC
2690                  * and in the PHY to avoid CRC errors.
2691                  */
2692                 ret_val = e1000_read_phy_reg(hw,
2693                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2694                 if (ret_val)
2695                         return ret_val;
2696                 phy_data |= GG82563_ICR_DIS_PADDING;
2697                 ret_val = e1000_write_phy_reg(hw,
2698                                 GG82563_PHY_INBAND_CTRL, phy_data);
2699                 if (ret_val)
2700                         return ret_val;
2701         }
2702         return E1000_SUCCESS;
2703 }
2704
2705 /********************************************************************
2706 * Copper link setup for e1000_phy_m88 series.
2707 *
2708 * hw - Struct containing variables accessed by shared code
2709 *********************************************************************/
2710 static int32_t
2711 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2712 {
2713         int32_t ret_val;
2714         uint16_t phy_data;
2715
2716         DEBUGFUNC();
2717
2718         if (hw->phy_reset_disable)
2719                 return E1000_SUCCESS;
2720
2721         /* Enable CRS on TX. This must be set for half-duplex operation. */
2722         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2723         if (ret_val)
2724                 return ret_val;
2725
2726         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2727
2728         /* Options:
2729          *   MDI/MDI-X = 0 (default)
2730          *   0 - Auto for all speeds
2731          *   1 - MDI mode
2732          *   2 - MDI-X mode
2733          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2734          */
2735         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2736
2737         switch (hw->mdix) {
2738         case 1:
2739                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2740                 break;
2741         case 2:
2742                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2743                 break;
2744         case 3:
2745                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2746                 break;
2747         case 0:
2748         default:
2749                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2750                 break;
2751         }
2752
2753         /* Options:
2754          *   disable_polarity_correction = 0 (default)
2755          *       Automatic Correction for Reversed Cable Polarity
2756          *   0 - Disabled
2757          *   1 - Enabled
2758          */
2759         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2760         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2761         if (ret_val)
2762                 return ret_val;
2763
2764         if (hw->phy_revision < M88E1011_I_REV_4) {
2765                 /* Force TX_CLK in the Extended PHY Specific Control Register
2766                  * to 25MHz clock.
2767                  */
2768                 ret_val = e1000_read_phy_reg(hw,
2769                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2770                 if (ret_val)
2771                         return ret_val;
2772
2773                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2774
2775                 if ((hw->phy_revision == E1000_REVISION_2) &&
2776                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2777                         /* Vidalia Phy, set the downshift counter to 5x */
2778                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2779                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2780                         ret_val = e1000_write_phy_reg(hw,
2781                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2782                         if (ret_val)
2783                                 return ret_val;
2784                 } else {
2785                         /* Configure Master and Slave downshift values */
2786                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2787                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2788                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2789                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2790                         ret_val = e1000_write_phy_reg(hw,
2791                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2792                         if (ret_val)
2793                                 return ret_val;
2794                 }
2795         }
2796
2797         /* SW Reset the PHY so all changes take effect */
2798         ret_val = e1000_phy_reset(hw);
2799         if (ret_val) {
2800                 DEBUGOUT("Error Resetting the PHY\n");
2801                 return ret_val;
2802         }
2803
2804         return E1000_SUCCESS;
2805 }
2806
2807 /********************************************************************
2808 * Setup auto-negotiation and flow control advertisements,
2809 * and then perform auto-negotiation.
2810 *
2811 * hw - Struct containing variables accessed by shared code
2812 *********************************************************************/
2813 static int32_t
2814 e1000_copper_link_autoneg(struct e1000_hw *hw)
2815 {
2816         int32_t ret_val;
2817         uint16_t phy_data;
2818
2819         DEBUGFUNC();
2820
2821         /* Perform some bounds checking on the hw->autoneg_advertised
2822          * parameter.  If this variable is zero, then set it to the default.
2823          */
2824         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2825
2826         /* If autoneg_advertised is zero, we assume it was not defaulted
2827          * by the calling code so we set to advertise full capability.
2828          */
2829         if (hw->autoneg_advertised == 0)
2830                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2831
2832         /* IFE phy only supports 10/100 */
2833         if (hw->phy_type == e1000_phy_ife)
2834                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2835
2836         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2837         ret_val = e1000_phy_setup_autoneg(hw);
2838         if (ret_val) {
2839                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2840                 return ret_val;
2841         }
2842         DEBUGOUT("Restarting Auto-Neg\n");
2843
2844         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2845          * the Auto Neg Restart bit in the PHY control register.
2846          */
2847         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2848         if (ret_val)
2849                 return ret_val;
2850
2851         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2852         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2853         if (ret_val)
2854                 return ret_val;
2855
2856         /* Does the user want to wait for Auto-Neg to complete here, or
2857          * check at a later time (for example, callback routine).
2858          */
2859         /* If we do not wait for autonegtation to complete I
2860          * do not see a valid link status.
2861          * wait_autoneg_complete = 1 .
2862          */
2863         if (hw->wait_autoneg_complete) {
2864                 ret_val = e1000_wait_autoneg(hw);
2865                 if (ret_val) {
2866                         DEBUGOUT("Error while waiting for autoneg"
2867                                         "to complete\n");
2868                         return ret_val;
2869                 }
2870         }
2871
2872         hw->get_link_status = TRUE;
2873
2874         return E1000_SUCCESS;
2875 }
2876
2877 /******************************************************************************
2878 * Config the MAC and the PHY after link is up.
2879 *   1) Set up the MAC to the current PHY speed/duplex
2880 *      if we are on 82543.  If we
2881 *      are on newer silicon, we only need to configure
2882 *      collision distance in the Transmit Control Register.
2883 *   2) Set up flow control on the MAC to that established with
2884 *      the link partner.
2885 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
2886 *
2887 * hw - Struct containing variables accessed by shared code
2888 ******************************************************************************/
2889 static int32_t
2890 e1000_copper_link_postconfig(struct e1000_hw *hw)
2891 {
2892         int32_t ret_val;
2893         DEBUGFUNC();
2894
2895         if (hw->mac_type >= e1000_82544) {
2896                 e1000_config_collision_dist(hw);
2897         } else {
2898                 ret_val = e1000_config_mac_to_phy(hw);
2899                 if (ret_val) {
2900                         DEBUGOUT("Error configuring MAC to PHY settings\n");
2901                         return ret_val;
2902                 }
2903         }
2904         ret_val = e1000_config_fc_after_link_up(hw);
2905         if (ret_val) {
2906                 DEBUGOUT("Error Configuring Flow Control\n");
2907                 return ret_val;
2908         }
2909         return E1000_SUCCESS;
2910 }
2911
2912 /******************************************************************************
2913 * Detects which PHY is present and setup the speed and duplex
2914 *
2915 * hw - Struct containing variables accessed by shared code
2916 ******************************************************************************/
2917 static int
2918 e1000_setup_copper_link(struct eth_device *nic)
2919 {
2920         struct e1000_hw *hw = nic->priv;
2921         int32_t ret_val;
2922         uint16_t i;
2923         uint16_t phy_data;
2924         uint16_t reg_data;
2925
2926         DEBUGFUNC();
2927
2928         switch (hw->mac_type) {
2929         case e1000_80003es2lan:
2930         case e1000_ich8lan:
2931                 /* Set the mac to wait the maximum time between each
2932                  * iteration and increase the max iterations when
2933                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2934                 ret_val = e1000_write_kmrn_reg(hw,
2935                                 GG82563_REG(0x34, 4), 0xFFFF);
2936                 if (ret_val)
2937                         return ret_val;
2938                 ret_val = e1000_read_kmrn_reg(hw,
2939                                 GG82563_REG(0x34, 9), &reg_data);
2940                 if (ret_val)
2941                         return ret_val;
2942                 reg_data |= 0x3F;
2943                 ret_val = e1000_write_kmrn_reg(hw,
2944                                 GG82563_REG(0x34, 9), reg_data);
2945                 if (ret_val)
2946                         return ret_val;
2947         default:
2948                 break;
2949         }
2950
2951         /* Check if it is a valid PHY and set PHY mode if necessary. */
2952         ret_val = e1000_copper_link_preconfig(hw);
2953         if (ret_val)
2954                 return ret_val;
2955         switch (hw->mac_type) {
2956         case e1000_80003es2lan:
2957                 /* Kumeran registers are written-only */
2958                 reg_data =
2959                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2960                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2961                 ret_val = e1000_write_kmrn_reg(hw,
2962                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
2963                 if (ret_val)
2964                         return ret_val;
2965                 break;
2966         default:
2967                 break;
2968         }
2969
2970         if (hw->phy_type == e1000_phy_igp ||
2971                 hw->phy_type == e1000_phy_igp_3 ||
2972                 hw->phy_type == e1000_phy_igp_2) {
2973                 ret_val = e1000_copper_link_igp_setup(hw);
2974                 if (ret_val)
2975                         return ret_val;
2976         } else if (hw->phy_type == e1000_phy_m88) {
2977                 ret_val = e1000_copper_link_mgp_setup(hw);
2978                 if (ret_val)
2979                         return ret_val;
2980         } else if (hw->phy_type == e1000_phy_gg82563) {
2981                 ret_val = e1000_copper_link_ggp_setup(hw);
2982                 if (ret_val)
2983                         return ret_val;
2984         }
2985
2986         /* always auto */
2987         /* Setup autoneg and flow control advertisement
2988           * and perform autonegotiation */
2989         ret_val = e1000_copper_link_autoneg(hw);
2990         if (ret_val)
2991                 return ret_val;
2992
2993         /* Check link status. Wait up to 100 microseconds for link to become
2994          * valid.
2995          */
2996         for (i = 0; i < 10; i++) {
2997                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2998                 if (ret_val)
2999                         return ret_val;
3000                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3001                 if (ret_val)
3002                         return ret_val;
3003
3004                 if (phy_data & MII_SR_LINK_STATUS) {
3005                         /* Config the MAC and PHY after link is up */
3006                         ret_val = e1000_copper_link_postconfig(hw);
3007                         if (ret_val)
3008                                 return ret_val;
3009
3010                         DEBUGOUT("Valid link established!!!\n");
3011                         return E1000_SUCCESS;
3012                 }
3013                 udelay(10);
3014         }
3015
3016         DEBUGOUT("Unable to establish link!!!\n");
3017         return E1000_SUCCESS;
3018 }
3019
3020 /******************************************************************************
3021 * Configures PHY autoneg and flow control advertisement settings
3022 *
3023 * hw - Struct containing variables accessed by shared code
3024 ******************************************************************************/
3025 int32_t
3026 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3027 {
3028         int32_t ret_val;
3029         uint16_t mii_autoneg_adv_reg;
3030         uint16_t mii_1000t_ctrl_reg;
3031
3032         DEBUGFUNC();
3033
3034         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3035         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3036         if (ret_val)
3037                 return ret_val;
3038
3039         if (hw->phy_type != e1000_phy_ife) {
3040                 /* Read the MII 1000Base-T Control Register (Address 9). */
3041                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3042                                 &mii_1000t_ctrl_reg);
3043                 if (ret_val)
3044                         return ret_val;
3045         } else
3046                 mii_1000t_ctrl_reg = 0;
3047
3048         /* Need to parse both autoneg_advertised and fc and set up
3049          * the appropriate PHY registers.  First we will parse for
3050          * autoneg_advertised software override.  Since we can advertise
3051          * a plethora of combinations, we need to check each bit
3052          * individually.
3053          */
3054
3055         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3056          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3057          * the  1000Base-T Control Register (Address 9).
3058          */
3059         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3060         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3061
3062         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3063
3064         /* Do we want to advertise 10 Mb Half Duplex? */
3065         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3066                 DEBUGOUT("Advertise 10mb Half duplex\n");
3067                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3068         }
3069
3070         /* Do we want to advertise 10 Mb Full Duplex? */
3071         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3072                 DEBUGOUT("Advertise 10mb Full duplex\n");
3073                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3074         }
3075
3076         /* Do we want to advertise 100 Mb Half Duplex? */
3077         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3078                 DEBUGOUT("Advertise 100mb Half duplex\n");
3079                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3080         }
3081
3082         /* Do we want to advertise 100 Mb Full Duplex? */
3083         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3084                 DEBUGOUT("Advertise 100mb Full duplex\n");
3085                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3086         }
3087
3088         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3089         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3090                 DEBUGOUT
3091                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3092         }
3093
3094         /* Do we want to advertise 1000 Mb Full Duplex? */
3095         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3096                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3097                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3098         }
3099
3100         /* Check for a software override of the flow control settings, and
3101          * setup the PHY advertisement registers accordingly.  If
3102          * auto-negotiation is enabled, then software will have to set the
3103          * "PAUSE" bits to the correct value in the Auto-Negotiation
3104          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3105          *
3106          * The possible values of the "fc" parameter are:
3107          *      0:  Flow control is completely disabled
3108          *      1:  Rx flow control is enabled (we can receive pause frames
3109          *          but not send pause frames).
3110          *      2:  Tx flow control is enabled (we can send pause frames
3111          *          but we do not support receiving pause frames).
3112          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3113          *  other:  No software override.  The flow control configuration
3114          *          in the EEPROM is used.
3115          */
3116         switch (hw->fc) {
3117         case e1000_fc_none:     /* 0 */
3118                 /* Flow control (RX & TX) is completely disabled by a
3119                  * software over-ride.
3120                  */
3121                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3122                 break;
3123         case e1000_fc_rx_pause: /* 1 */
3124                 /* RX Flow control is enabled, and TX Flow control is
3125                  * disabled, by a software over-ride.
3126                  */
3127                 /* Since there really isn't a way to advertise that we are
3128                  * capable of RX Pause ONLY, we will advertise that we
3129                  * support both symmetric and asymmetric RX PAUSE.  Later
3130                  * (in e1000_config_fc_after_link_up) we will disable the
3131                  *hw's ability to send PAUSE frames.
3132                  */
3133                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3134                 break;
3135         case e1000_fc_tx_pause: /* 2 */
3136                 /* TX Flow control is enabled, and RX Flow control is
3137                  * disabled, by a software over-ride.
3138                  */
3139                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3140                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3141                 break;
3142         case e1000_fc_full:     /* 3 */
3143                 /* Flow control (both RX and TX) is enabled by a software
3144                  * over-ride.
3145                  */
3146                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3147                 break;
3148         default:
3149                 DEBUGOUT("Flow control param set incorrectly\n");
3150                 return -E1000_ERR_CONFIG;
3151         }
3152
3153         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3154         if (ret_val)
3155                 return ret_val;
3156
3157         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3158
3159         if (hw->phy_type != e1000_phy_ife) {
3160                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3161                                 mii_1000t_ctrl_reg);
3162                 if (ret_val)
3163                         return ret_val;
3164         }
3165
3166         return E1000_SUCCESS;
3167 }
3168
3169 /******************************************************************************
3170 * Sets the collision distance in the Transmit Control register
3171 *
3172 * hw - Struct containing variables accessed by shared code
3173 *
3174 * Link should have been established previously. Reads the speed and duplex
3175 * information from the Device Status register.
3176 ******************************************************************************/
3177 static void
3178 e1000_config_collision_dist(struct e1000_hw *hw)
3179 {
3180         uint32_t tctl, coll_dist;
3181
3182         DEBUGFUNC();
3183
3184         if (hw->mac_type < e1000_82543)
3185                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3186         else
3187                 coll_dist = E1000_COLLISION_DISTANCE;
3188
3189         tctl = E1000_READ_REG(hw, TCTL);
3190
3191         tctl &= ~E1000_TCTL_COLD;
3192         tctl |= coll_dist << E1000_COLD_SHIFT;
3193
3194         E1000_WRITE_REG(hw, TCTL, tctl);
3195         E1000_WRITE_FLUSH(hw);
3196 }
3197
3198 /******************************************************************************
3199 * Sets MAC speed and duplex settings to reflect the those in the PHY
3200 *
3201 * hw - Struct containing variables accessed by shared code
3202 * mii_reg - data to write to the MII control register
3203 *
3204 * The contents of the PHY register containing the needed information need to
3205 * be passed in.
3206 ******************************************************************************/
3207 static int
3208 e1000_config_mac_to_phy(struct e1000_hw *hw)
3209 {
3210         uint32_t ctrl;
3211         uint16_t phy_data;
3212
3213         DEBUGFUNC();
3214
3215         /* Read the Device Control Register and set the bits to Force Speed
3216          * and Duplex.
3217          */
3218         ctrl = E1000_READ_REG(hw, CTRL);
3219         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3220         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3221
3222         /* Set up duplex in the Device Control and Transmit Control
3223          * registers depending on negotiated values.
3224          */
3225         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3226                 DEBUGOUT("PHY Read Error\n");
3227                 return -E1000_ERR_PHY;
3228         }
3229         if (phy_data & M88E1000_PSSR_DPLX)
3230                 ctrl |= E1000_CTRL_FD;
3231         else
3232                 ctrl &= ~E1000_CTRL_FD;
3233
3234         e1000_config_collision_dist(hw);
3235
3236         /* Set up speed in the Device Control register depending on
3237          * negotiated values.
3238          */
3239         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3240                 ctrl |= E1000_CTRL_SPD_1000;
3241         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3242                 ctrl |= E1000_CTRL_SPD_100;
3243         /* Write the configured values back to the Device Control Reg. */
3244         E1000_WRITE_REG(hw, CTRL, ctrl);
3245         return 0;
3246 }
3247
3248 /******************************************************************************
3249  * Forces the MAC's flow control settings.
3250  *
3251  * hw - Struct containing variables accessed by shared code
3252  *
3253  * Sets the TFCE and RFCE bits in the device control register to reflect
3254  * the adapter settings. TFCE and RFCE need to be explicitly set by
3255  * software when a Copper PHY is used because autonegotiation is managed
3256  * by the PHY rather than the MAC. Software must also configure these
3257  * bits when link is forced on a fiber connection.
3258  *****************************************************************************/
3259 static int
3260 e1000_force_mac_fc(struct e1000_hw *hw)
3261 {
3262         uint32_t ctrl;
3263
3264         DEBUGFUNC();
3265
3266         /* Get the current configuration of the Device Control Register */
3267         ctrl = E1000_READ_REG(hw, CTRL);
3268
3269         /* Because we didn't get link via the internal auto-negotiation
3270          * mechanism (we either forced link or we got link via PHY
3271          * auto-neg), we have to manually enable/disable transmit an
3272          * receive flow control.
3273          *
3274          * The "Case" statement below enables/disable flow control
3275          * according to the "hw->fc" parameter.
3276          *
3277          * The possible values of the "fc" parameter are:
3278          *      0:  Flow control is completely disabled
3279          *      1:  Rx flow control is enabled (we can receive pause
3280          *          frames but not send pause frames).
3281          *      2:  Tx flow control is enabled (we can send pause frames
3282          *          frames but we do not receive pause frames).
3283          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3284          *  other:  No other values should be possible at this point.
3285          */
3286
3287         switch (hw->fc) {
3288         case e1000_fc_none:
3289                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3290                 break;
3291         case e1000_fc_rx_pause:
3292                 ctrl &= (~E1000_CTRL_TFCE);
3293                 ctrl |= E1000_CTRL_RFCE;
3294                 break;
3295         case e1000_fc_tx_pause:
3296                 ctrl &= (~E1000_CTRL_RFCE);
3297                 ctrl |= E1000_CTRL_TFCE;
3298                 break;
3299         case e1000_fc_full:
3300                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3301                 break;
3302         default:
3303                 DEBUGOUT("Flow control param set incorrectly\n");
3304                 return -E1000_ERR_CONFIG;
3305         }
3306
3307         /* Disable TX Flow Control for 82542 (rev 2.0) */
3308         if (hw->mac_type == e1000_82542_rev2_0)
3309                 ctrl &= (~E1000_CTRL_TFCE);
3310
3311         E1000_WRITE_REG(hw, CTRL, ctrl);
3312         return 0;
3313 }
3314
3315 /******************************************************************************
3316  * Configures flow control settings after link is established
3317  *
3318  * hw - Struct containing variables accessed by shared code
3319  *
3320  * Should be called immediately after a valid link has been established.
3321  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3322  * and autonegotiation is enabled, the MAC flow control settings will be set
3323  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3324  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3325  *****************************************************************************/
3326 static int32_t
3327 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3328 {
3329         int32_t ret_val;
3330         uint16_t mii_status_reg;
3331         uint16_t mii_nway_adv_reg;
3332         uint16_t mii_nway_lp_ability_reg;
3333         uint16_t speed;
3334         uint16_t duplex;
3335
3336         DEBUGFUNC();
3337
3338         /* Check for the case where we have fiber media and auto-neg failed
3339          * so we had to force link.  In this case, we need to force the
3340          * configuration of the MAC to match the "fc" parameter.
3341          */
3342         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3343                 || ((hw->media_type == e1000_media_type_internal_serdes)
3344                 && (hw->autoneg_failed))
3345                 || ((hw->media_type == e1000_media_type_copper)
3346                 && (!hw->autoneg))) {
3347                 ret_val = e1000_force_mac_fc(hw);
3348                 if (ret_val < 0) {
3349                         DEBUGOUT("Error forcing flow control settings\n");
3350                         return ret_val;
3351                 }
3352         }
3353
3354         /* Check for the case where we have copper media and auto-neg is
3355          * enabled.  In this case, we need to check and see if Auto-Neg
3356          * has completed, and if so, how the PHY and link partner has
3357          * flow control configured.
3358          */
3359         if (hw->media_type == e1000_media_type_copper) {
3360                 /* Read the MII Status Register and check to see if AutoNeg
3361                  * has completed.  We read this twice because this reg has
3362                  * some "sticky" (latched) bits.
3363                  */
3364                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3365                         DEBUGOUT("PHY Read Error \n");
3366                         return -E1000_ERR_PHY;
3367                 }
3368                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3369                         DEBUGOUT("PHY Read Error \n");
3370                         return -E1000_ERR_PHY;
3371                 }
3372
3373                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3374                         /* The AutoNeg process has completed, so we now need to
3375                          * read both the Auto Negotiation Advertisement Register
3376                          * (Address 4) and the Auto_Negotiation Base Page Ability
3377                          * Register (Address 5) to determine how flow control was
3378                          * negotiated.
3379                          */
3380                         if (e1000_read_phy_reg
3381                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3382                                 DEBUGOUT("PHY Read Error\n");
3383                                 return -E1000_ERR_PHY;
3384                         }
3385                         if (e1000_read_phy_reg
3386                             (hw, PHY_LP_ABILITY,
3387                              &mii_nway_lp_ability_reg) < 0) {
3388                                 DEBUGOUT("PHY Read Error\n");
3389                                 return -E1000_ERR_PHY;
3390                         }
3391
3392                         /* Two bits in the Auto Negotiation Advertisement Register
3393                          * (Address 4) and two bits in the Auto Negotiation Base
3394                          * Page Ability Register (Address 5) determine flow control
3395                          * for both the PHY and the link partner.  The following
3396                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3397                          * 1999, describes these PAUSE resolution bits and how flow
3398                          * control is determined based upon these settings.
3399                          * NOTE:  DC = Don't Care
3400                          *
3401                          *   LOCAL DEVICE  |   LINK PARTNER
3402                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3403                          *-------|---------|-------|---------|--------------------
3404                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3405                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3406                          *   0   |    1    |   1   |    0    | e1000_fc_none
3407                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3408                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3409                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3410                          *   1   |    1    |   0   |    0    | e1000_fc_none
3411                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3412                          *
3413                          */
3414                         /* Are both PAUSE bits set to 1?  If so, this implies
3415                          * Symmetric Flow Control is enabled at both ends.  The
3416                          * ASM_DIR bits are irrelevant per the spec.
3417                          *
3418                          * For Symmetric Flow Control:
3419                          *
3420                          *   LOCAL DEVICE  |   LINK PARTNER
3421                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3422                          *-------|---------|-------|---------|--------------------
3423                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3424                          *
3425                          */
3426                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3427                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3428                                 /* Now we need to check if the user selected RX ONLY
3429                                  * of pause frames.  In this case, we had to advertise
3430                                  * FULL flow control because we could not advertise RX
3431                                  * ONLY. Hence, we must now check to see if we need to
3432                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3433                                  */
3434                                 if (hw->original_fc == e1000_fc_full) {
3435                                         hw->fc = e1000_fc_full;
3436                                         DEBUGOUT("Flow Control = FULL.\r\n");
3437                                 } else {
3438                                         hw->fc = e1000_fc_rx_pause;
3439                                         DEBUGOUT
3440                                             ("Flow Control = RX PAUSE frames only.\r\n");
3441                                 }
3442                         }
3443                         /* For receiving PAUSE frames ONLY.
3444                          *
3445                          *   LOCAL DEVICE  |   LINK PARTNER
3446                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3447                          *-------|---------|-------|---------|--------------------
3448                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3449                          *
3450                          */
3451                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3452                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3453                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3454                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3455                         {
3456                                 hw->fc = e1000_fc_tx_pause;
3457                                 DEBUGOUT
3458                                     ("Flow Control = TX PAUSE frames only.\r\n");
3459                         }
3460                         /* For transmitting PAUSE frames ONLY.
3461                          *
3462                          *   LOCAL DEVICE  |   LINK PARTNER
3463                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3464                          *-------|---------|-------|---------|--------------------
3465                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3466                          *
3467                          */
3468                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3469                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3470                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3471                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3472                         {
3473                                 hw->fc = e1000_fc_rx_pause;
3474                                 DEBUGOUT
3475                                     ("Flow Control = RX PAUSE frames only.\r\n");
3476                         }
3477                         /* Per the IEEE spec, at this point flow control should be
3478                          * disabled.  However, we want to consider that we could
3479                          * be connected to a legacy switch that doesn't advertise
3480                          * desired flow control, but can be forced on the link
3481                          * partner.  So if we advertised no flow control, that is
3482                          * what we will resolve to.  If we advertised some kind of
3483                          * receive capability (Rx Pause Only or Full Flow Control)
3484                          * and the link partner advertised none, we will configure
3485                          * ourselves to enable Rx Flow Control only.  We can do
3486                          * this safely for two reasons:  If the link partner really
3487                          * didn't want flow control enabled, and we enable Rx, no
3488                          * harm done since we won't be receiving any PAUSE frames
3489                          * anyway.  If the intent on the link partner was to have
3490                          * flow control enabled, then by us enabling RX only, we
3491                          * can at least receive pause frames and process them.
3492                          * This is a good idea because in most cases, since we are
3493                          * predominantly a server NIC, more times than not we will
3494                          * be asked to delay transmission of packets than asking
3495                          * our link partner to pause transmission of frames.
3496                          */
3497                         else if (hw->original_fc == e1000_fc_none ||
3498                                  hw->original_fc == e1000_fc_tx_pause) {
3499                                 hw->fc = e1000_fc_none;
3500                                 DEBUGOUT("Flow Control = NONE.\r\n");
3501                         } else {
3502                                 hw->fc = e1000_fc_rx_pause;
3503                                 DEBUGOUT
3504                                     ("Flow Control = RX PAUSE frames only.\r\n");
3505                         }
3506
3507                         /* Now we need to do one last check...  If we auto-
3508                          * negotiated to HALF DUPLEX, flow control should not be
3509                          * enabled per IEEE 802.3 spec.
3510                          */
3511                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3512
3513                         if (duplex == HALF_DUPLEX)
3514                                 hw->fc = e1000_fc_none;
3515
3516                         /* Now we call a subroutine to actually force the MAC
3517                          * controller to use the correct flow control settings.
3518                          */
3519                         ret_val = e1000_force_mac_fc(hw);
3520                         if (ret_val < 0) {
3521                                 DEBUGOUT
3522                                     ("Error forcing flow control settings\n");
3523                                 return ret_val;
3524                         }
3525                 } else {
3526                         DEBUGOUT
3527                             ("Copper PHY and Auto Neg has not completed.\r\n");
3528                 }
3529         }
3530         return E1000_SUCCESS;
3531 }
3532
3533 /******************************************************************************
3534  * Checks to see if the link status of the hardware has changed.
3535  *
3536  * hw - Struct containing variables accessed by shared code
3537  *
3538  * Called by any function that needs to check the link status of the adapter.
3539  *****************************************************************************/
3540 static int
3541 e1000_check_for_link(struct eth_device *nic)
3542 {
3543         struct e1000_hw *hw = nic->priv;
3544         uint32_t rxcw;
3545         uint32_t ctrl;
3546         uint32_t status;
3547         uint32_t rctl;
3548         uint32_t signal;
3549         int32_t ret_val;
3550         uint16_t phy_data;
3551         uint16_t lp_capability;
3552
3553         DEBUGFUNC();
3554
3555         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3556          * set when the optics detect a signal. On older adapters, it will be
3557          * cleared when there is a signal
3558          */
3559         ctrl = E1000_READ_REG(hw, CTRL);
3560         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3561                 signal = E1000_CTRL_SWDPIN1;
3562         else
3563                 signal = 0;
3564
3565         status = E1000_READ_REG(hw, STATUS);
3566         rxcw = E1000_READ_REG(hw, RXCW);
3567         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3568
3569         /* If we have a copper PHY then we only want to go out to the PHY
3570          * registers to see if Auto-Neg has completed and/or if our link
3571          * status has changed.  The get_link_status flag will be set if we
3572          * receive a Link Status Change interrupt or we have Rx Sequence
3573          * Errors.
3574          */
3575         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3576                 /* First we want to see if the MII Status Register reports
3577                  * link.  If so, then we want to get the current speed/duplex
3578                  * of the PHY.
3579                  * Read the register twice since the link bit is sticky.
3580                  */
3581                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3582                         DEBUGOUT("PHY Read Error\n");
3583                         return -E1000_ERR_PHY;
3584                 }
3585                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3586                         DEBUGOUT("PHY Read Error\n");
3587                         return -E1000_ERR_PHY;
3588                 }
3589
3590                 if (phy_data & MII_SR_LINK_STATUS) {
3591                         hw->get_link_status = FALSE;
3592                 } else {
3593                         /* No link detected */
3594                         return -E1000_ERR_NOLINK;
3595                 }
3596
3597                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3598                  * have Si on board that is 82544 or newer, Auto
3599                  * Speed Detection takes care of MAC speed/duplex
3600                  * configuration.  So we only need to configure Collision
3601                  * Distance in the MAC.  Otherwise, we need to force
3602                  * speed/duplex on the MAC to the current PHY speed/duplex
3603                  * settings.
3604                  */
3605                 if (hw->mac_type >= e1000_82544)
3606                         e1000_config_collision_dist(hw);
3607                 else {
3608                         ret_val = e1000_config_mac_to_phy(hw);
3609                         if (ret_val < 0) {
3610                                 DEBUGOUT
3611                                     ("Error configuring MAC to PHY settings\n");
3612                                 return ret_val;
3613                         }
3614                 }
3615
3616                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3617                  * need to restore the desired flow control settings because we may
3618                  * have had to re-autoneg with a different link partner.
3619                  */
3620                 ret_val = e1000_config_fc_after_link_up(hw);
3621                 if (ret_val < 0) {
3622                         DEBUGOUT("Error configuring flow control\n");
3623                         return ret_val;
3624                 }
3625
3626                 /* At this point we know that we are on copper and we have
3627                  * auto-negotiated link.  These are conditions for checking the link
3628                  * parter capability register.  We use the link partner capability to
3629                  * determine if TBI Compatibility needs to be turned on or off.  If
3630                  * the link partner advertises any speed in addition to Gigabit, then
3631                  * we assume that they are GMII-based, and TBI compatibility is not
3632                  * needed. If no other speeds are advertised, we assume the link
3633                  * partner is TBI-based, and we turn on TBI Compatibility.
3634                  */
3635                 if (hw->tbi_compatibility_en) {
3636                         if (e1000_read_phy_reg
3637                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3638                                 DEBUGOUT("PHY Read Error\n");
3639                                 return -E1000_ERR_PHY;
3640                         }
3641                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3642                                              NWAY_LPAR_10T_FD_CAPS |
3643                                              NWAY_LPAR_100TX_HD_CAPS |
3644                                              NWAY_LPAR_100TX_FD_CAPS |
3645                                              NWAY_LPAR_100T4_CAPS)) {
3646                                 /* If our link partner advertises anything in addition to
3647                                  * gigabit, we do not need to enable TBI compatibility.
3648                                  */
3649                                 if (hw->tbi_compatibility_on) {
3650                                         /* If we previously were in the mode, turn it off. */
3651                                         rctl = E1000_READ_REG(hw, RCTL);
3652                                         rctl &= ~E1000_RCTL_SBP;
3653                                         E1000_WRITE_REG(hw, RCTL, rctl);
3654                                         hw->tbi_compatibility_on = FALSE;
3655                                 }
3656                         } else {
3657                                 /* If TBI compatibility is was previously off, turn it on. For
3658                                  * compatibility with a TBI link partner, we will store bad
3659                                  * packets. Some frames have an additional byte on the end and
3660                                  * will look like CRC errors to to the hardware.
3661                                  */
3662                                 if (!hw->tbi_compatibility_on) {
3663                                         hw->tbi_compatibility_on = TRUE;
3664                                         rctl = E1000_READ_REG(hw, RCTL);
3665                                         rctl |= E1000_RCTL_SBP;
3666                                         E1000_WRITE_REG(hw, RCTL, rctl);
3667                                 }
3668                         }
3669                 }
3670         }
3671         /* If we don't have link (auto-negotiation failed or link partner cannot
3672          * auto-negotiate), the cable is plugged in (we have signal), and our
3673          * link partner is not trying to auto-negotiate with us (we are receiving
3674          * idles or data), we need to force link up. We also need to give
3675          * auto-negotiation time to complete, in case the cable was just plugged
3676          * in. The autoneg_failed flag does this.
3677          */
3678         else if ((hw->media_type == e1000_media_type_fiber) &&
3679                  (!(status & E1000_STATUS_LU)) &&
3680                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3681                  (!(rxcw & E1000_RXCW_C))) {
3682                 if (hw->autoneg_failed == 0) {
3683                         hw->autoneg_failed = 1;
3684                         return 0;
3685                 }
3686                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3687
3688                 /* Disable auto-negotiation in the TXCW register */
3689                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3690
3691                 /* Force link-up and also force full-duplex. */
3692                 ctrl = E1000_READ_REG(hw, CTRL);
3693                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3694                 E1000_WRITE_REG(hw, CTRL, ctrl);
3695
3696                 /* Configure Flow Control after forcing link up. */
3697                 ret_val = e1000_config_fc_after_link_up(hw);
3698                 if (ret_val < 0) {
3699                         DEBUGOUT("Error configuring flow control\n");
3700                         return ret_val;
3701                 }
3702         }
3703         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3704          * auto-negotiation in the TXCW register and disable forced link in the
3705          * Device Control register in an attempt to auto-negotiate with our link
3706          * partner.
3707          */
3708         else if ((hw->media_type == e1000_media_type_fiber) &&
3709                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3710                 DEBUGOUT
3711                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3712                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3713                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3714         }
3715         return 0;
3716 }
3717
3718 /******************************************************************************
3719 * Configure the MAC-to-PHY interface for 10/100Mbps
3720 *
3721 * hw - Struct containing variables accessed by shared code
3722 ******************************************************************************/
3723 static int32_t
3724 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3725 {
3726         int32_t ret_val = E1000_SUCCESS;
3727         uint32_t tipg;
3728         uint16_t reg_data;
3729
3730         DEBUGFUNC();
3731
3732         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3733         ret_val = e1000_write_kmrn_reg(hw,
3734                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3735         if (ret_val)
3736                 return ret_val;
3737
3738         /* Configure Transmit Inter-Packet Gap */
3739         tipg = E1000_READ_REG(hw, TIPG);
3740         tipg &= ~E1000_TIPG_IPGT_MASK;
3741         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3742         E1000_WRITE_REG(hw, TIPG, tipg);
3743
3744         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3745
3746         if (ret_val)
3747                 return ret_val;
3748
3749         if (duplex == HALF_DUPLEX)
3750                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3751         else
3752                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3753
3754         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3755
3756         return ret_val;
3757 }
3758
3759 static int32_t
3760 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3761 {
3762         int32_t ret_val = E1000_SUCCESS;
3763         uint16_t reg_data;
3764         uint32_t tipg;
3765
3766         DEBUGFUNC();
3767
3768         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3769         ret_val = e1000_write_kmrn_reg(hw,
3770                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3771         if (ret_val)
3772                 return ret_val;
3773
3774         /* Configure Transmit Inter-Packet Gap */
3775         tipg = E1000_READ_REG(hw, TIPG);
3776         tipg &= ~E1000_TIPG_IPGT_MASK;
3777         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3778         E1000_WRITE_REG(hw, TIPG, tipg);
3779
3780         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3781
3782         if (ret_val)
3783                 return ret_val;
3784
3785         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3786         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3787
3788         return ret_val;
3789 }
3790
3791 /******************************************************************************
3792  * Detects the current speed and duplex settings of the hardware.
3793  *
3794  * hw - Struct containing variables accessed by shared code
3795  * speed - Speed of the connection
3796  * duplex - Duplex setting of the connection
3797  *****************************************************************************/
3798 static int
3799 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3800                 uint16_t *duplex)
3801 {
3802         uint32_t status;
3803         int32_t ret_val;
3804         uint16_t phy_data;
3805
3806         DEBUGFUNC();
3807
3808         if (hw->mac_type >= e1000_82543) {
3809                 status = E1000_READ_REG(hw, STATUS);
3810                 if (status & E1000_STATUS_SPEED_1000) {
3811                         *speed = SPEED_1000;
3812                         DEBUGOUT("1000 Mbs, ");
3813                 } else if (status & E1000_STATUS_SPEED_100) {
3814                         *speed = SPEED_100;
3815                         DEBUGOUT("100 Mbs, ");
3816                 } else {
3817                         *speed = SPEED_10;
3818                         DEBUGOUT("10 Mbs, ");
3819                 }
3820
3821                 if (status & E1000_STATUS_FD) {
3822                         *duplex = FULL_DUPLEX;
3823                         DEBUGOUT("Full Duplex\r\n");
3824                 } else {
3825                         *duplex = HALF_DUPLEX;
3826                         DEBUGOUT(" Half Duplex\r\n");
3827                 }
3828         } else {
3829                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3830                 *speed = SPEED_1000;
3831                 *duplex = FULL_DUPLEX;
3832         }
3833
3834         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3835          * even if it is operating at half duplex.  Here we set the duplex
3836          * settings to match the duplex in the link partner's capabilities.
3837          */
3838         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3839                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3840                 if (ret_val)
3841                         return ret_val;
3842
3843                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3844                         *duplex = HALF_DUPLEX;
3845                 else {
3846                         ret_val = e1000_read_phy_reg(hw,
3847                                         PHY_LP_ABILITY, &phy_data);
3848                         if (ret_val)
3849                                 return ret_val;
3850                         if ((*speed == SPEED_100 &&
3851                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3852                                 || (*speed == SPEED_10
3853                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3854                                 *duplex = HALF_DUPLEX;
3855                 }
3856         }
3857
3858         if ((hw->mac_type == e1000_80003es2lan) &&
3859                 (hw->media_type == e1000_media_type_copper)) {
3860                 if (*speed == SPEED_1000)
3861                         ret_val = e1000_configure_kmrn_for_1000(hw);
3862                 else
3863                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3864                 if (ret_val)
3865                         return ret_val;
3866         }
3867         return E1000_SUCCESS;
3868 }
3869
3870 /******************************************************************************
3871 * Blocks until autoneg completes or times out (~4.5 seconds)
3872 *
3873 * hw - Struct containing variables accessed by shared code
3874 ******************************************************************************/
3875 static int
3876 e1000_wait_autoneg(struct e1000_hw *hw)
3877 {
3878         uint16_t i;
3879         uint16_t phy_data;
3880
3881         DEBUGFUNC();
3882         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3883
3884         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3885         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3886                 /* Read the MII Status Register and wait for Auto-Neg
3887                  * Complete bit to be set.
3888                  */
3889                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3890                         DEBUGOUT("PHY Read Error\n");
3891                         return -E1000_ERR_PHY;
3892                 }
3893                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3894                         DEBUGOUT("PHY Read Error\n");
3895                         return -E1000_ERR_PHY;
3896                 }
3897                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3898                         DEBUGOUT("Auto-Neg complete.\n");
3899                         return 0;
3900                 }
3901                 mdelay(100);
3902         }
3903         DEBUGOUT("Auto-Neg timedout.\n");
3904         return -E1000_ERR_TIMEOUT;
3905 }
3906
3907 /******************************************************************************
3908 * Raises the Management Data Clock
3909 *
3910 * hw - Struct containing variables accessed by shared code
3911 * ctrl - Device control register's current value
3912 ******************************************************************************/
3913 static void
3914 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3915 {
3916         /* Raise the clock input to the Management Data Clock (by setting the MDC
3917          * bit), and then delay 2 microseconds.
3918          */
3919         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3920         E1000_WRITE_FLUSH(hw);
3921         udelay(2);
3922 }
3923
3924 /******************************************************************************
3925 * Lowers the Management Data Clock
3926 *
3927 * hw - Struct containing variables accessed by shared code
3928 * ctrl - Device control register's current value
3929 ******************************************************************************/
3930 static void
3931 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3932 {
3933         /* Lower the clock input to the Management Data Clock (by clearing the MDC
3934          * bit), and then delay 2 microseconds.
3935          */
3936         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3937         E1000_WRITE_FLUSH(hw);
3938         udelay(2);
3939 }
3940
3941 /******************************************************************************
3942 * Shifts data bits out to the PHY
3943 *
3944 * hw - Struct containing variables accessed by shared code
3945 * data - Data to send out to the PHY
3946 * count - Number of bits to shift out
3947 *
3948 * Bits are shifted out in MSB to LSB order.
3949 ******************************************************************************/
3950 static void
3951 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3952 {
3953         uint32_t ctrl;
3954         uint32_t mask;
3955
3956         /* We need to shift "count" number of bits out to the PHY. So, the value
3957          * in the "data" parameter will be shifted out to the PHY one bit at a
3958          * time. In order to do this, "data" must be broken down into bits.
3959          */
3960         mask = 0x01;
3961         mask <<= (count - 1);
3962
3963         ctrl = E1000_READ_REG(hw, CTRL);
3964
3965         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3966         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3967
3968         while (mask) {
3969                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3970                  * then raising and lowering the Management Data Clock. A "0" is
3971                  * shifted out to the PHY by setting the MDIO bit to "0" and then
3972                  * raising and lowering the clock.
3973                  */
3974                 if (data & mask)
3975                         ctrl |= E1000_CTRL_MDIO;
3976                 else
3977                         ctrl &= ~E1000_CTRL_MDIO;
3978
3979                 E1000_WRITE_REG(hw, CTRL, ctrl);
3980                 E1000_WRITE_FLUSH(hw);
3981
3982                 udelay(2);
3983
3984                 e1000_raise_mdi_clk(hw, &ctrl);
3985                 e1000_lower_mdi_clk(hw, &ctrl);
3986
3987                 mask = mask >> 1;
3988         }
3989 }
3990
3991 /******************************************************************************
3992 * Shifts data bits in from the PHY
3993 *
3994 * hw - Struct containing variables accessed by shared code
3995 *
3996 * Bits are shifted in in MSB to LSB order.
3997 ******************************************************************************/
3998 static uint16_t
3999 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4000 {
4001         uint32_t ctrl;
4002         uint16_t data = 0;
4003         uint8_t i;
4004
4005         /* In order to read a register from the PHY, we need to shift in a total
4006          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4007          * to avoid contention on the MDIO pin when a read operation is performed.
4008          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4009          * by raising the input to the Management Data Clock (setting the MDC bit),
4010          * and then reading the value of the MDIO bit.
4011          */
4012         ctrl = E1000_READ_REG(hw, CTRL);
4013
4014         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4015         ctrl &= ~E1000_CTRL_MDIO_DIR;
4016         ctrl &= ~E1000_CTRL_MDIO;
4017
4018         E1000_WRITE_REG(hw, CTRL, ctrl);
4019         E1000_WRITE_FLUSH(hw);
4020
4021         /* Raise and Lower the clock before reading in the data. This accounts for
4022          * the turnaround bits. The first clock occurred when we clocked out the
4023          * last bit of the Register Address.
4024          */
4025         e1000_raise_mdi_clk(hw, &ctrl);
4026         e1000_lower_mdi_clk(hw, &ctrl);
4027
4028         for (data = 0, i = 0; i < 16; i++) {
4029                 data = data << 1;
4030                 e1000_raise_mdi_clk(hw, &ctrl);
4031                 ctrl = E1000_READ_REG(hw, CTRL);
4032                 /* Check to see if we shifted in a "1". */
4033                 if (ctrl & E1000_CTRL_MDIO)
4034                         data |= 1;
4035                 e1000_lower_mdi_clk(hw, &ctrl);
4036         }
4037
4038         e1000_raise_mdi_clk(hw, &ctrl);
4039         e1000_lower_mdi_clk(hw, &ctrl);
4040
4041         return data;
4042 }
4043
4044 /*****************************************************************************
4045 * Reads the value from a PHY register
4046 *
4047 * hw - Struct containing variables accessed by shared code
4048 * reg_addr - address of the PHY register to read
4049 ******************************************************************************/
4050 static int
4051 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4052 {
4053         uint32_t i;
4054         uint32_t mdic = 0;
4055         const uint32_t phy_addr = 1;
4056
4057         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4058                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4059                 return -E1000_ERR_PARAM;
4060         }
4061
4062         if (hw->mac_type > e1000_82543) {
4063                 /* Set up Op-code, Phy Address, and register address in the MDI
4064                  * Control register.  The MAC will take care of interfacing with the
4065                  * PHY to retrieve the desired data.
4066                  */
4067                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4068                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4069                         (E1000_MDIC_OP_READ));
4070
4071                 E1000_WRITE_REG(hw, MDIC, mdic);
4072
4073                 /* Poll the ready bit to see if the MDI read completed */
4074                 for (i = 0; i < 64; i++) {
4075                         udelay(10);
4076                         mdic = E1000_READ_REG(hw, MDIC);
4077                         if (mdic & E1000_MDIC_READY)
4078                                 break;
4079                 }
4080                 if (!(mdic & E1000_MDIC_READY)) {
4081                         DEBUGOUT("MDI Read did not complete\n");
4082                         return -E1000_ERR_PHY;
4083                 }
4084                 if (mdic & E1000_MDIC_ERROR) {
4085                         DEBUGOUT("MDI Error\n");
4086                         return -E1000_ERR_PHY;
4087                 }
4088                 *phy_data = (uint16_t) mdic;
4089         } else {
4090                 /* We must first send a preamble through the MDIO pin to signal the
4091                  * beginning of an MII instruction.  This is done by sending 32
4092                  * consecutive "1" bits.
4093                  */
4094                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4095
4096                 /* Now combine the next few fields that are required for a read
4097                  * operation.  We use this method instead of calling the
4098                  * e1000_shift_out_mdi_bits routine five different times. The format of
4099                  * a MII read instruction consists of a shift out of 14 bits and is
4100                  * defined as follows:
4101                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4102                  * followed by a shift in of 18 bits.  This first two bits shifted in
4103                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4104                  * READ operation is performed.  These two bits are thrown away
4105                  * followed by a shift in of 16 bits which contains the desired data.
4106                  */
4107                 mdic = ((reg_addr) | (phy_addr << 5) |
4108                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4109
4110                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4111
4112                 /* Now that we've shifted out the read command to the MII, we need to
4113                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4114                  * register address.
4115                  */
4116                 *phy_data = e1000_shift_in_mdi_bits(hw);
4117         }
4118         return 0;
4119 }
4120
4121 /******************************************************************************
4122 * Writes a value to a PHY register
4123 *
4124 * hw - Struct containing variables accessed by shared code
4125 * reg_addr - address of the PHY register to write
4126 * data - data to write to the PHY
4127 ******************************************************************************/
4128 static int
4129 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4130 {
4131         uint32_t i;
4132         uint32_t mdic = 0;
4133         const uint32_t phy_addr = 1;
4134
4135         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4136                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4137                 return -E1000_ERR_PARAM;
4138         }
4139
4140         if (hw->mac_type > e1000_82543) {
4141                 /* Set up Op-code, Phy Address, register address, and data intended
4142                  * for the PHY register in the MDI Control register.  The MAC will take
4143                  * care of interfacing with the PHY to send the desired data.
4144                  */
4145                 mdic = (((uint32_t) phy_data) |
4146                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4147                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4148                         (E1000_MDIC_OP_WRITE));
4149
4150                 E1000_WRITE_REG(hw, MDIC, mdic);
4151
4152                 /* Poll the ready bit to see if the MDI read completed */
4153                 for (i = 0; i < 64; i++) {
4154                         udelay(10);
4155                         mdic = E1000_READ_REG(hw, MDIC);
4156                         if (mdic & E1000_MDIC_READY)
4157                                 break;
4158                 }
4159                 if (!(mdic & E1000_MDIC_READY)) {
4160                         DEBUGOUT("MDI Write did not complete\n");
4161                         return -E1000_ERR_PHY;
4162                 }
4163         } else {
4164                 /* We'll need to use the SW defined pins to shift the write command
4165                  * out to the PHY. We first send a preamble to the PHY to signal the
4166                  * beginning of the MII instruction.  This is done by sending 32
4167                  * consecutive "1" bits.
4168                  */
4169                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4170
4171                 /* Now combine the remaining required fields that will indicate a
4172                  * write operation. We use this method instead of calling the
4173                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4174                  * format of a MII write instruction is as follows:
4175                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4176                  */
4177                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4178                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4179                 mdic <<= 16;
4180                 mdic |= (uint32_t) phy_data;
4181
4182                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4183         }
4184         return 0;
4185 }
4186
4187 /******************************************************************************
4188  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4189  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4190  * the caller to figure out how to deal with it.
4191  *
4192  * hw - Struct containing variables accessed by shared code
4193  *
4194  * returns: - E1000_BLK_PHY_RESET
4195  *            E1000_SUCCESS
4196  *
4197  *****************************************************************************/
4198 int32_t
4199 e1000_check_phy_reset_block(struct e1000_hw *hw)
4200 {
4201         uint32_t manc = 0;
4202         uint32_t fwsm = 0;
4203
4204         if (hw->mac_type == e1000_ich8lan) {
4205                 fwsm = E1000_READ_REG(hw, FWSM);
4206                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4207                                                 : E1000_BLK_PHY_RESET;
4208         }
4209
4210         if (hw->mac_type > e1000_82547_rev_2)
4211                 manc = E1000_READ_REG(hw, MANC);
4212         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4213                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4214 }
4215
4216 /***************************************************************************
4217  * Checks if the PHY configuration is done
4218  *
4219  * hw: Struct containing variables accessed by shared code
4220  *
4221  * returns: - E1000_ERR_RESET if fail to reset MAC
4222  *            E1000_SUCCESS at any other case.
4223  *
4224  ***************************************************************************/
4225 static int32_t
4226 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4227 {
4228         int32_t timeout = PHY_CFG_TIMEOUT;
4229         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4230
4231         DEBUGFUNC();
4232
4233         switch (hw->mac_type) {
4234         default:
4235                 mdelay(10);
4236                 break;
4237
4238         case e1000_80003es2lan:
4239                 /* Separate *_CFG_DONE_* bit for each port */
4240                 if (e1000_is_second_port(hw))
4241                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4242                 /* Fall Through */
4243
4244         case e1000_82571:
4245         case e1000_82572:
4246                 while (timeout) {
4247                         if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4248                                 break;
4249                         else
4250                                 mdelay(1);
4251                         timeout--;
4252                 }
4253                 if (!timeout) {
4254                         DEBUGOUT("MNG configuration cycle has not "
4255                                         "completed.\n");
4256                         return -E1000_ERR_RESET;
4257                 }
4258                 break;
4259         }
4260
4261         return E1000_SUCCESS;
4262 }
4263
4264 /******************************************************************************
4265 * Returns the PHY to the power-on reset state
4266 *
4267 * hw - Struct containing variables accessed by shared code
4268 ******************************************************************************/
4269 int32_t
4270 e1000_phy_hw_reset(struct e1000_hw *hw)
4271 {
4272         uint16_t swfw = E1000_SWFW_PHY0_SM;
4273         uint32_t ctrl, ctrl_ext;
4274         uint32_t led_ctrl;
4275         int32_t ret_val;
4276
4277         DEBUGFUNC();
4278
4279         /* In the case of the phy reset being blocked, it's not an error, we
4280          * simply return success without performing the reset. */
4281         ret_val = e1000_check_phy_reset_block(hw);
4282         if (ret_val)
4283                 return E1000_SUCCESS;
4284
4285         DEBUGOUT("Resetting Phy...\n");
4286
4287         if (hw->mac_type > e1000_82543) {
4288                 if (e1000_is_second_port(hw))
4289                         swfw = E1000_SWFW_PHY1_SM;
4290
4291                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4292                         DEBUGOUT("Unable to acquire swfw sync\n");
4293                         return -E1000_ERR_SWFW_SYNC;
4294                 }
4295
4296                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4297                  * bit. Then, take it out of reset.
4298                  */
4299                 ctrl = E1000_READ_REG(hw, CTRL);
4300                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4301                 E1000_WRITE_FLUSH(hw);
4302
4303                 if (hw->mac_type < e1000_82571)
4304                         udelay(10);
4305                 else
4306                         udelay(100);
4307
4308                 E1000_WRITE_REG(hw, CTRL, ctrl);
4309                 E1000_WRITE_FLUSH(hw);
4310
4311                 if (hw->mac_type >= e1000_82571)
4312                         mdelay(10);
4313
4314         } else {
4315                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4316                  * bit to put the PHY into reset. Then, take it out of reset.
4317                  */
4318                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4319                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4320                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4321                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4322                 E1000_WRITE_FLUSH(hw);
4323                 mdelay(10);
4324                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4325                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4326                 E1000_WRITE_FLUSH(hw);
4327         }
4328         udelay(150);
4329
4330         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4331                 /* Configure activity LED after PHY reset */
4332                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4333                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4334                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4335                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4336         }
4337
4338         /* Wait for FW to finish PHY configuration. */
4339         ret_val = e1000_get_phy_cfg_done(hw);
4340         if (ret_val != E1000_SUCCESS)
4341                 return ret_val;
4342
4343         return ret_val;
4344 }
4345
4346 /******************************************************************************
4347  * IGP phy init script - initializes the GbE PHY
4348  *
4349  * hw - Struct containing variables accessed by shared code
4350  *****************************************************************************/
4351 static void
4352 e1000_phy_init_script(struct e1000_hw *hw)
4353 {
4354         uint32_t ret_val;
4355         uint16_t phy_saved_data;
4356         DEBUGFUNC();
4357
4358         if (hw->phy_init_script) {
4359                 mdelay(20);
4360
4361                 /* Save off the current value of register 0x2F5B to be
4362                  * restored at the end of this routine. */
4363                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4364
4365                 /* Disabled the PHY transmitter */
4366                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4367
4368                 mdelay(20);
4369
4370                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4371
4372                 mdelay(5);
4373
4374                 switch (hw->mac_type) {
4375                 case e1000_82541:
4376                 case e1000_82547:
4377                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4378
4379                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4380
4381                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4382
4383                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4384
4385                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4386
4387                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4388
4389                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4390
4391                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4392
4393                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4394                         break;
4395
4396                 case e1000_82541_rev_2:
4397                 case e1000_82547_rev_2:
4398                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4399                         break;
4400                 default:
4401                         break;
4402                 }
4403
4404                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4405
4406                 mdelay(20);
4407
4408                 /* Now enable the transmitter */
4409                 if (!ret_val)
4410                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4411
4412                 if (hw->mac_type == e1000_82547) {
4413                         uint16_t fused, fine, coarse;
4414
4415                         /* Move to analog registers page */
4416                         e1000_read_phy_reg(hw,
4417                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4418
4419                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4420                                 e1000_read_phy_reg(hw,
4421                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4422
4423                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4424                                 coarse = fused
4425                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4426
4427                                 if (coarse >
4428                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4429                                         coarse -=
4430                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4431                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4432                                 } else if (coarse
4433                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4434                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4435
4436                                 fused = (fused
4437                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4438                                         (fine
4439                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4440                                         (coarse
4441                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4442
4443                                 e1000_write_phy_reg(hw,
4444                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4445                                 e1000_write_phy_reg(hw,
4446                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4447                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4448                         }
4449                 }
4450         }
4451 }
4452
4453 /******************************************************************************
4454 * Resets the PHY
4455 *
4456 * hw - Struct containing variables accessed by shared code
4457 *
4458 * Sets bit 15 of the MII Control register
4459 ******************************************************************************/
4460 int32_t
4461 e1000_phy_reset(struct e1000_hw *hw)
4462 {
4463         int32_t ret_val;
4464         uint16_t phy_data;
4465
4466         DEBUGFUNC();
4467
4468         /* In the case of the phy reset being blocked, it's not an error, we
4469          * simply return success without performing the reset. */
4470         ret_val = e1000_check_phy_reset_block(hw);
4471         if (ret_val)
4472                 return E1000_SUCCESS;
4473
4474         switch (hw->phy_type) {
4475         case e1000_phy_igp:
4476         case e1000_phy_igp_2:
4477         case e1000_phy_igp_3:
4478         case e1000_phy_ife:
4479                 ret_val = e1000_phy_hw_reset(hw);
4480                 if (ret_val)
4481                         return ret_val;
4482                 break;
4483         default:
4484                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4485                 if (ret_val)
4486                         return ret_val;
4487
4488                 phy_data |= MII_CR_RESET;
4489                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4490                 if (ret_val)
4491                         return ret_val;
4492
4493                 udelay(1);
4494                 break;
4495         }
4496
4497         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4498                 e1000_phy_init_script(hw);
4499
4500         return E1000_SUCCESS;
4501 }
4502
4503 static int e1000_set_phy_type (struct e1000_hw *hw)
4504 {
4505         DEBUGFUNC ();
4506
4507         if (hw->mac_type == e1000_undefined)
4508                 return -E1000_ERR_PHY_TYPE;
4509
4510         switch (hw->phy_id) {
4511         case M88E1000_E_PHY_ID:
4512         case M88E1000_I_PHY_ID:
4513         case M88E1011_I_PHY_ID:
4514         case M88E1111_I_PHY_ID:
4515                 hw->phy_type = e1000_phy_m88;
4516                 break;
4517         case IGP01E1000_I_PHY_ID:
4518                 if (hw->mac_type == e1000_82541 ||
4519                         hw->mac_type == e1000_82541_rev_2 ||
4520                         hw->mac_type == e1000_82547 ||
4521                         hw->mac_type == e1000_82547_rev_2) {
4522                         hw->phy_type = e1000_phy_igp;
4523                         hw->phy_type = e1000_phy_igp;
4524                         break;
4525                 }
4526         case IGP03E1000_E_PHY_ID:
4527                 hw->phy_type = e1000_phy_igp_3;
4528                 break;
4529         case IFE_E_PHY_ID:
4530         case IFE_PLUS_E_PHY_ID:
4531         case IFE_C_E_PHY_ID:
4532                 hw->phy_type = e1000_phy_ife;
4533                 break;
4534         case GG82563_E_PHY_ID:
4535                 if (hw->mac_type == e1000_80003es2lan) {
4536                         hw->phy_type = e1000_phy_gg82563;
4537                         break;
4538                 }
4539         case BME1000_E_PHY_ID:
4540                 hw->phy_type = e1000_phy_bm;
4541                 break;
4542                 /* Fall Through */
4543         default:
4544                 /* Should never have loaded on this device */
4545                 hw->phy_type = e1000_phy_undefined;
4546                 return -E1000_ERR_PHY_TYPE;
4547         }
4548
4549         return E1000_SUCCESS;
4550 }
4551
4552 /******************************************************************************
4553 * Probes the expected PHY address for known PHY IDs
4554 *
4555 * hw - Struct containing variables accessed by shared code
4556 ******************************************************************************/
4557 static int32_t
4558 e1000_detect_gig_phy(struct e1000_hw *hw)
4559 {
4560         int32_t phy_init_status, ret_val;
4561         uint16_t phy_id_high, phy_id_low;
4562         boolean_t match = FALSE;
4563
4564         DEBUGFUNC();
4565
4566         /* The 82571 firmware may still be configuring the PHY.  In this
4567          * case, we cannot access the PHY until the configuration is done.  So
4568          * we explicitly set the PHY values. */
4569         if (hw->mac_type == e1000_82571 ||
4570                 hw->mac_type == e1000_82572) {
4571                 hw->phy_id = IGP01E1000_I_PHY_ID;
4572                 hw->phy_type = e1000_phy_igp_2;
4573                 return E1000_SUCCESS;
4574         }
4575
4576         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4577          * work- around that forces PHY page 0 to be set or the reads fail.
4578          * The rest of the code in this routine uses e1000_read_phy_reg to
4579          * read the PHY ID.  So for ESB-2 we need to have this set so our
4580          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4581          * the routines below will figure this out as well. */
4582         if (hw->mac_type == e1000_80003es2lan)
4583                 hw->phy_type = e1000_phy_gg82563;
4584
4585         /* Read the PHY ID Registers to identify which PHY is onboard. */
4586         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4587         if (ret_val)
4588                 return ret_val;
4589
4590         hw->phy_id = (uint32_t) (phy_id_high << 16);
4591         udelay(20);
4592         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4593         if (ret_val)
4594                 return ret_val;
4595
4596         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4597         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4598
4599         switch (hw->mac_type) {
4600         case e1000_82543:
4601                 if (hw->phy_id == M88E1000_E_PHY_ID)
4602                         match = TRUE;
4603                 break;
4604         case e1000_82544:
4605                 if (hw->phy_id == M88E1000_I_PHY_ID)
4606                         match = TRUE;
4607                 break;
4608         case e1000_82540:
4609         case e1000_82545:
4610         case e1000_82545_rev_3:
4611         case e1000_82546:
4612         case e1000_82546_rev_3:
4613                 if (hw->phy_id == M88E1011_I_PHY_ID)
4614                         match = TRUE;
4615                 break;
4616         case e1000_82541:
4617         case e1000_82541_rev_2:
4618         case e1000_82547:
4619         case e1000_82547_rev_2:
4620                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4621                         match = TRUE;
4622
4623                 break;
4624         case e1000_82573:
4625                 if (hw->phy_id == M88E1111_I_PHY_ID)
4626                         match = TRUE;
4627                 break;
4628         case e1000_82574:
4629                 if (hw->phy_id == BME1000_E_PHY_ID)
4630                         match = TRUE;
4631                 break;
4632         case e1000_80003es2lan:
4633                 if (hw->phy_id == GG82563_E_PHY_ID)
4634                         match = TRUE;
4635                 break;
4636         case e1000_ich8lan:
4637                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4638                         match = TRUE;
4639                 if (hw->phy_id == IFE_E_PHY_ID)
4640                         match = TRUE;
4641                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4642                         match = TRUE;
4643                 if (hw->phy_id == IFE_C_E_PHY_ID)
4644                         match = TRUE;
4645                 break;
4646         default:
4647                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4648                 return -E1000_ERR_CONFIG;
4649         }
4650
4651         phy_init_status = e1000_set_phy_type(hw);
4652
4653         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4654                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4655                 return 0;
4656         }
4657         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4658         return -E1000_ERR_PHY;
4659 }
4660
4661 /*****************************************************************************
4662  * Set media type and TBI compatibility.
4663  *
4664  * hw - Struct containing variables accessed by shared code
4665  * **************************************************************************/
4666 void
4667 e1000_set_media_type(struct e1000_hw *hw)
4668 {
4669         uint32_t status;
4670
4671         DEBUGFUNC();
4672
4673         if (hw->mac_type != e1000_82543) {
4674                 /* tbi_compatibility is only valid on 82543 */
4675                 hw->tbi_compatibility_en = FALSE;
4676         }
4677
4678         switch (hw->device_id) {
4679         case E1000_DEV_ID_82545GM_SERDES:
4680         case E1000_DEV_ID_82546GB_SERDES:
4681         case E1000_DEV_ID_82571EB_SERDES:
4682         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4683         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4684         case E1000_DEV_ID_82572EI_SERDES:
4685         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4686                 hw->media_type = e1000_media_type_internal_serdes;
4687                 break;
4688         default:
4689                 switch (hw->mac_type) {
4690                 case e1000_82542_rev2_0:
4691                 case e1000_82542_rev2_1:
4692                         hw->media_type = e1000_media_type_fiber;
4693                         break;
4694                 case e1000_ich8lan:
4695                 case e1000_82573:
4696                 case e1000_82574:
4697                         /* The STATUS_TBIMODE bit is reserved or reused
4698                          * for the this device.
4699                          */
4700                         hw->media_type = e1000_media_type_copper;
4701                         break;
4702                 default:
4703                         status = E1000_READ_REG(hw, STATUS);
4704                         if (status & E1000_STATUS_TBIMODE) {
4705                                 hw->media_type = e1000_media_type_fiber;
4706                                 /* tbi_compatibility not valid on fiber */
4707                                 hw->tbi_compatibility_en = FALSE;
4708                         } else {
4709                                 hw->media_type = e1000_media_type_copper;
4710                         }
4711                         break;
4712                 }
4713         }
4714 }
4715
4716 /**
4717  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4718  *
4719  * e1000_sw_init initializes the Adapter private data structure.
4720  * Fields are initialized based on PCI device information and
4721  * OS network device settings (MTU size).
4722  **/
4723
4724 static int
4725 e1000_sw_init(struct eth_device *nic)
4726 {
4727         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4728         int result;
4729
4730         /* PCI config space info */
4731         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4732         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4733         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4734                              &hw->subsystem_vendor_id);
4735         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4736
4737         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4738         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4739
4740         /* identify the MAC */
4741         result = e1000_set_mac_type(hw);
4742         if (result) {
4743                 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4744                 return result;
4745         }
4746
4747         switch (hw->mac_type) {
4748         default:
4749                 break;
4750         case e1000_82541:
4751         case e1000_82547:
4752         case e1000_82541_rev_2:
4753         case e1000_82547_rev_2:
4754                 hw->phy_init_script = 1;
4755                 break;
4756         }
4757
4758         /* flow control settings */
4759         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4760         hw->fc_low_water = E1000_FC_LOW_THRESH;
4761         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4762         hw->fc_send_xon = 1;
4763
4764         /* Media type - copper or fiber */
4765         e1000_set_media_type(hw);
4766
4767         if (hw->mac_type >= e1000_82543) {
4768                 uint32_t status = E1000_READ_REG(hw, STATUS);
4769
4770                 if (status & E1000_STATUS_TBIMODE) {
4771                         DEBUGOUT("fiber interface\n");
4772                         hw->media_type = e1000_media_type_fiber;
4773                 } else {
4774                         DEBUGOUT("copper interface\n");
4775                         hw->media_type = e1000_media_type_copper;
4776                 }
4777         } else {
4778                 hw->media_type = e1000_media_type_fiber;
4779         }
4780
4781         hw->tbi_compatibility_en = TRUE;
4782         hw->wait_autoneg_complete = TRUE;
4783         if (hw->mac_type < e1000_82543)
4784                 hw->report_tx_early = 0;
4785         else
4786                 hw->report_tx_early = 1;
4787
4788         return E1000_SUCCESS;
4789 }
4790
4791 void
4792 fill_rx(struct e1000_hw *hw)
4793 {
4794         struct e1000_rx_desc *rd;
4795
4796         rx_last = rx_tail;
4797         rd = rx_base + rx_tail;
4798         rx_tail = (rx_tail + 1) % 8;
4799         memset(rd, 0, 16);
4800         rd->buffer_addr = cpu_to_le64((u32) & packet);
4801         E1000_WRITE_REG(hw, RDT, rx_tail);
4802 }
4803
4804 /**
4805  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4806  * @adapter: board private structure
4807  *
4808  * Configure the Tx unit of the MAC after a reset.
4809  **/
4810
4811 static void
4812 e1000_configure_tx(struct e1000_hw *hw)
4813 {
4814         unsigned long ptr;
4815         unsigned long tctl;
4816         unsigned long tipg, tarc;
4817         uint32_t ipgr1, ipgr2;
4818
4819         ptr = (u32) tx_pool;
4820         if (ptr & 0xf)
4821                 ptr = (ptr + 0x10) & (~0xf);
4822
4823         tx_base = (typeof(tx_base)) ptr;
4824
4825         E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4826         E1000_WRITE_REG(hw, TDBAH, 0);
4827
4828         E1000_WRITE_REG(hw, TDLEN, 128);
4829
4830         /* Setup the HW Tx Head and Tail descriptor pointers */
4831         E1000_WRITE_REG(hw, TDH, 0);
4832         E1000_WRITE_REG(hw, TDT, 0);
4833         tx_tail = 0;
4834
4835         /* Set the default values for the Tx Inter Packet Gap timer */
4836         if (hw->mac_type <= e1000_82547_rev_2 &&
4837             (hw->media_type == e1000_media_type_fiber ||
4838              hw->media_type == e1000_media_type_internal_serdes))
4839                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4840         else
4841                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4842
4843         /* Set the default values for the Tx Inter Packet Gap timer */
4844         switch (hw->mac_type) {
4845         case e1000_82542_rev2_0:
4846         case e1000_82542_rev2_1:
4847                 tipg = DEFAULT_82542_TIPG_IPGT;
4848                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4849                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4850                 break;
4851         case e1000_80003es2lan:
4852                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4853                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4854                 break;
4855         default:
4856                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4857                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4858                 break;
4859         }
4860         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4861         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4862         E1000_WRITE_REG(hw, TIPG, tipg);
4863         /* Program the Transmit Control Register */
4864         tctl = E1000_READ_REG(hw, TCTL);
4865         tctl &= ~E1000_TCTL_CT;
4866         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4867             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4868
4869         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4870                 tarc = E1000_READ_REG(hw, TARC0);
4871                 /* set the speed mode bit, we'll clear it if we're not at
4872                  * gigabit link later */
4873                 /* git bit can be set to 1*/
4874         } else if (hw->mac_type == e1000_80003es2lan) {
4875                 tarc = E1000_READ_REG(hw, TARC0);
4876                 tarc |= 1;
4877                 E1000_WRITE_REG(hw, TARC0, tarc);
4878                 tarc = E1000_READ_REG(hw, TARC1);
4879                 tarc |= 1;
4880                 E1000_WRITE_REG(hw, TARC1, tarc);
4881         }
4882
4883
4884         e1000_config_collision_dist(hw);
4885         /* Setup Transmit Descriptor Settings for eop descriptor */
4886         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4887
4888         /* Need to set up RS bit */
4889         if (hw->mac_type < e1000_82543)
4890                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4891         else
4892                 hw->txd_cmd |= E1000_TXD_CMD_RS;
4893         E1000_WRITE_REG(hw, TCTL, tctl);
4894 }
4895
4896 /**
4897  * e1000_setup_rctl - configure the receive control register
4898  * @adapter: Board private structure
4899  **/
4900 static void
4901 e1000_setup_rctl(struct e1000_hw *hw)
4902 {
4903         uint32_t rctl;
4904
4905         rctl = E1000_READ_REG(hw, RCTL);
4906
4907         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4908
4909         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4910                 | E1000_RCTL_RDMTS_HALF;        /* |
4911                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4912
4913         if (hw->tbi_compatibility_on == 1)
4914                 rctl |= E1000_RCTL_SBP;
4915         else
4916                 rctl &= ~E1000_RCTL_SBP;
4917
4918         rctl &= ~(E1000_RCTL_SZ_4096);
4919                 rctl |= E1000_RCTL_SZ_2048;
4920                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4921         E1000_WRITE_REG(hw, RCTL, rctl);
4922 }
4923
4924 /**
4925  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4926  * @adapter: board private structure
4927  *
4928  * Configure the Rx unit of the MAC after a reset.
4929  **/
4930 static void
4931 e1000_configure_rx(struct e1000_hw *hw)
4932 {
4933         unsigned long ptr;
4934         unsigned long rctl, ctrl_ext;
4935         rx_tail = 0;
4936         /* make sure receives are disabled while setting up the descriptors */
4937         rctl = E1000_READ_REG(hw, RCTL);
4938         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4939         if (hw->mac_type >= e1000_82540) {
4940                 /* Set the interrupt throttling rate.  Value is calculated
4941                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4942 #define MAX_INTS_PER_SEC        8000
4943 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
4944                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4945         }
4946
4947         if (hw->mac_type >= e1000_82571) {
4948                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4949                 /* Reset delay timers after every interrupt */
4950                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4951                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4952                 E1000_WRITE_FLUSH(hw);
4953         }
4954         /* Setup the Base and Length of the Rx Descriptor Ring */
4955         ptr = (u32) rx_pool;
4956         if (ptr & 0xf)
4957                 ptr = (ptr + 0x10) & (~0xf);
4958         rx_base = (typeof(rx_base)) ptr;
4959         E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
4960         E1000_WRITE_REG(hw, RDBAH, 0);
4961
4962         E1000_WRITE_REG(hw, RDLEN, 128);
4963
4964         /* Setup the HW Rx Head and Tail Descriptor Pointers */
4965         E1000_WRITE_REG(hw, RDH, 0);
4966         E1000_WRITE_REG(hw, RDT, 0);
4967         /* Enable Receives */
4968
4969         E1000_WRITE_REG(hw, RCTL, rctl);
4970         fill_rx(hw);
4971 }
4972
4973 /**************************************************************************
4974 POLL - Wait for a frame
4975 ***************************************************************************/
4976 static int
4977 e1000_poll(struct eth_device *nic)
4978 {
4979         struct e1000_hw *hw = nic->priv;
4980         struct e1000_rx_desc *rd;
4981         /* return true if there's an ethernet packet ready to read */
4982         rd = rx_base + rx_last;
4983         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
4984                 return 0;
4985         /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
4986         NetReceive((uchar *)packet, le32_to_cpu(rd->length));
4987         fill_rx(hw);
4988         return 1;
4989 }
4990
4991 /**************************************************************************
4992 TRANSMIT - Transmit a frame
4993 ***************************************************************************/
4994 static int e1000_transmit(struct eth_device *nic, void *packet, int length)
4995 {
4996         void *nv_packet = (void *)packet;
4997         struct e1000_hw *hw = nic->priv;
4998         struct e1000_tx_desc *txp;
4999         int i = 0;
5000
5001         txp = tx_base + tx_tail;
5002         tx_tail = (tx_tail + 1) % 8;
5003
5004         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5005         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5006         txp->upper.data = 0;
5007         E1000_WRITE_REG(hw, TDT, tx_tail);
5008
5009         E1000_WRITE_FLUSH(hw);
5010         while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5011                 if (i++ > TOUT_LOOP) {
5012                         DEBUGOUT("e1000: tx timeout\n");
5013                         return 0;
5014                 }
5015                 udelay(10);     /* give the nic a chance to write to the register */
5016         }
5017         return 1;
5018 }
5019
5020 /*reset function*/
5021 static inline int
5022 e1000_reset(struct eth_device *nic)
5023 {
5024         struct e1000_hw *hw = nic->priv;
5025
5026         e1000_reset_hw(hw);
5027         if (hw->mac_type >= e1000_82544) {
5028                 E1000_WRITE_REG(hw, WUC, 0);
5029         }
5030         return e1000_init_hw(nic);
5031 }
5032
5033 /**************************************************************************
5034 DISABLE - Turn off ethernet interface
5035 ***************************************************************************/
5036 static void
5037 e1000_disable(struct eth_device *nic)
5038 {
5039         struct e1000_hw *hw = nic->priv;
5040
5041         /* Turn off the ethernet interface */
5042         E1000_WRITE_REG(hw, RCTL, 0);
5043         E1000_WRITE_REG(hw, TCTL, 0);
5044
5045         /* Clear the transmit ring */
5046         E1000_WRITE_REG(hw, TDH, 0);
5047         E1000_WRITE_REG(hw, TDT, 0);
5048
5049         /* Clear the receive ring */
5050         E1000_WRITE_REG(hw, RDH, 0);
5051         E1000_WRITE_REG(hw, RDT, 0);
5052
5053         /* put the card in its initial state */
5054 #if 0
5055         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5056 #endif
5057         mdelay(10);
5058
5059 }
5060
5061 /**************************************************************************
5062 INIT - set up ethernet interface(s)
5063 ***************************************************************************/
5064 static int
5065 e1000_init(struct eth_device *nic, bd_t * bis)
5066 {
5067         struct e1000_hw *hw = nic->priv;
5068         int ret_val = 0;
5069
5070         ret_val = e1000_reset(nic);
5071         if (ret_val < 0) {
5072                 if ((ret_val == -E1000_ERR_NOLINK) ||
5073                     (ret_val == -E1000_ERR_TIMEOUT)) {
5074                         E1000_ERR(hw->nic, "Valid Link not detected\n");
5075                 } else {
5076                         E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5077                 }
5078                 return 0;
5079         }
5080         e1000_configure_tx(hw);
5081         e1000_setup_rctl(hw);
5082         e1000_configure_rx(hw);
5083         return 1;
5084 }
5085
5086 /******************************************************************************
5087  * Gets the current PCI bus type of hardware
5088  *
5089  * hw - Struct containing variables accessed by shared code
5090  *****************************************************************************/
5091 void e1000_get_bus_type(struct e1000_hw *hw)
5092 {
5093         uint32_t status;
5094
5095         switch (hw->mac_type) {
5096         case e1000_82542_rev2_0:
5097         case e1000_82542_rev2_1:
5098                 hw->bus_type = e1000_bus_type_pci;
5099                 break;
5100         case e1000_82571:
5101         case e1000_82572:
5102         case e1000_82573:
5103         case e1000_82574:
5104         case e1000_80003es2lan:
5105                 hw->bus_type = e1000_bus_type_pci_express;
5106                 break;
5107         case e1000_ich8lan:
5108                 hw->bus_type = e1000_bus_type_pci_express;
5109                 break;
5110         default:
5111                 status = E1000_READ_REG(hw, STATUS);
5112                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5113                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5114                 break;
5115         }
5116 }
5117
5118 /* A list of all registered e1000 devices */
5119 static LIST_HEAD(e1000_hw_list);
5120
5121 /**************************************************************************
5122 PROBE - Look for an adapter, this routine's visible to the outside
5123 You should omit the last argument struct pci_device * for a non-PCI NIC
5124 ***************************************************************************/
5125 int
5126 e1000_initialize(bd_t * bis)
5127 {
5128         unsigned int i;
5129         pci_dev_t devno;
5130
5131         DEBUGFUNC();
5132
5133         /* Find and probe all the matching PCI devices */
5134         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5135                 u32 val;
5136
5137                 /*
5138                  * These will never get freed due to errors, this allows us to
5139                  * perform SPI EEPROM programming from U-boot, for example.
5140                  */
5141                 struct eth_device *nic = malloc(sizeof(*nic));
5142                 struct e1000_hw *hw = malloc(sizeof(*hw));
5143                 if (!nic || !hw) {
5144                         printf("e1000#%u: Out of Memory!\n", i);
5145                         free(nic);
5146                         free(hw);
5147                         continue;
5148                 }
5149
5150                 /* Make sure all of the fields are initially zeroed */
5151                 memset(nic, 0, sizeof(*nic));
5152                 memset(hw, 0, sizeof(*hw));
5153
5154                 /* Assign the passed-in values */
5155                 hw->cardnum = i;
5156                 hw->pdev = devno;
5157                 hw->nic = nic;
5158                 nic->priv = hw;
5159
5160                 /* Generate a card name */
5161                 sprintf(nic->name, "e1000#%u", hw->cardnum);
5162
5163                 /* Print a debug message with the IO base address */
5164                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5165                 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5166
5167                 /* Try to enable I/O accesses and bus-mastering */
5168                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5169                 pci_write_config_dword(devno, PCI_COMMAND, val);
5170
5171                 /* Make sure it worked */
5172                 pci_read_config_dword(devno, PCI_COMMAND, &val);
5173                 if (!(val & PCI_COMMAND_MEMORY)) {
5174                         E1000_ERR(nic, "Can't enable I/O memory\n");
5175                         continue;
5176                 }
5177                 if (!(val & PCI_COMMAND_MASTER)) {
5178                         E1000_ERR(nic, "Can't enable bus-mastering\n");
5179                         continue;
5180                 }
5181
5182                 /* Are these variables needed? */
5183                 hw->fc = e1000_fc_default;
5184                 hw->original_fc = e1000_fc_default;
5185                 hw->autoneg_failed = 0;
5186                 hw->autoneg = 1;
5187                 hw->get_link_status = TRUE;
5188                 hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5189                                                         PCI_REGION_MEM);
5190                 hw->mac_type = e1000_undefined;
5191
5192                 /* MAC and Phy settings */
5193                 if (e1000_sw_init(nic) < 0) {
5194                         E1000_ERR(nic, "Software init failed\n");
5195                         continue;
5196                 }
5197                 if (e1000_check_phy_reset_block(hw))
5198                         E1000_ERR(nic, "PHY Reset is blocked!\n");
5199
5200                 /* Basic init was OK, reset the hardware and allow SPI access */
5201                 e1000_reset_hw(hw);
5202                 list_add_tail(&hw->list_node, &e1000_hw_list);
5203
5204                 /* Validate the EEPROM and get chipset information */
5205 #if !defined(CONFIG_MVBC_1G)
5206                 if (e1000_init_eeprom_params(hw)) {
5207                         E1000_ERR(nic, "EEPROM is invalid!\n");
5208                         continue;
5209                 }
5210                 if (e1000_validate_eeprom_checksum(hw))
5211                         continue;
5212 #endif
5213                 e1000_read_mac_addr(nic);
5214                 e1000_get_bus_type(hw);
5215
5216                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5217                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5218                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5219
5220                 /* Set up the function pointers and register the device */
5221                 nic->init = e1000_init;
5222                 nic->recv = e1000_poll;
5223                 nic->send = e1000_transmit;
5224                 nic->halt = e1000_disable;
5225                 eth_register(nic);
5226         }
5227
5228         return i;
5229 }
5230
5231 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5232 {
5233         struct e1000_hw *hw;
5234
5235         list_for_each_entry(hw, &e1000_hw_list, list_node)
5236                 if (hw->cardnum == cardnum)
5237                         return hw;
5238
5239         return NULL;
5240 }
5241
5242 #ifdef CONFIG_CMD_E1000
5243 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5244                 int argc, char * const argv[])
5245 {
5246         struct e1000_hw *hw;
5247
5248         if (argc < 3) {
5249                 cmd_usage(cmdtp);
5250                 return 1;
5251         }
5252
5253         /* Make sure we can find the requested e1000 card */
5254         hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5255         if (!hw) {
5256                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5257                 return 1;
5258         }
5259
5260         if (!strcmp(argv[2], "print-mac-address")) {
5261                 unsigned char *mac = hw->nic->enetaddr;
5262                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5263                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5264                 return 0;
5265         }
5266
5267 #ifdef CONFIG_E1000_SPI
5268         /* Handle the "SPI" subcommand */
5269         if (!strcmp(argv[2], "spi"))
5270                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5271 #endif
5272
5273         cmd_usage(cmdtp);
5274         return 1;
5275 }
5276
5277 U_BOOT_CMD(
5278         e1000, 7, 0, do_e1000,
5279         "Intel e1000 controller management",
5280         /*  */"<card#> print-mac-address\n"
5281 #ifdef CONFIG_E1000_SPI
5282         "e1000 <card#> spi show [<offset> [<length>]]\n"
5283         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5284         "e1000 <card#> spi program <addr> <offset> <length>\n"
5285         "e1000 <card#> spi checksum [update]\n"
5286 #endif
5287         "       - Manage the Intel E1000 PCI device"
5288 );
5289 #endif /* not CONFIG_CMD_E1000 */