drivers/net/sh_eth.c

   1 /*
   2  * sh_eth.c - Driver for Renesas ethernet controler.
   3  *
   4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   5  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  * Copyright (C) 2013  Renesas Electronics Corporation
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <miiphy.h>
  18 #include <asm/errno.h>
  19 #include <asm/io.h>
  20
  21 #include "sh_eth.h"
  22
  23 #ifndef CONFIG_SH_ETHER_USE_PORT
  24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  25 #endif
  26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  28 #endif
  29
  30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
  31 #define flush_cache_wback(addr, len)    \
  32                 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
  33 #else
  34 #define flush_cache_wback(...)
  35 #endif
  36
  37 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  38 #define invalidate_cache(addr, len)             \
  39         {       \
  40                 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;    \
  41                 u32 start, end; \
  42                 \
  43                 start = (u32)addr;      \
  44                 end = start + len;      \
  45                 start &= ~(line_size - 1);      \
  46                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  47                 \
  48                 invalidate_dcache_range(start, end);    \
  49         }
  50 #else
  51 #define invalidate_cache(...)
  52 #endif
  53
  54 #define TIMEOUT_CNT 1000
  55
  56 int sh_eth_send(struct eth_device *dev, void *packet, int len)
  57 {
  58         struct sh_eth_dev *eth = dev->priv;
  59         int port = eth->port, ret = 0, timeout;
  60         struct sh_eth_info *port_info = &eth->port_info[port];
  61
  62         if (!packet || len > 0xffff) {
  63                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  64                 ret = -EINVAL;
  65                 goto err;
  66         }
  67
  68         /* packet must be a 4 byte boundary */
  69         if ((int)packet & 3) {
  70                 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
  71                 ret = -EFAULT;
  72                 goto err;
  73         }
  74
  75         /* Update tx descriptor */
  76         flush_cache_wback(packet, len);
  77         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  78         port_info->tx_desc_cur->td1 = len << 16;
  79         /* Must preserve the end of descriptor list indication */
  80         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  81                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  82         else
  83                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  84
  85         /* Restart the transmitter if disabled */
  86         if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
  87                 sh_eth_write(eth, EDTRR_TRNS, EDTRR);
  88
  89         /* Wait until packet is transmitted */
  90         timeout = TIMEOUT_CNT;
  91         do {
  92                 invalidate_cache(port_info->tx_desc_cur,
  93                                  sizeof(struct tx_desc_s));
  94                 udelay(100);
  95         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
  96
  97         if (timeout < 0) {
  98                 printf(SHETHER_NAME ": transmit timeout\n");
  99                 ret = -ETIMEDOUT;
 100                 goto err;
 101         }
 102
 103         port_info->tx_desc_cur++;
 104         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 105                 port_info->tx_desc_cur = port_info->tx_desc_base;
 106
 107 err:
 108         return ret;
 109 }
 110
 111 int sh_eth_recv(struct eth_device *dev)
 112 {
 113         struct sh_eth_dev *eth = dev->priv;
 114         int port = eth->port, len = 0;
 115         struct sh_eth_info *port_info = &eth->port_info[port];
 116         uchar *packet;
 117
 118         /* Check if the rx descriptor is ready */
 119         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 120         if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
 121                 /* Check for errors */
 122                 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
 123                         len = port_info->rx_desc_cur->rd1 & 0xffff;
 124                         packet = (uchar *)
 125                                 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 126                         invalidate_cache(packet, len);
 127                         NetReceive(packet, len);
 128                 }
 129
 130                 /* Make current descriptor available again */
 131                 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 132                         port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 133                 else
 134                         port_info->rx_desc_cur->rd0 = RD_RACT;
 135                 /* Point to the next descriptor */
 136                 port_info->rx_desc_cur++;
 137                 if (port_info->rx_desc_cur >=
 138                     port_info->rx_desc_base + NUM_RX_DESC)
 139                         port_info->rx_desc_cur = port_info->rx_desc_base;
 140         }
 141
 142         /* Restart the receiver if disabled */
 143         if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
 144                 sh_eth_write(eth, EDRRR_R, EDRRR);
 145
 146         return len;
 147 }
 148
 149 static int sh_eth_reset(struct sh_eth_dev *eth)
 150 {
 151 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 152         int ret = 0, i;
 153
 154         /* Start e-dmac transmitter and receiver */
 155         sh_eth_write(eth, EDSR_ENALL, EDSR);
 156
 157         /* Perform a software reset and wait for it to complete */
 158         sh_eth_write(eth, EDMR_SRST, EDMR);
 159         for (i = 0; i < TIMEOUT_CNT ; i++) {
 160                 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
 161                         break;
 162                 udelay(1000);
 163         }
 164
 165         if (i == TIMEOUT_CNT) {
 166                 printf(SHETHER_NAME  ": Software reset timeout\n");
 167                 ret = -EIO;
 168         }
 169
 170         return ret;
 171 #else
 172         sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
 173         udelay(3000);
 174         sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
 175
 176         return 0;
 177 #endif
 178 }
 179
 180 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 181 {
 182         int port = eth->port, i, ret = 0;
 183         u32 tmp_addr;
 184         struct sh_eth_info *port_info = &eth->port_info[port];
 185         struct tx_desc_s *cur_tx_desc;
 186
 187         /*
 188          * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
 189          */
 190         port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
 191                                                  sizeof(struct tx_desc_s) +
 192                                                  TX_DESC_SIZE - 1);
 193         if (!port_info->tx_desc_malloc) {
 194                 printf(SHETHER_NAME ": malloc failed\n");
 195                 ret = -ENOMEM;
 196                 goto err;
 197         }
 198
 199         tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
 200                           ~(TX_DESC_SIZE - 1));
 201         flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
 202         /* Make sure we use a P2 address (non-cacheable) */
 203         port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
 204         port_info->tx_desc_cur = port_info->tx_desc_base;
 205
 206         /* Initialize all descriptors */
 207         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 208              cur_tx_desc++, i++) {
 209                 cur_tx_desc->td0 = 0x00;
 210                 cur_tx_desc->td1 = 0x00;
 211                 cur_tx_desc->td2 = 0x00;
 212         }
 213
 214         /* Mark the end of the descriptors */
 215         cur_tx_desc--;
 216         cur_tx_desc->td0 |= TD_TDLE;
 217
 218         /* Point the controller to the tx descriptor list. Must use physical
 219            addresses */
 220         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 221 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 222         sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 223         sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 224         sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
 225 #endif
 226
 227 err:
 228         return ret;
 229 }
 230
 231 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 232 {
 233         int port = eth->port, i , ret = 0;
 234         struct sh_eth_info *port_info = &eth->port_info[port];
 235         struct rx_desc_s *cur_rx_desc;
 236         u32 tmp_addr;
 237         u8 *rx_buf;
 238
 239         /*
 240          * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
 241          */
 242         port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
 243                                                  sizeof(struct rx_desc_s) +
 244                                                  RX_DESC_SIZE - 1);
 245         if (!port_info->rx_desc_malloc) {
 246                 printf(SHETHER_NAME ": malloc failed\n");
 247                 ret = -ENOMEM;
 248                 goto err;
 249         }
 250
 251         tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
 252                           ~(RX_DESC_SIZE - 1));
 253         flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
 254         /* Make sure we use a P2 address (non-cacheable) */
 255         port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
 256
 257         port_info->rx_desc_cur = port_info->rx_desc_base;
 258
 259         /*
 260          * Allocate rx data buffers. They must be 32 bytes aligned  and in
 261          * P2 area
 262          */
 263         port_info->rx_buf_malloc = malloc(
 264                 NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
 265         if (!port_info->rx_buf_malloc) {
 266                 printf(SHETHER_NAME ": malloc failed\n");
 267                 ret = -ENOMEM;
 268                 goto err_buf_malloc;
 269         }
 270
 271         tmp_addr = (u32)(((int)port_info->rx_buf_malloc
 272                           + (RX_BUF_ALIGNE_SIZE - 1)) &
 273                           ~(RX_BUF_ALIGNE_SIZE - 1));
 274         port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
 275
 276         /* Initialize all descriptors */
 277         for (cur_rx_desc = port_info->rx_desc_base,
 278              rx_buf = port_info->rx_buf_base, i = 0;
 279              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 280                 cur_rx_desc->rd0 = RD_RACT;
 281                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 282                 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
 283         }
 284
 285         /* Mark the end of the descriptors */
 286         cur_rx_desc--;
 287         cur_rx_desc->rd0 |= RD_RDLE;
 288
 289         /* Point the controller to the rx descriptor list */
 290         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 291 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 292         sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 293         sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 294         sh_eth_write(eth, RDFFR_RDLF, RDFFR);
 295 #endif
 296
 297         return ret;
 298
 299 err_buf_malloc:
 300         free(port_info->rx_desc_malloc);
 301         port_info->rx_desc_malloc = NULL;
 302
 303 err:
 304         return ret;
 305 }
 306
 307 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 308 {
 309         int port = eth->port;
 310         struct sh_eth_info *port_info = &eth->port_info[port];
 311
 312         if (port_info->tx_desc_malloc) {
 313                 free(port_info->tx_desc_malloc);
 314                 port_info->tx_desc_malloc = NULL;
 315         }
 316 }
 317
 318 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 319 {
 320         int port = eth->port;
 321         struct sh_eth_info *port_info = &eth->port_info[port];
 322
 323         if (port_info->rx_desc_malloc) {
 324                 free(port_info->rx_desc_malloc);
 325                 port_info->rx_desc_malloc = NULL;
 326         }
 327
 328         if (port_info->rx_buf_malloc) {
 329                 free(port_info->rx_buf_malloc);
 330                 port_info->rx_buf_malloc = NULL;
 331         }
 332 }
 333
 334 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 335 {
 336         int ret = 0;
 337
 338         ret = sh_eth_tx_desc_init(eth);
 339         if (ret)
 340                 goto err_tx_init;
 341
 342         ret = sh_eth_rx_desc_init(eth);
 343         if (ret)
 344                 goto err_rx_init;
 345
 346         return ret;
 347 err_rx_init:
 348         sh_eth_tx_desc_free(eth);
 349
 350 err_tx_init:
 351         return ret;
 352 }
 353
 354 static int sh_eth_phy_config(struct sh_eth_dev *eth)
 355 {
 356         int port = eth->port, ret = 0;
 357         struct sh_eth_info *port_info = &eth->port_info[port];
 358         struct eth_device *dev = port_info->dev;
 359         struct phy_device *phydev;
 360
 361         phydev = phy_connect(
 362                         miiphy_get_dev_by_name(dev->name),
 363                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 364         port_info->phydev = phydev;
 365         phy_config(phydev);
 366
 367         return ret;
 368 }
 369
 370 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 371 {
 372         int port = eth->port, ret = 0;
 373         u32 val;
 374         struct sh_eth_info *port_info = &eth->port_info[port];
 375         struct eth_device *dev = port_info->dev;
 376         struct phy_device *phy;
 377
 378         /* Configure e-dmac registers */
 379         sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
 380                         (EMDR_DESC | EDMR_EL), EDMR);
 381
 382         sh_eth_write(eth, 0, EESIPR);
 383         sh_eth_write(eth, 0, TRSCER);
 384         sh_eth_write(eth, 0, TFTR);
 385         sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 386         sh_eth_write(eth, RMCR_RST, RMCR);
 387 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 388         sh_eth_write(eth, 0, RPADIR);
 389 #endif
 390         sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 391
 392         /* Configure e-mac registers */
 393         sh_eth_write(eth, 0, ECSIPR);
 394
 395         /* Set Mac address */
 396         val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 397             dev->enetaddr[2] << 8 | dev->enetaddr[3];
 398         sh_eth_write(eth, val, MAHR);
 399
 400         val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
 401         sh_eth_write(eth, val, MALR);
 402
 403         sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
 404 #if defined(SH_ETH_TYPE_GETHER)
 405         sh_eth_write(eth, 0, PIPR);
 406 #endif
 407 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 408         sh_eth_write(eth, APR_AP, APR);
 409         sh_eth_write(eth, MPR_MP, MPR);
 410         sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
 411 #endif
 412
 413 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 414         sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 415 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
 416         sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
 417 #endif
 418         /* Configure phy */
 419         ret = sh_eth_phy_config(eth);
 420         if (ret) {
 421                 printf(SHETHER_NAME ": phy config timeout\n");
 422                 goto err_phy_cfg;
 423         }
 424         phy = port_info->phydev;
 425         ret = phy_startup(phy);
 426         if (ret) {
 427                 printf(SHETHER_NAME ": phy startup failure\n");
 428                 return ret;
 429         }
 430
 431         val = 0;
 432
 433         /* Set the transfer speed */
 434         if (phy->speed == 100) {
 435                 printf(SHETHER_NAME ": 100Base/");
 436 #if defined(SH_ETH_TYPE_GETHER)
 437                 sh_eth_write(eth, GECMR_100B, GECMR);
 438 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 439                 sh_eth_write(eth, 1, RTRATE);
 440 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
 441                 defined(CONFIG_R8A7791)
 442                 val = ECMR_RTM;
 443 #endif
 444         } else if (phy->speed == 10) {
 445                 printf(SHETHER_NAME ": 10Base/");
 446 #if defined(SH_ETH_TYPE_GETHER)
 447                 sh_eth_write(eth, GECMR_10B, GECMR);
 448 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 449                 sh_eth_write(eth, 0, RTRATE);
 450 #endif
 451         }
 452 #if defined(SH_ETH_TYPE_GETHER)
 453         else if (phy->speed == 1000) {
 454                 printf(SHETHER_NAME ": 1000Base/");
 455                 sh_eth_write(eth, GECMR_1000B, GECMR);
 456         }
 457 #endif
 458
 459         /* Check if full duplex mode is supported by the phy */
 460         if (phy->duplex) {
 461                 printf("Full\n");
 462                 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
 463                              ECMR);
 464         } else {
 465                 printf("Half\n");
 466                 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
 467         }
 468
 469         return ret;
 470
 471 err_phy_cfg:
 472         return ret;
 473 }
 474
 475 static void sh_eth_start(struct sh_eth_dev *eth)
 476 {
 477         /*
 478          * Enable the e-dmac receiver only. The transmitter will be enabled when
 479          * we have something to transmit
 480          */
 481         sh_eth_write(eth, EDRRR_R, EDRRR);
 482 }
 483
 484 static void sh_eth_stop(struct sh_eth_dev *eth)
 485 {
 486         sh_eth_write(eth, ~EDRRR_R, EDRRR);
 487 }
 488
 489 int sh_eth_init(struct eth_device *dev, bd_t *bd)
 490 {
 491         int ret = 0;
 492         struct sh_eth_dev *eth = dev->priv;
 493
 494         ret = sh_eth_reset(eth);
 495         if (ret)
 496                 goto err;
 497
 498         ret = sh_eth_desc_init(eth);
 499         if (ret)
 500                 goto err;
 501
 502         ret = sh_eth_config(eth, bd);
 503         if (ret)
 504                 goto err_config;
 505
 506         sh_eth_start(eth);
 507
 508         return ret;
 509
 510 err_config:
 511         sh_eth_tx_desc_free(eth);
 512         sh_eth_rx_desc_free(eth);
 513
 514 err:
 515         return ret;
 516 }
 517
 518 void sh_eth_halt(struct eth_device *dev)
 519 {
 520         struct sh_eth_dev *eth = dev->priv;
 521         sh_eth_stop(eth);
 522 }
 523
 524 int sh_eth_initialize(bd_t *bd)
 525 {
 526     int ret = 0;
 527         struct sh_eth_dev *eth = NULL;
 528     struct eth_device *dev = NULL;
 529
 530     eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 531         if (!eth) {
 532                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 533                 ret = -ENOMEM;
 534                 goto err;
 535         }
 536
 537     dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 538         if (!dev) {
 539                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 540                 ret = -ENOMEM;
 541                 goto err;
 542         }
 543     memset(dev, 0, sizeof(struct eth_device));
 544     memset(eth, 0, sizeof(struct sh_eth_dev));
 545
 546         eth->port = CONFIG_SH_ETHER_USE_PORT;
 547         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 548
 549     dev->priv = (void *)eth;
 550     dev->iobase = 0;
 551     dev->init = sh_eth_init;
 552     dev->halt = sh_eth_halt;
 553     dev->send = sh_eth_send;
 554     dev->recv = sh_eth_recv;
 555     eth->port_info[eth->port].dev = dev;
 556
 557         sprintf(dev->name, SHETHER_NAME);
 558
 559     /* Register Device to EtherNet subsystem  */
 560     eth_register(dev);
 561
 562         bb_miiphy_buses[0].priv = eth;
 563         miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
 564
 565         if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
 566                 puts("Please set MAC address\n");
 567
 568         return ret;
 569
 570 err:
 571         if (dev)
 572                 free(dev);
 573
 574         if (eth)
 575                 free(eth);
 576
 577         printf(SHETHER_NAME ": Failed\n");
 578         return ret;
 579 }
 580
 581 /******* for bb_miiphy *******/
 582 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 583 {
 584         return 0;
 585 }
 586
 587 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 588 {
 589         struct sh_eth_dev *eth = bus->priv;
 590
 591         sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
 592
 593         return 0;
 594 }
 595
 596 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 597 {
 598         struct sh_eth_dev *eth = bus->priv;
 599
 600         sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
 601
 602         return 0;
 603 }
 604
 605 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 606 {
 607         struct sh_eth_dev *eth = bus->priv;
 608
 609         if (v)
 610                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
 611         else
 612                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
 613
 614         return 0;
 615 }
 616
 617 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 618 {
 619         struct sh_eth_dev *eth = bus->priv;
 620
 621         *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
 622
 623         return 0;
 624 }
 625
 626 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 627 {
 628         struct sh_eth_dev *eth = bus->priv;
 629
 630         if (v)
 631                 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
 632         else
 633                 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
 634
 635         return 0;
 636 }
 637
 638 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 639 {
 640         udelay(10);
 641
 642         return 0;
 643 }
 644
 645 struct bb_miiphy_bus bb_miiphy_buses[] = {
 646         {
 647                 .name           = "sh_eth",
 648                 .init           = sh_eth_bb_init,
 649                 .mdio_active    = sh_eth_bb_mdio_active,
 650                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 651                 .set_mdio       = sh_eth_bb_set_mdio,
 652                 .get_mdio       = sh_eth_bb_get_mdio,
 653                 .set_mdc        = sh_eth_bb_set_mdc,
 654                 .delay          = sh_eth_bb_delay,
 655         }
 656 };
 657 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);