drivers/net/smc911x.h

   1 /*
   2  * SMSC LAN9[12]1[567] Network driver
   3  *
   4  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _SMC911X_H_
  26 #define _SMC911X_H_
  27
  28 #include <linux/types.h>
  29
  30 #if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
  31         defined (CONFIG_DRIVER_SMC911X_16_BIT)
  32 #error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
  33         CONFIG_DRIVER_SMC911X_16_BIT shall be set"
  34 #endif
  35
  36 #if defined (CONFIG_DRIVER_SMC911X_32_BIT)
  37 static inline u32 __smc911x_reg_read(u32 addr)
  38 {
  39         return *(volatile u32*)addr;
  40 }
  41 u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read")));
  42
  43 static inline void __smc911x_reg_write(u32 addr, u32 val)
  44 {
  45         *(volatile u32*)addr = val;
  46 }
  47 void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write")));
  48 #elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
  49 static inline u32 smc911x_reg_read(u32 addr)
  50 {
  51         volatile u16 *addr_16 = (u16 *)addr;
  52         return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  53 }
  54 static inline void smc911x_reg_write(u32 addr, u32 val)
  55 {
  56         *(volatile u16*)addr = (u16)val;
  57         *(volatile u16*)(addr + 2) = (u16)(val >> 16);
  58 }
  59 #else
  60 #error "SMC911X: undefined bus width"
  61 #endif /* CONFIG_DRIVER_SMC911X_16_BIT */
  62
  63 /* Below are the register offsets and bit definitions
  64  * of the Lan911x memory space
  65  */
  66 #define RX_DATA_FIFO             (CONFIG_DRIVER_SMC911X_BASE + 0x00)
  67
  68 #define TX_DATA_FIFO             (CONFIG_DRIVER_SMC911X_BASE + 0x20)
  69 #define TX_CMD_A_INT_ON_COMP                    0x80000000
  70 #define TX_CMD_A_INT_BUF_END_ALGN               0x03000000
  71 #define TX_CMD_A_INT_4_BYTE_ALGN                0x00000000
  72 #define TX_CMD_A_INT_16_BYTE_ALGN               0x01000000
  73 #define TX_CMD_A_INT_32_BYTE_ALGN               0x02000000
  74 #define TX_CMD_A_INT_DATA_OFFSET                0x001F0000
  75 #define TX_CMD_A_INT_FIRST_SEG                  0x00002000
  76 #define TX_CMD_A_INT_LAST_SEG                   0x00001000
  77 #define TX_CMD_A_BUF_SIZE                       0x000007FF
  78 #define TX_CMD_B_PKT_TAG                        0xFFFF0000
  79 #define TX_CMD_B_ADD_CRC_DISABLE                0x00002000
  80 #define TX_CMD_B_DISABLE_PADDING                0x00001000
  81 #define TX_CMD_B_PKT_BYTE_LENGTH                0x000007FF
  82
  83 #define RX_STATUS_FIFO          (CONFIG_DRIVER_SMC911X_BASE + 0x40)
  84 #define RX_STS_PKT_LEN                          0x3FFF0000
  85 #define RX_STS_ES                               0x00008000
  86 #define RX_STS_BCST                             0x00002000
  87 #define RX_STS_LEN_ERR                          0x00001000
  88 #define RX_STS_RUNT_ERR                         0x00000800
  89 #define RX_STS_MCAST                            0x00000400
  90 #define RX_STS_TOO_LONG                         0x00000080
  91 #define RX_STS_COLL                             0x00000040
  92 #define RX_STS_ETH_TYPE                         0x00000020
  93 #define RX_STS_WDOG_TMT                         0x00000010
  94 #define RX_STS_MII_ERR                          0x00000008
  95 #define RX_STS_DRIBBLING                        0x00000004
  96 #define RX_STS_CRC_ERR                          0x00000002
  97 #define RX_STATUS_FIFO_PEEK     (CONFIG_DRIVER_SMC911X_BASE + 0x44)
  98 #define TX_STATUS_FIFO          (CONFIG_DRIVER_SMC911X_BASE + 0x48)
  99 #define TX_STS_TAG                              0xFFFF0000
 100 #define TX_STS_ES                               0x00008000
 101 #define TX_STS_LOC                              0x00000800
 102 #define TX_STS_NO_CARR                          0x00000400
 103 #define TX_STS_LATE_COLL                        0x00000200
 104 #define TX_STS_MANY_COLL                        0x00000100
 105 #define TX_STS_COLL_CNT                         0x00000078
 106 #define TX_STS_MANY_DEFER                       0x00000004
 107 #define TX_STS_UNDERRUN                         0x00000002
 108 #define TX_STS_DEFERRED                         0x00000001
 109 #define TX_STATUS_FIFO_PEEK     (CONFIG_DRIVER_SMC911X_BASE + 0x4C)
 110 #define ID_REV                  (CONFIG_DRIVER_SMC911X_BASE + 0x50)
 111 #define ID_REV_CHIP_ID                          0xFFFF0000  /* RO */
 112 #define ID_REV_REV_ID                           0x0000FFFF  /* RO */
 113
 114 #define INT_CFG                 (CONFIG_DRIVER_SMC911X_BASE + 0x54)
 115 #define INT_CFG_INT_DEAS                        0xFF000000  /* R/W */
 116 #define INT_CFG_INT_DEAS_CLR                    0x00004000
 117 #define INT_CFG_INT_DEAS_STS                    0x00002000
 118 #define INT_CFG_IRQ_INT                         0x00001000  /* RO */
 119 #define INT_CFG_IRQ_EN                          0x00000100  /* R/W */
 120 #define INT_CFG_IRQ_POL                         0x00000010  /* R/W Not Affected by SW Reset */
 121 #define INT_CFG_IRQ_TYPE                        0x00000001  /* R/W Not Affected by SW Reset */
 122
 123 #define INT_STS                 (CONFIG_DRIVER_SMC911X_BASE + 0x58)
 124 #define INT_STS_SW_INT                          0x80000000  /* R/WC */
 125 #define INT_STS_TXSTOP_INT                      0x02000000  /* R/WC */
 126 #define INT_STS_RXSTOP_INT                      0x01000000  /* R/WC */
 127 #define INT_STS_RXDFH_INT                       0x00800000  /* R/WC */
 128 #define INT_STS_RXDF_INT                        0x00400000  /* R/WC */
 129 #define INT_STS_TX_IOC                          0x00200000  /* R/WC */
 130 #define INT_STS_RXD_INT                         0x00100000  /* R/WC */
 131 #define INT_STS_GPT_INT                         0x00080000  /* R/WC */
 132 #define INT_STS_PHY_INT                         0x00040000  /* RO */
 133 #define INT_STS_PME_INT                         0x00020000  /* R/WC */
 134 #define INT_STS_TXSO                            0x00010000  /* R/WC */
 135 #define INT_STS_RWT                             0x00008000  /* R/WC */
 136 #define INT_STS_RXE                             0x00004000  /* R/WC */
 137 #define INT_STS_TXE                             0x00002000  /* R/WC */
 138 /*#define       INT_STS_ERX             0x00001000*/  /* R/WC */
 139 #define INT_STS_TDFU                            0x00000800  /* R/WC */
 140 #define INT_STS_TDFO                            0x00000400  /* R/WC */
 141 #define INT_STS_TDFA                            0x00000200  /* R/WC */
 142 #define INT_STS_TSFF                            0x00000100  /* R/WC */
 143 #define INT_STS_TSFL                            0x00000080  /* R/WC */
 144 /*#define       INT_STS_RXDF            0x00000040*/  /* R/WC */
 145 #define INT_STS_RDFO                            0x00000040  /* R/WC */
 146 #define INT_STS_RDFL                            0x00000020  /* R/WC */
 147 #define INT_STS_RSFF                            0x00000010  /* R/WC */
 148 #define INT_STS_RSFL                            0x00000008  /* R/WC */
 149 #define INT_STS_GPIO2_INT                       0x00000004  /* R/WC */
 150 #define INT_STS_GPIO1_INT                       0x00000002  /* R/WC */
 151 #define INT_STS_GPIO0_INT                       0x00000001  /* R/WC */
 152 #define INT_EN                  (CONFIG_DRIVER_SMC911X_BASE + 0x5C)
 153 #define INT_EN_SW_INT_EN                        0x80000000  /* R/W */
 154 #define INT_EN_TXSTOP_INT_EN                    0x02000000  /* R/W */
 155 #define INT_EN_RXSTOP_INT_EN                    0x01000000  /* R/W */
 156 #define INT_EN_RXDFH_INT_EN                     0x00800000  /* R/W */
 157 /*#define       INT_EN_RXDF_INT_EN              0x00400000*/  /* R/W */
 158 #define INT_EN_TIOC_INT_EN                      0x00200000  /* R/W */
 159 #define INT_EN_RXD_INT_EN                       0x00100000  /* R/W */
 160 #define INT_EN_GPT_INT_EN                       0x00080000  /* R/W */
 161 #define INT_EN_PHY_INT_EN                       0x00040000  /* R/W */
 162 #define INT_EN_PME_INT_EN                       0x00020000  /* R/W */
 163 #define INT_EN_TXSO_EN                          0x00010000  /* R/W */
 164 #define INT_EN_RWT_EN                           0x00008000  /* R/W */
 165 #define INT_EN_RXE_EN                           0x00004000  /* R/W */
 166 #define INT_EN_TXE_EN                           0x00002000  /* R/W */
 167 /*#define       INT_EN_ERX_EN                   0x00001000*/  /* R/W */
 168 #define INT_EN_TDFU_EN                          0x00000800  /* R/W */
 169 #define INT_EN_TDFO_EN                          0x00000400  /* R/W */
 170 #define INT_EN_TDFA_EN                          0x00000200  /* R/W */
 171 #define INT_EN_TSFF_EN                          0x00000100  /* R/W */
 172 #define INT_EN_TSFL_EN                          0x00000080  /* R/W */
 173 /*#define       INT_EN_RXDF_EN                  0x00000040*/  /* R/W */
 174 #define INT_EN_RDFO_EN                          0x00000040  /* R/W */
 175 #define INT_EN_RDFL_EN                          0x00000020  /* R/W */
 176 #define INT_EN_RSFF_EN                          0x00000010  /* R/W */
 177 #define INT_EN_RSFL_EN                          0x00000008  /* R/W */
 178 #define INT_EN_GPIO2_INT                        0x00000004  /* R/W */
 179 #define INT_EN_GPIO1_INT                        0x00000002  /* R/W */
 180 #define INT_EN_GPIO0_INT                        0x00000001  /* R/W */
 181
 182 #define BYTE_TEST               (CONFIG_DRIVER_SMC911X_BASE + 0x64)
 183 #define FIFO_INT                (CONFIG_DRIVER_SMC911X_BASE + 0x68)
 184 #define FIFO_INT_TX_AVAIL_LEVEL                 0xFF000000  /* R/W */
 185 #define FIFO_INT_TX_STS_LEVEL                   0x00FF0000  /* R/W */
 186 #define FIFO_INT_RX_AVAIL_LEVEL                 0x0000FF00  /* R/W */
 187 #define FIFO_INT_RX_STS_LEVEL                   0x000000FF  /* R/W */
 188
 189 #define RX_CFG                  (CONFIG_DRIVER_SMC911X_BASE + 0x6C)
 190 #define RX_CFG_RX_END_ALGN                      0xC0000000  /* R/W */
 191 #define         RX_CFG_RX_END_ALGN4             0x00000000  /* R/W */
 192 #define         RX_CFG_RX_END_ALGN16            0x40000000  /* R/W */
 193 #define         RX_CFG_RX_END_ALGN32            0x80000000  /* R/W */
 194 #define RX_CFG_RX_DMA_CNT                       0x0FFF0000  /* R/W */
 195 #define RX_CFG_RX_DUMP                          0x00008000  /* R/W */
 196 #define RX_CFG_RXDOFF                           0x00001F00  /* R/W */
 197 /*#define       RX_CFG_RXBAD                    0x00000001*/  /* R/W */
 198
 199 #define TX_CFG                  (CONFIG_DRIVER_SMC911X_BASE + 0x70)
 200 /*#define       TX_CFG_TX_DMA_LVL               0xE0000000*/     /* R/W */
 201 /*#define       TX_CFG_TX_DMA_CNT               0x0FFF0000*/     /* R/W Self Clearing */
 202 #define TX_CFG_TXS_DUMP                         0x00008000  /* Self Clearing */
 203 #define TX_CFG_TXD_DUMP                         0x00004000  /* Self Clearing */
 204 #define TX_CFG_TXSAO                            0x00000004  /* R/W */
 205 #define TX_CFG_TX_ON                            0x00000002  /* R/W */
 206 #define TX_CFG_STOP_TX                          0x00000001  /* Self Clearing */
 207
 208 #define HW_CFG                  (CONFIG_DRIVER_SMC911X_BASE + 0x74)
 209 #define HW_CFG_TTM                              0x00200000  /* R/W */
 210 #define HW_CFG_SF                               0x00100000  /* R/W */
 211 #define HW_CFG_TX_FIF_SZ                        0x000F0000  /* R/W */
 212 #define HW_CFG_TR                               0x00003000  /* R/W */
 213 #define HW_CFG_PHY_CLK_SEL                      0x00000060  /* R/W */
 214 #define HW_CFG_PHY_CLK_SEL_INT_PHY              0x00000000 /* R/W */
 215 #define HW_CFG_PHY_CLK_SEL_EXT_PHY              0x00000020 /* R/W */
 216 #define HW_CFG_PHY_CLK_SEL_CLK_DIS              0x00000040 /* R/W */
 217 #define HW_CFG_SMI_SEL                          0x00000010  /* R/W */
 218 #define HW_CFG_EXT_PHY_DET                      0x00000008  /* RO */
 219 #define HW_CFG_EXT_PHY_EN                       0x00000004  /* R/W */
 220 #define HW_CFG_32_16_BIT_MODE                   0x00000004  /* RO */
 221 #define HW_CFG_SRST_TO                          0x00000002  /* RO */
 222 #define HW_CFG_SRST                             0x00000001  /* Self Clearing */
 223
 224 #define RX_DP_CTRL              (CONFIG_DRIVER_SMC911X_BASE + 0x78)
 225 #define RX_DP_CTRL_RX_FFWD                      0x80000000  /* R/W */
 226 #define RX_DP_CTRL_FFWD_BUSY                    0x80000000  /* RO */
 227
 228 #define RX_FIFO_INF             (CONFIG_DRIVER_SMC911X_BASE + 0x7C)
 229 #define  RX_FIFO_INF_RXSUSED                    0x00FF0000  /* RO */
 230 #define  RX_FIFO_INF_RXDUSED                    0x0000FFFF  /* RO */
 231
 232 #define TX_FIFO_INF             (CONFIG_DRIVER_SMC911X_BASE + 0x80)
 233 #define TX_FIFO_INF_TSUSED                      0x00FF0000  /* RO */
 234 #define TX_FIFO_INF_TDFREE                      0x0000FFFF  /* RO */
 235
 236 #define PMT_CTRL                (CONFIG_DRIVER_SMC911X_BASE + 0x84)
 237 #define PMT_CTRL_PM_MODE                        0x00003000  /* Self Clearing */
 238 #define PMT_CTRL_PHY_RST                        0x00000400  /* Self Clearing */
 239 #define PMT_CTRL_WOL_EN                         0x00000200  /* R/W */
 240 #define PMT_CTRL_ED_EN                          0x00000100  /* R/W */
 241 #define PMT_CTRL_PME_TYPE                       0x00000040  /* R/W Not Affected by SW Reset */
 242 #define PMT_CTRL_WUPS                           0x00000030  /* R/WC */
 243 #define PMT_CTRL_WUPS_NOWAKE                    0x00000000  /* R/WC */
 244 #define PMT_CTRL_WUPS_ED                        0x00000010  /* R/WC */
 245 #define PMT_CTRL_WUPS_WOL                       0x00000020  /* R/WC */
 246 #define PMT_CTRL_WUPS_MULTI                     0x00000030  /* R/WC */
 247 #define PMT_CTRL_PME_IND                        0x00000008  /* R/W */
 248 #define PMT_CTRL_PME_POL                        0x00000004  /* R/W */
 249 #define PMT_CTRL_PME_EN                         0x00000002  /* R/W Not Affected by SW Reset */
 250 #define PMT_CTRL_READY                          0x00000001  /* RO */
 251
 252 #define GPIO_CFG                (CONFIG_DRIVER_SMC911X_BASE + 0x88)
 253 #define GPIO_CFG_LED3_EN                        0x40000000  /* R/W */
 254 #define GPIO_CFG_LED2_EN                        0x20000000  /* R/W */
 255 #define GPIO_CFG_LED1_EN                        0x10000000  /* R/W */
 256 #define GPIO_CFG_GPIO2_INT_POL                  0x04000000  /* R/W */
 257 #define GPIO_CFG_GPIO1_INT_POL                  0x02000000  /* R/W */
 258 #define GPIO_CFG_GPIO0_INT_POL                  0x01000000  /* R/W */
 259 #define GPIO_CFG_EEPR_EN                        0x00700000  /* R/W */
 260 #define GPIO_CFG_GPIOBUF2                       0x00040000  /* R/W */
 261 #define GPIO_CFG_GPIOBUF1                       0x00020000  /* R/W */
 262 #define GPIO_CFG_GPIOBUF0                       0x00010000  /* R/W */
 263 #define GPIO_CFG_GPIODIR2                       0x00000400  /* R/W */
 264 #define GPIO_CFG_GPIODIR1                       0x00000200  /* R/W */
 265 #define GPIO_CFG_GPIODIR0                       0x00000100  /* R/W */
 266 #define GPIO_CFG_GPIOD4                         0x00000010  /* R/W */
 267 #define GPIO_CFG_GPIOD3                         0x00000008  /* R/W */
 268 #define GPIO_CFG_GPIOD2                         0x00000004  /* R/W */
 269 #define GPIO_CFG_GPIOD1                         0x00000002  /* R/W */
 270 #define GPIO_CFG_GPIOD0                         0x00000001  /* R/W */
 271
 272 #define GPT_CFG                 (CONFIG_DRIVER_SMC911X_BASE + 0x8C)
 273 #define GPT_CFG_TIMER_EN                        0x20000000  /* R/W */
 274 #define GPT_CFG_GPT_LOAD                        0x0000FFFF  /* R/W */
 275
 276 #define GPT_CNT                 (CONFIG_DRIVER_SMC911X_BASE + 0x90)
 277 #define GPT_CNT_GPT_CNT                         0x0000FFFF  /* RO */
 278
 279 #define ENDIAN                  (CONFIG_DRIVER_SMC911X_BASE + 0x98)
 280 #define FREE_RUN                (CONFIG_DRIVER_SMC911X_BASE + 0x9C)
 281 #define RX_DROP                 (CONFIG_DRIVER_SMC911X_BASE + 0xA0)
 282 #define MAC_CSR_CMD             (CONFIG_DRIVER_SMC911X_BASE + 0xA4)
 283 #define  MAC_CSR_CMD_CSR_BUSY                   0x80000000  /* Self Clearing */
 284 #define  MAC_CSR_CMD_R_NOT_W                    0x40000000  /* R/W */
 285 #define  MAC_CSR_CMD_CSR_ADDR                   0x000000FF  /* R/W */
 286
 287 #define MAC_CSR_DATA            (CONFIG_DRIVER_SMC911X_BASE + 0xA8)
 288 #define AFC_CFG                 (CONFIG_DRIVER_SMC911X_BASE + 0xAC)
 289 #define         AFC_CFG_AFC_HI                  0x00FF0000  /* R/W */
 290 #define         AFC_CFG_AFC_LO                  0x0000FF00  /* R/W */
 291 #define         AFC_CFG_BACK_DUR                0x000000F0  /* R/W */
 292 #define         AFC_CFG_FCMULT                  0x00000008  /* R/W */
 293 #define         AFC_CFG_FCBRD                   0x00000004  /* R/W */
 294 #define         AFC_CFG_FCADD                   0x00000002  /* R/W */
 295 #define         AFC_CFG_FCANY                   0x00000001  /* R/W */
 296
 297 #define E2P_CMD                 (CONFIG_DRIVER_SMC911X_BASE + 0xB0)
 298 #define         E2P_CMD_EPC_BUSY                0x80000000  /* Self Clearing */
 299 #define         E2P_CMD_EPC_CMD                 0x70000000  /* R/W */
 300 #define         E2P_CMD_EPC_CMD_READ            0x00000000  /* R/W */
 301 #define         E2P_CMD_EPC_CMD_EWDS            0x10000000  /* R/W */
 302 #define         E2P_CMD_EPC_CMD_EWEN            0x20000000  /* R/W */
 303 #define         E2P_CMD_EPC_CMD_WRITE           0x30000000  /* R/W */
 304 #define         E2P_CMD_EPC_CMD_WRAL            0x40000000  /* R/W */
 305 #define         E2P_CMD_EPC_CMD_ERASE           0x50000000  /* R/W */
 306 #define         E2P_CMD_EPC_CMD_ERAL            0x60000000  /* R/W */
 307 #define         E2P_CMD_EPC_CMD_RELOAD          0x70000000  /* R/W */
 308 #define         E2P_CMD_EPC_TIMEOUT             0x00000200  /* RO */
 309 #define         E2P_CMD_MAC_ADDR_LOADED         0x00000100  /* RO */
 310 #define         E2P_CMD_EPC_ADDR                0x000000FF  /* R/W */
 311
 312 #define E2P_DATA                (CONFIG_DRIVER_SMC911X_BASE + 0xB4)
 313 #define E2P_DATA_EEPROM_DATA                    0x000000FF  /* R/W */
 314 /* end of LAN register offsets and bit definitions */
 315
 316 /* MAC Control and Status registers */
 317 #define MAC_CR                  0x01  /* R/W */
 318
 319 /* MAC_CR - MAC Control Register */
 320 #define MAC_CR_RXALL                    0x80000000
 321 /* TODO: delete this bit? It is not described in the data sheet. */
 322 #define MAC_CR_HBDIS                    0x10000000
 323 #define MAC_CR_RCVOWN                   0x00800000
 324 #define MAC_CR_LOOPBK                   0x00200000
 325 #define MAC_CR_FDPX                     0x00100000
 326 #define MAC_CR_MCPAS                    0x00080000
 327 #define MAC_CR_PRMS                     0x00040000
 328 #define MAC_CR_INVFILT                  0x00020000
 329 #define MAC_CR_PASSBAD                  0x00010000
 330 #define MAC_CR_HFILT                    0x00008000
 331 #define MAC_CR_HPFILT                   0x00002000
 332 #define MAC_CR_LCOLL                    0x00001000
 333 #define MAC_CR_BCAST                    0x00000800
 334 #define MAC_CR_DISRTY                   0x00000400
 335 #define MAC_CR_PADSTR                   0x00000100
 336 #define MAC_CR_BOLMT_MASK               0x000000C0
 337 #define MAC_CR_DFCHK                    0x00000020
 338 #define MAC_CR_TXEN                     0x00000008
 339 #define MAC_CR_RXEN                     0x00000004
 340
 341 #define ADDRH                   0x02      /* R/W mask 0x0000FFFFUL */
 342 #define ADDRL                   0x03      /* R/W mask 0xFFFFFFFFUL */
 343 #define HASHH                   0x04      /* R/W */
 344 #define HASHL                   0x05      /* R/W */
 345
 346 #define MII_ACC                 0x06      /* R/W */
 347 #define MII_ACC_PHY_ADDR                0x0000F800
 348 #define MII_ACC_MIIRINDA                0x000007C0
 349 #define MII_ACC_MII_WRITE               0x00000002
 350 #define MII_ACC_MII_BUSY                0x00000001
 351
 352 #define MII_DATA                0x07      /* R/W mask 0x0000FFFFUL */
 353
 354 #define FLOW                    0x08      /* R/W */
 355 #define FLOW_FCPT                       0xFFFF0000
 356 #define FLOW_FCPASS                     0x00000004
 357 #define FLOW_FCEN                       0x00000002
 358 #define FLOW_FCBSY                      0x00000001
 359
 360 #define VLAN1                   0x09      /* R/W mask 0x0000FFFFUL */
 361 #define VLAN1_VTI1                      0x0000ffff
 362
 363 #define VLAN2                   0x0A      /* R/W mask 0x0000FFFFUL */
 364 #define VLAN2_VTI2                      0x0000ffff
 365
 366 #define WUFF                    0x0B      /* WO */
 367
 368 #define WUCSR                   0x0C      /* R/W */
 369 #define WUCSR_GUE                       0x00000200
 370 #define WUCSR_WUFR                      0x00000040
 371 #define WUCSR_MPR                       0x00000020
 372 #define WUCSR_WAKE_EN                   0x00000004
 373 #define WUCSR_MPEN                      0x00000002
 374
 375 /* Chip ID values */
 376 #define CHIP_9115       0x115
 377 #define CHIP_9116       0x116
 378 #define CHIP_9117       0x117
 379 #define CHIP_9118       0x118
 380 #define CHIP_9211       0x9211
 381 #define CHIP_9215       0x115a
 382 #define CHIP_9216       0x116a
 383 #define CHIP_9217       0x117a
 384 #define CHIP_9218       0x118a
 385 #define CHIP_9221       0x9221
 386
 387 struct chip_id {
 388         u16 id;
 389         char *name;
 390 };
 391
 392 static const struct chip_id chip_ids[] =  {
 393         { CHIP_9115, "LAN9115" },
 394         { CHIP_9116, "LAN9116" },
 395         { CHIP_9117, "LAN9117" },
 396         { CHIP_9118, "LAN9118" },
 397         { CHIP_9211, "LAN9211" },
 398         { CHIP_9215, "LAN9215" },
 399         { CHIP_9216, "LAN9216" },
 400         { CHIP_9217, "LAN9217" },
 401         { CHIP_9218, "LAN9218" },
 402         { CHIP_9221, "LAN9221" },
 403         { 0, NULL },
 404 };
 405
 406
 407 #define DRIVERNAME "smc911x"
 408
 409 static u32 smc911x_get_mac_csr(u8 reg)
 410 {
 411         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 412                 ;
 413         smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
 414         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 415                 ;
 416
 417         return smc911x_reg_read(MAC_CSR_DATA);
 418 }
 419
 420 static void smc911x_set_mac_csr(u8 reg, u32 data)
 421 {
 422         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 423                 ;
 424         smc911x_reg_write(MAC_CSR_DATA, data);
 425         smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
 426         while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
 427                 ;
 428 }
 429
 430 static int smc911x_detect_chip(void)
 431 {
 432         unsigned long val, i;
 433
 434         val = smc911x_reg_read(BYTE_TEST);
 435         if (val != 0x87654321) {
 436                 printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
 437                 return -1;
 438         }
 439
 440         val = smc911x_reg_read(ID_REV) >> 16;
 441         for (i = 0; chip_ids[i].id != 0; i++) {
 442                 if (chip_ids[i].id == val) break;
 443         }
 444         if (!chip_ids[i].id) {
 445                 printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
 446                 return -1;
 447         }
 448
 449         printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
 450
 451         return 0;
 452 }
 453
 454 static void smc911x_reset(void)
 455 {
 456         int timeout;
 457
 458         /* Take out of PM setting first */
 459         if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) {
 460                 /* Write to the bytetest will take out of powerdown */
 461                 smc911x_reg_write(BYTE_TEST, 0x0);
 462
 463                 timeout = 10;
 464
 465                 while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY))
 466                         udelay(10);
 467                 if (!timeout) {
 468                         printf(DRIVERNAME
 469                                 ": timeout waiting for PM restore\n");
 470                         return;
 471                 }
 472         }
 473
 474         /* Disable interrupts */
 475         smc911x_reg_write(INT_EN, 0);
 476
 477         smc911x_reg_write(HW_CFG, HW_CFG_SRST);
 478
 479         timeout = 1000;
 480         while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
 481                 udelay(10);
 482
 483         if (!timeout) {
 484                 printf(DRIVERNAME ": reset timeout\n");
 485                 return;
 486         }
 487
 488         /* Reset the FIFO level and flow control settings */
 489         smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
 490         smc911x_reg_write(AFC_CFG, 0x0050287F);
 491
 492         /* Set to LED outputs */
 493         smc911x_reg_write(GPIO_CFG, 0x70070000);
 494 }
 495
 496 #endif