drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * PCI routines
  13  */
  14
  15 #include <common.h>
  16
  17 #include <command.h>
  18 #include <asm/processor.h>
  19 #include <asm/io.h>
  20 #include <pci.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define PCI_HOSE_OP(rw, size, type)                                     \
  25 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  26                                   pci_dev_t dev,                        \
  27                                   int offset, type value)               \
  28 {                                                                       \
  29         return hose->rw##_##size(hose, dev, offset, value);             \
  30 }
  31
  32 PCI_HOSE_OP(read, byte, u8 *)
  33 PCI_HOSE_OP(read, word, u16 *)
  34 PCI_HOSE_OP(read, dword, u32 *)
  35 PCI_HOSE_OP(write, byte, u8)
  36 PCI_HOSE_OP(write, word, u16)
  37 PCI_HOSE_OP(write, dword, u32)
  38
  39 #define PCI_OP(rw, size, type, error_code)                              \
  40 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  41 {                                                                       \
  42         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  43                                                                         \
  44         if (!hose)                                                      \
  45         {                                                               \
  46                 error_code;                                             \
  47                 return -1;                                              \
  48         }                                                               \
  49                                                                         \
  50         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  51 }
  52
  53 PCI_OP(read, byte, u8 *, *value = 0xff)
  54 PCI_OP(read, word, u16 *, *value = 0xffff)
  55 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  56 PCI_OP(write, byte, u8, )
  57 PCI_OP(write, word, u16, )
  58 PCI_OP(write, dword, u32, )
  59
  60 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  61 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  62                                         pci_dev_t dev,                  \
  63                                         int offset, type val)           \
  64 {                                                                       \
  65         u32 val32;                                                      \
  66                                                                         \
  67         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  68                 *val = -1;                                              \
  69                 return -1;                                              \
  70         }                                                               \
  71                                                                         \
  72         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  73                                                                         \
  74         return 0;                                                       \
  75 }
  76
  77 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  78 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  79                                              pci_dev_t dev,             \
  80                                              int offset, type val)      \
  81 {                                                                       \
  82         u32 val32, mask, ldata, shift;                                  \
  83                                                                         \
  84         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  85                 return -1;                                              \
  86                                                                         \
  87         shift = ((offset & (int)off_mask) * 8);                         \
  88         ldata = (((unsigned long)val) & val_mask) << shift;             \
  89         mask = val_mask << shift;                                       \
  90         val32 = (val32 & ~mask) | ldata;                                \
  91                                                                         \
  92         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
  93                 return -1;                                              \
  94                                                                         \
  95         return 0;                                                       \
  96 }
  97
  98 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
  99 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 100 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 101 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 102
 103 /* Get a virtual address associated with a BAR region */
 104 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 105 {
 106         pci_addr_t pci_bus_addr;
 107         u32 bar_response;
 108
 109         /* read BAR address */
 110         pci_read_config_dword(pdev, bar, &bar_response);
 111         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 112
 113         /*
 114          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
 115          * isn't actualy used on any platform because u-boot assumes a static
 116          * linear mapping.  In the future, this could read the BAR size
 117          * and pass that as the size if needed.
 118          */
 119         return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 120 }
 121
 122 /*
 123  *
 124  */
 125
 126 static struct pci_controller* hose_head;
 127
 128 struct pci_controller *pci_get_hose_head(void)
 129 {
 130         if (gd->hose)
 131                 return gd->hose;
 132
 133         return hose_head;
 134 }
 135
 136 void pci_register_hose(struct pci_controller* hose)
 137 {
 138         struct pci_controller **phose = &hose_head;
 139
 140         while(*phose)
 141                 phose = &(*phose)->next;
 142
 143         hose->next = NULL;
 144
 145         *phose = hose;
 146 }
 147
 148 struct pci_controller *pci_bus_to_hose(int bus)
 149 {
 150         struct pci_controller *hose;
 151
 152         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
 153                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 154                         return hose;
 155         }
 156
 157         printf("pci_bus_to_hose() failed\n");
 158         return NULL;
 159 }
 160
 161 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 162 {
 163         struct pci_controller *hose;
 164
 165         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
 166                 if (hose->cfg_addr == cfg_addr)
 167                         return hose;
 168         }
 169
 170         return NULL;
 171 }
 172
 173 int pci_last_busno(void)
 174 {
 175         struct pci_controller *hose = pci_get_hose_head();
 176
 177         if (!hose)
 178                 return -1;
 179
 180         while (hose->next)
 181                 hose = hose->next;
 182
 183         return hose->last_busno;
 184 }
 185
 186 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 187 {
 188         struct pci_controller * hose;
 189         u16 vendor, device;
 190         u8 header_type;
 191         pci_dev_t bdf;
 192         int i, bus, found_multi = 0;
 193
 194         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
 195 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 196                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 197 #else
 198                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 199 #endif
 200                         for (bdf = PCI_BDF(bus, 0, 0);
 201                              bdf < PCI_BDF(bus + 1, 0, 0);
 202                              bdf += PCI_BDF(0, 0, 1)) {
 203                                 if (pci_skip_dev(hose, bdf))
 204                                         continue;
 205
 206                                 if (!PCI_FUNC(bdf)) {
 207                                         pci_read_config_byte(bdf,
 208                                                              PCI_HEADER_TYPE,
 209                                                              &header_type);
 210
 211                                         found_multi = header_type & 0x80;
 212                                 } else {
 213                                         if (!found_multi)
 214                                                 continue;
 215                                 }
 216
 217                                 pci_read_config_word(bdf,
 218                                                      PCI_VENDOR_ID,
 219                                                      &vendor);
 220                                 pci_read_config_word(bdf,
 221                                                      PCI_DEVICE_ID,
 222                                                      &device);
 223
 224                                 for (i = 0; ids[i].vendor != 0; i++) {
 225                                         if (vendor == ids[i].vendor &&
 226                                             device == ids[i].device) {
 227                                                 if (index <= 0)
 228                                                         return bdf;
 229
 230                                                 index--;
 231                                         }
 232                                 }
 233                         }
 234         }
 235
 236         return -1;
 237 }
 238
 239 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 240 {
 241         struct pci_device_id ids[2] = { {}, {0, 0} };
 242
 243         ids[0].vendor = vendor;
 244         ids[0].device = device;
 245
 246         return pci_find_devices(ids, index);
 247 }
 248
 249 /*
 250  *
 251  */
 252
 253 int __pci_hose_phys_to_bus(struct pci_controller *hose,
 254                                 phys_addr_t phys_addr,
 255                                 unsigned long flags,
 256                                 unsigned long skip_mask,
 257                                 pci_addr_t *ba)
 258 {
 259         struct pci_region *res;
 260         pci_addr_t bus_addr;
 261         int i;
 262
 263         for (i = 0; i < hose->region_count; i++) {
 264                 res = &hose->regions[i];
 265
 266                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 267                         continue;
 268
 269                 if (res->flags & skip_mask)
 270                         continue;
 271
 272                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 273
 274                 if (bus_addr >= res->bus_start &&
 275                         bus_addr < res->bus_start + res->size) {
 276                         *ba = bus_addr;
 277                         return 0;
 278                 }
 279         }
 280
 281         return 1;
 282 }
 283
 284 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 285                                     phys_addr_t phys_addr,
 286                                     unsigned long flags)
 287 {
 288         pci_addr_t bus_addr = 0;
 289         int ret;
 290
 291         if (!hose) {
 292                 puts("pci_hose_phys_to_bus: invalid hose\n");
 293                 return bus_addr;
 294         }
 295
 296         /*
 297          * if PCI_REGION_MEM is set we do a two pass search with preference
 298          * on matches that don't have PCI_REGION_SYS_MEMORY set
 299          */
 300         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 301                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
 302                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 303                 if (!ret)
 304                         return bus_addr;
 305         }
 306
 307         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 308
 309         if (ret)
 310                 puts("pci_hose_phys_to_bus: invalid physical address\n");
 311
 312         return bus_addr;
 313 }
 314
 315 int __pci_hose_bus_to_phys(struct pci_controller *hose,
 316                                 pci_addr_t bus_addr,
 317                                 unsigned long flags,
 318                                 unsigned long skip_mask,
 319                                 phys_addr_t *pa)
 320 {
 321         struct pci_region *res;
 322         int i;
 323
 324         for (i = 0; i < hose->region_count; i++) {
 325                 res = &hose->regions[i];
 326
 327                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 328                         continue;
 329
 330                 if (res->flags & skip_mask)
 331                         continue;
 332
 333                 if (bus_addr >= res->bus_start &&
 334                         (bus_addr - res->bus_start) < res->size) {
 335                         *pa = (bus_addr - res->bus_start + res->phys_start);
 336                         return 0;
 337                 }
 338         }
 339
 340         return 1;
 341 }
 342
 343 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 344                                  pci_addr_t bus_addr,
 345                                  unsigned long flags)
 346 {
 347         phys_addr_t phys_addr = 0;
 348         int ret;
 349
 350         if (!hose) {
 351                 puts("pci_hose_bus_to_phys: invalid hose\n");
 352                 return phys_addr;
 353         }
 354
 355         /*
 356          * if PCI_REGION_MEM is set we do a two pass search with preference
 357          * on matches that don't have PCI_REGION_SYS_MEMORY set
 358          */
 359         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 360                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
 361                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 362                 if (!ret)
 363                         return phys_addr;
 364         }
 365
 366         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 367
 368         if (ret)
 369                 puts("pci_hose_bus_to_phys: invalid physical address\n");
 370
 371         return phys_addr;
 372 }
 373
 374 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
 375                      u32 addr_and_ctrl)
 376 {
 377         int bar;
 378
 379         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
 380         pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
 381 }
 382
 383 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
 384 {
 385         u32 addr;
 386         int bar;
 387
 388         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
 389         pci_hose_read_config_dword(hose, dev, bar, &addr);
 390         if (addr & PCI_BASE_ADDRESS_SPACE_IO)
 391                 return addr & PCI_BASE_ADDRESS_IO_MASK;
 392         else
 393                 return addr & PCI_BASE_ADDRESS_MEM_MASK;
 394 }
 395
 396 int pci_hose_config_device(struct pci_controller *hose,
 397                            pci_dev_t dev,
 398                            unsigned long io,
 399                            pci_addr_t mem,
 400                            unsigned long command)
 401 {
 402         u32 bar_response;
 403         unsigned int old_command;
 404         pci_addr_t bar_value;
 405         pci_size_t bar_size;
 406         unsigned char pin;
 407         int bar, found_mem64;
 408
 409         debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
 410                 (u64)mem, command);
 411
 412         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
 413
 414         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
 415                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 416                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 417
 418                 if (!bar_response)
 419                         continue;
 420
 421                 found_mem64 = 0;
 422
 423                 /* Check the BAR type and set our address mask */
 424                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 425                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 426                         /* round up region base address to a multiple of size */
 427                         io = ((io - 1) | (bar_size - 1)) + 1;
 428                         bar_value = io;
 429                         /* compute new region base address */
 430                         io = io + bar_size;
 431                 } else {
 432                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 433                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
 434                                 u32 bar_response_upper;
 435                                 u64 bar64;
 436                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 437                                         0xffffffff);
 438                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 439                                         &bar_response_upper);
 440
 441                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 442
 443                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 444                                 found_mem64 = 1;
 445                         } else {
 446                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 447                         }
 448
 449                         /* round up region base address to multiple of size */
 450                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 451                         bar_value = mem;
 452                         /* compute new region base address */
 453                         mem = mem + bar_size;
 454                 }
 455
 456                 /* Write it out and update our limit */
 457                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 458
 459                 if (found_mem64) {
 460                         bar += 4;
 461 #ifdef CONFIG_SYS_PCI_64BIT
 462                         pci_hose_write_config_dword(hose, dev, bar,
 463                                 (u32)(bar_value >> 32));
 464 #else
 465                         pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 466 #endif
 467                 }
 468         }
 469
 470         /* Configure Cache Line Size Register */
 471         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 472
 473         /* Configure Latency Timer */
 474         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 475
 476         /* Disable interrupt line, if device says it wants to use interrupts */
 477         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
 478         if (pin != 0) {
 479                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
 480         }
 481
 482         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
 483         pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
 484                                      (old_command & 0xffff0000) | command);
 485
 486         return 0;
 487 }
 488
 489 /*
 490  *
 491  */
 492
 493 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 494                                          unsigned short class,
 495                                          unsigned int vendor,
 496                                          unsigned int device,
 497                                          unsigned int bus,
 498                                          unsigned int dev,
 499                                          unsigned int func)
 500 {
 501         struct pci_config_table *table;
 502
 503         for (table = hose->config_table; table && table->vendor; table++) {
 504                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 505                     (table->device == PCI_ANY_ID || table->device == device) &&
 506                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 507                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 508                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 509                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 510                         return table;
 511                 }
 512         }
 513
 514         return NULL;
 515 }
 516
 517 void pci_cfgfunc_config_device(struct pci_controller *hose,
 518                                pci_dev_t dev,
 519                                struct pci_config_table *entry)
 520 {
 521         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
 522                 entry->priv[2]);
 523 }
 524
 525 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 526                             pci_dev_t dev, struct pci_config_table *entry)
 527 {
 528 }
 529
 530 /*
 531  * HJF: Changed this to return int. I think this is required
 532  * to get the correct result when scanning bridges
 533  */
 534 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 535
 536 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
 537 const char * pci_class_str(u8 class)
 538 {
 539         switch (class) {
 540         case PCI_CLASS_NOT_DEFINED:
 541                 return "Build before PCI Rev2.0";
 542                 break;
 543         case PCI_BASE_CLASS_STORAGE:
 544                 return "Mass storage controller";
 545                 break;
 546         case PCI_BASE_CLASS_NETWORK:
 547                 return "Network controller";
 548                 break;
 549         case PCI_BASE_CLASS_DISPLAY:
 550                 return "Display controller";
 551                 break;
 552         case PCI_BASE_CLASS_MULTIMEDIA:
 553                 return "Multimedia device";
 554                 break;
 555         case PCI_BASE_CLASS_MEMORY:
 556                 return "Memory controller";
 557                 break;
 558         case PCI_BASE_CLASS_BRIDGE:
 559                 return "Bridge device";
 560                 break;
 561         case PCI_BASE_CLASS_COMMUNICATION:
 562                 return "Simple comm. controller";
 563                 break;
 564         case PCI_BASE_CLASS_SYSTEM:
 565                 return "Base system peripheral";
 566                 break;
 567         case PCI_BASE_CLASS_INPUT:
 568                 return "Input device";
 569                 break;
 570         case PCI_BASE_CLASS_DOCKING:
 571                 return "Docking station";
 572                 break;
 573         case PCI_BASE_CLASS_PROCESSOR:
 574                 return "Processor";
 575                 break;
 576         case PCI_BASE_CLASS_SERIAL:
 577                 return "Serial bus controller";
 578                 break;
 579         case PCI_BASE_CLASS_INTELLIGENT:
 580                 return "Intelligent controller";
 581                 break;
 582         case PCI_BASE_CLASS_SATELLITE:
 583                 return "Satellite controller";
 584                 break;
 585         case PCI_BASE_CLASS_CRYPT:
 586                 return "Cryptographic device";
 587                 break;
 588         case PCI_BASE_CLASS_SIGNAL_PROCESSING:
 589                 return "DSP";
 590                 break;
 591         case PCI_CLASS_OTHERS:
 592                 return "Does not fit any class";
 593                 break;
 594         default:
 595         return  "???";
 596                 break;
 597         };
 598 }
 599 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
 600
 601 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 602 {
 603         /*
 604          * Check if pci device should be skipped in configuration
 605          */
 606         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 607 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 608                 /*
 609                  * Only skip configuration if "pciconfighost" is not set
 610                  */
 611                 if (getenv("pciconfighost") == NULL)
 612                         return 1;
 613 #else
 614                 return 1;
 615 #endif
 616         }
 617
 618         return 0;
 619 }
 620
 621 #ifdef CONFIG_PCI_SCAN_SHOW
 622 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 623 {
 624         if (dev == PCI_BDF(hose->first_busno, 0, 0))
 625                 return 0;
 626
 627         return 1;
 628 }
 629 #endif /* CONFIG_PCI_SCAN_SHOW */
 630
 631 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 632 {
 633         unsigned int sub_bus, found_multi = 0;
 634         unsigned short vendor, device, class;
 635         unsigned char header_type;
 636 #ifndef CONFIG_PCI_PNP
 637         struct pci_config_table *cfg;
 638 #endif
 639         pci_dev_t dev;
 640 #ifdef CONFIG_PCI_SCAN_SHOW
 641         static int indent = 0;
 642 #endif
 643
 644         sub_bus = bus;
 645
 646         for (dev =  PCI_BDF(bus,0,0);
 647              dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
 648                                 PCI_MAX_PCI_FUNCTIONS - 1);
 649              dev += PCI_BDF(0, 0, 1)) {
 650
 651                 if (pci_skip_dev(hose, dev))
 652                         continue;
 653
 654                 if (PCI_FUNC(dev) && !found_multi)
 655                         continue;
 656
 657                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 658
 659                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 660
 661                 if (vendor == 0xffff || vendor == 0x0000)
 662                         continue;
 663
 664                 if (!PCI_FUNC(dev))
 665                         found_multi = header_type & 0x80;
 666
 667                 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 668                         PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 669
 670                 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 671                 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 672
 673 #ifdef CONFIG_PCI_FIXUP_DEV
 674                 board_pci_fixup_dev(hose, dev, vendor, device, class);
 675 #endif
 676
 677 #ifdef CONFIG_PCI_SCAN_SHOW
 678                 indent++;
 679
 680                 /* Print leading space, including bus indentation */
 681                 printf("%*c", indent + 1, ' ');
 682
 683                 if (pci_print_dev(hose, dev)) {
 684                         printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
 685                                PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
 686                                vendor, device, pci_class_str(class >> 8));
 687                 }
 688 #endif
 689
 690 #ifdef CONFIG_PCI_PNP
 691                 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
 692                               sub_bus);
 693 #else
 694                 cfg = pci_find_config(hose, class, vendor, device,
 695                                       PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 696                 if (cfg) {
 697                         cfg->config_device(hose, dev, cfg);
 698                         sub_bus = max(sub_bus,
 699                                       (unsigned int)hose->current_busno);
 700                 }
 701 #endif
 702
 703 #ifdef CONFIG_PCI_SCAN_SHOW
 704                 indent--;
 705 #endif
 706
 707                 if (hose->fixup_irq)
 708                         hose->fixup_irq(hose, dev);
 709         }
 710
 711         return sub_bus;
 712 }
 713
 714 int pci_hose_scan(struct pci_controller *hose)
 715 {
 716 #if defined(CONFIG_PCI_BOOTDELAY)
 717         char *s;
 718         int i;
 719
 720         if (!gd->pcidelay_done) {
 721                 /* wait "pcidelay" ms (if defined)... */
 722                 s = getenv("pcidelay");
 723                 if (s) {
 724                         int val = simple_strtoul(s, NULL, 10);
 725                         for (i = 0; i < val; i++)
 726                                 udelay(1000);
 727                 }
 728                 gd->pcidelay_done = 1;
 729         }
 730 #endif /* CONFIG_PCI_BOOTDELAY */
 731
 732         /*
 733          * Start scan at current_busno.
 734          * PCIe will start scan at first_busno+1.
 735          */
 736         /* For legacy support, ensure current >= first */
 737         if (hose->first_busno > hose->current_busno)
 738                 hose->current_busno = hose->first_busno;
 739 #ifdef CONFIG_PCI_PNP
 740         pciauto_config_init(hose);
 741 #endif
 742         return pci_hose_scan_bus(hose, hose->current_busno);
 743 }
 744
 745 void pci_init(void)
 746 {
 747         hose_head = NULL;
 748
 749         /* now call board specific pci_init()... */
 750         pci_init_board();
 751 }
 752
 753 /* Returns the address of the requested capability structure within the
 754  * device's PCI configuration space or 0 in case the device does not
 755  * support it.
 756  * */
 757 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
 758                              int cap)
 759 {
 760         int pos;
 761         u8 hdr_type;
 762
 763         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
 764
 765         pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
 766
 767         if (pos)
 768                 pos = pci_find_cap(hose, dev, pos, cap);
 769
 770         return pos;
 771 }
 772
 773 /* Find the header pointer to the Capabilities*/
 774 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
 775                             u8 hdr_type)
 776 {
 777         u16 status;
 778
 779         pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
 780
 781         if (!(status & PCI_STATUS_CAP_LIST))
 782                 return 0;
 783
 784         switch (hdr_type) {
 785         case PCI_HEADER_TYPE_NORMAL:
 786         case PCI_HEADER_TYPE_BRIDGE:
 787                 return PCI_CAPABILITY_LIST;
 788         case PCI_HEADER_TYPE_CARDBUS:
 789                 return PCI_CB_CAPABILITY_LIST;
 790         default:
 791                 return 0;
 792         }
 793 }
 794
 795 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
 796 {
 797         int ttl = PCI_FIND_CAP_TTL;
 798         u8 id;
 799         u8 next_pos;
 800
 801         while (ttl--) {
 802                 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
 803                 if (next_pos < CAP_START_POS)
 804                         break;
 805                 next_pos &= ~3;
 806                 pos = (int) next_pos;
 807                 pci_hose_read_config_byte(hose, dev,
 808                                           pos + PCI_CAP_LIST_ID, &id);
 809                 if (id == 0xff)
 810                         break;
 811                 if (id == cap)
 812                         return pos;
 813                 pos += PCI_CAP_LIST_NEXT;
 814         }
 815         return 0;
 816 }