drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 #include <common.h>
  32
  33 #include <command.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <pci.h>
  37
  38 #define PCI_HOSE_OP(rw, size, type)                                     \
  39 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  40                                   pci_dev_t dev,                        \
  41                                   int offset, type value)               \
  42 {                                                                       \
  43         return hose->rw##_##size(hose, dev, offset, value);             \
  44 }
  45
  46 PCI_HOSE_OP(read, byte, u8 *)
  47 PCI_HOSE_OP(read, word, u16 *)
  48 PCI_HOSE_OP(read, dword, u32 *)
  49 PCI_HOSE_OP(write, byte, u8)
  50 PCI_HOSE_OP(write, word, u16)
  51 PCI_HOSE_OP(write, dword, u32)
  52
  53 #define PCI_OP(rw, size, type, error_code)                              \
  54 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  55 {                                                                       \
  56         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  57                                                                         \
  58         if (!hose)                                                      \
  59         {                                                               \
  60                 error_code;                                             \
  61                 return -1;                                              \
  62         }                                                               \
  63                                                                         \
  64         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  65 }
  66
  67 PCI_OP(read, byte, u8 *, *value = 0xff)
  68 PCI_OP(read, word, u16 *, *value = 0xffff)
  69 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  70 PCI_OP(write, byte, u8, )
  71 PCI_OP(write, word, u16, )
  72 PCI_OP(write, dword, u32, )
  73
  74 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  75 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  76                                         pci_dev_t dev,                  \
  77                                         int offset, type val)           \
  78 {                                                                       \
  79         u32 val32;                                                      \
  80                                                                         \
  81         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  82                 *val = -1;                                              \
  83                 return -1;                                              \
  84         }                                                               \
  85                                                                         \
  86         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  87                                                                         \
  88         return 0;                                                       \
  89 }
  90
  91 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  92 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  93                                              pci_dev_t dev,             \
  94                                              int offset, type val)      \
  95 {                                                                       \
  96         u32 val32, mask, ldata, shift;                                  \
  97                                                                         \
  98         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  99                 return -1;                                              \
 100                                                                         \
 101         shift = ((offset & (int)off_mask) * 8);                         \
 102         ldata = (((unsigned long)val) & val_mask) << shift;             \
 103         mask = val_mask << shift;                                       \
 104         val32 = (val32 & ~mask) | ldata;                                \
 105                                                                         \
 106         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 107                 return -1;                                              \
 108                                                                         \
 109         return 0;                                                       \
 110 }
 111
 112 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 113 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 114 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 115 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 116
 117 /* Get a virtual address associated with a BAR region */
 118 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 119 {
 120         pci_addr_t pci_bus_addr;
 121         pci_addr_t bar_response;
 122
 123         /* read BAR address */
 124         pci_read_config_dword(pdev, bar, &bar_response);
 125         pci_bus_addr = bar_response & ~0xf;
 126
 127         /*
 128          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
 129          * isn't actualy used on any platform because u-boot assumes a static
 130          * linear mapping.  In the future, this could read the BAR size
 131          * and pass that as the size if needed.
 132          */
 133         return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 134 }
 135
 136 /*
 137  *
 138  */
 139
 140 static struct pci_controller* hose_head;
 141
 142 void pci_register_hose(struct pci_controller* hose)
 143 {
 144         struct pci_controller **phose = &hose_head;
 145
 146         while(*phose)
 147                 phose = &(*phose)->next;
 148
 149         hose->next = NULL;
 150
 151         *phose = hose;
 152 }
 153
 154 struct pci_controller *pci_bus_to_hose (int bus)
 155 {
 156         struct pci_controller *hose;
 157
 158         for (hose = hose_head; hose; hose = hose->next)
 159                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 160                         return hose;
 161
 162         printf("pci_bus_to_hose() failed\n");
 163         return NULL;
 164 }
 165
 166 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 167 {
 168         struct pci_controller *hose;
 169
 170         for (hose = hose_head; hose; hose = hose->next) {
 171                 if (hose->cfg_addr == cfg_addr)
 172                         return hose;
 173         }
 174
 175         return NULL;
 176 }
 177
 178 int pci_last_busno(void)
 179 {
 180         struct pci_controller *hose = hose_head;
 181
 182         if (!hose)
 183                 return -1;
 184
 185         while (hose->next)
 186                 hose = hose->next;
 187
 188         return hose->last_busno;
 189 }
 190
 191 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 192 {
 193         struct pci_controller * hose;
 194         u16 vendor, device;
 195         u8 header_type;
 196         pci_dev_t bdf;
 197         int i, bus, found_multi = 0;
 198
 199         for (hose = hose_head; hose; hose = hose->next)
 200         {
 201 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 202                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 203 #else
 204                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 205 #endif
 206                         for (bdf = PCI_BDF(bus,0,0);
 207 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
 208                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 209 #else
 210                              bdf < PCI_BDF(bus+1,0,0);
 211 #endif
 212                              bdf += PCI_BDF(0,0,1))
 213                         {
 214                                 if (!PCI_FUNC(bdf)) {
 215                                         pci_read_config_byte(bdf,
 216                                                              PCI_HEADER_TYPE,
 217                                                              &header_type);
 218
 219                                         found_multi = header_type & 0x80;
 220                                 } else {
 221                                         if (!found_multi)
 222                                                 continue;
 223                                 }
 224
 225                                 pci_read_config_word(bdf,
 226                                                      PCI_VENDOR_ID,
 227                                                      &vendor);
 228                                 pci_read_config_word(bdf,
 229                                                      PCI_DEVICE_ID,
 230                                                      &device);
 231
 232                                 for (i=0; ids[i].vendor != 0; i++)
 233                                         if (vendor == ids[i].vendor &&
 234                                             device == ids[i].device)
 235                                         {
 236                                                 if (index <= 0)
 237                                                         return bdf;
 238
 239                                                 index--;
 240                                         }
 241                         }
 242         }
 243
 244         return (-1);
 245 }
 246
 247 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 248 {
 249         static struct pci_device_id ids[2] = {{}, {0, 0}};
 250
 251         ids[0].vendor = vendor;
 252         ids[0].device = device;
 253
 254         return pci_find_devices(ids, index);
 255 }
 256
 257 /*
 258  *
 259  */
 260
 261 int __pci_hose_phys_to_bus (struct pci_controller *hose,
 262                                 phys_addr_t phys_addr,
 263                                 unsigned long flags,
 264                                 unsigned long skip_mask,
 265                                 pci_addr_t *ba)
 266 {
 267         struct pci_region *res;
 268         pci_addr_t bus_addr;
 269         int i;
 270
 271         for (i = 0; i < hose->region_count; i++) {
 272                 res = &hose->regions[i];
 273
 274                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 275                         continue;
 276
 277                 if (res->flags & skip_mask)
 278                         continue;
 279
 280                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 281
 282                 if (bus_addr >= res->bus_start &&
 283                         bus_addr < res->bus_start + res->size) {
 284                         *ba = bus_addr;
 285                         return 0;
 286                 }
 287         }
 288
 289         return 1;
 290 }
 291
 292 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 293                                     phys_addr_t phys_addr,
 294                                     unsigned long flags)
 295 {
 296         pci_addr_t bus_addr = 0;
 297         int ret;
 298
 299         if (!hose) {
 300                 puts ("pci_hose_phys_to_bus: invalid hose\n");
 301                 return bus_addr;
 302         }
 303
 304         /* if PCI_REGION_MEM is set we do a two pass search with preference
 305          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 306         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 307                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
 308                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 309                 if (!ret)
 310                         return bus_addr;
 311         }
 312
 313         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 314
 315         if (ret)
 316                 puts ("pci_hose_phys_to_bus: invalid physical address\n");
 317
 318         return bus_addr;
 319 }
 320
 321 int __pci_hose_bus_to_phys (struct pci_controller *hose,
 322                                 pci_addr_t bus_addr,
 323                                 unsigned long flags,
 324                                 unsigned long skip_mask,
 325                                 phys_addr_t *pa)
 326 {
 327         struct pci_region *res;
 328         int i;
 329
 330         for (i = 0; i < hose->region_count; i++) {
 331                 res = &hose->regions[i];
 332
 333                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 334                         continue;
 335
 336                 if (res->flags & skip_mask)
 337                         continue;
 338
 339                 if (bus_addr >= res->bus_start &&
 340                         bus_addr < res->bus_start + res->size) {
 341                         *pa = (bus_addr - res->bus_start + res->phys_start);
 342                         return 0;
 343                 }
 344         }
 345
 346         return 1;
 347 }
 348
 349 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 350                                  pci_addr_t bus_addr,
 351                                  unsigned long flags)
 352 {
 353         phys_addr_t phys_addr = 0;
 354         int ret;
 355
 356         if (!hose) {
 357                 puts ("pci_hose_bus_to_phys: invalid hose\n");
 358                 return phys_addr;
 359         }
 360
 361         /* if PCI_REGION_MEM is set we do a two pass search with preference
 362          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 363         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 364                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
 365                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 366                 if (!ret)
 367                         return phys_addr;
 368         }
 369
 370         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 371
 372         if (ret)
 373                 puts ("pci_hose_bus_to_phys: invalid physical address\n");
 374
 375         return phys_addr;
 376 }
 377
 378 /*
 379  *
 380  */
 381
 382 int pci_hose_config_device(struct pci_controller *hose,
 383                            pci_dev_t dev,
 384                            unsigned long io,
 385                            pci_addr_t mem,
 386                            unsigned long command)
 387 {
 388         pci_addr_t bar_response;
 389         unsigned int old_command;
 390         pci_addr_t bar_value;
 391         pci_size_t bar_size;
 392         unsigned char pin;
 393         int bar, found_mem64;
 394
 395         debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
 396                 io, (u64)mem, command);
 397
 398         pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 399
 400         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
 401                 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 402                 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 403
 404                 if (!bar_response)
 405                         continue;
 406
 407                 found_mem64 = 0;
 408
 409                 /* Check the BAR type and set our address mask */
 410                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 411                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 412                         /* round up region base address to a multiple of size */
 413                         io = ((io - 1) | (bar_size - 1)) + 1;
 414                         bar_value = io;
 415                         /* compute new region base address */
 416                         io = io + bar_size;
 417                 } else {
 418                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 419                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
 420                                 u32 bar_response_upper;
 421                                 u64 bar64;
 422                                 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
 423                                 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
 424
 425                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 426
 427                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 428                                 found_mem64 = 1;
 429                         } else {
 430                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 431                         }
 432
 433                         /* round up region base address to multiple of size */
 434                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 435                         bar_value = mem;
 436                         /* compute new region base address */
 437                         mem = mem + bar_size;
 438                 }
 439
 440                 /* Write it out and update our limit */
 441                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 442
 443                 if (found_mem64) {
 444                         bar += 4;
 445 #ifdef CONFIG_SYS_PCI_64BIT
 446                         pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 447 #else
 448                         pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 449 #endif
 450                 }
 451         }
 452
 453         /* Configure Cache Line Size Register */
 454         pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 455
 456         /* Configure Latency Timer */
 457         pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 458
 459         /* Disable interrupt line, if device says it wants to use interrupts */
 460         pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 461         if (pin != 0) {
 462                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 463         }
 464
 465         pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 466         pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 467                                      (old_command & 0xffff0000) | command);
 468
 469         return 0;
 470 }
 471
 472 /*
 473  *
 474  */
 475
 476 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 477                                          unsigned short class,
 478                                          unsigned int vendor,
 479                                          unsigned int device,
 480                                          unsigned int bus,
 481                                          unsigned int dev,
 482                                          unsigned int func)
 483 {
 484         struct pci_config_table *table;
 485
 486         for (table = hose->config_table; table && table->vendor; table++) {
 487                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 488                     (table->device == PCI_ANY_ID || table->device == device) &&
 489                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 490                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 491                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 492                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 493                         return table;
 494                 }
 495         }
 496
 497         return NULL;
 498 }
 499
 500 void pci_cfgfunc_config_device(struct pci_controller *hose,
 501                                pci_dev_t dev,
 502                                struct pci_config_table *entry)
 503 {
 504         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 505 }
 506
 507 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 508                             pci_dev_t dev, struct pci_config_table *entry)
 509 {
 510 }
 511
 512 /*
 513  *
 514  */
 515
 516 /* HJF: Changed this to return int. I think this is required
 517  * to get the correct result when scanning bridges
 518  */
 519 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 520
 521 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
 522 const char * pci_class_str(u8 class)
 523 {
 524         switch (class) {
 525         case PCI_CLASS_NOT_DEFINED:
 526                 return "Build before PCI Rev2.0";
 527                 break;
 528         case PCI_BASE_CLASS_STORAGE:
 529                 return "Mass storage controller";
 530                 break;
 531         case PCI_BASE_CLASS_NETWORK:
 532                 return "Network controller";
 533                 break;
 534         case PCI_BASE_CLASS_DISPLAY:
 535                 return "Display controller";
 536                 break;
 537         case PCI_BASE_CLASS_MULTIMEDIA:
 538                 return "Multimedia device";
 539                 break;
 540         case PCI_BASE_CLASS_MEMORY:
 541                 return "Memory controller";
 542                 break;
 543         case PCI_BASE_CLASS_BRIDGE:
 544                 return "Bridge device";
 545                 break;
 546         case PCI_BASE_CLASS_COMMUNICATION:
 547                 return "Simple comm. controller";
 548                 break;
 549         case PCI_BASE_CLASS_SYSTEM:
 550                 return "Base system peripheral";
 551                 break;
 552         case PCI_BASE_CLASS_INPUT:
 553                 return "Input device";
 554                 break;
 555         case PCI_BASE_CLASS_DOCKING:
 556                 return "Docking station";
 557                 break;
 558         case PCI_BASE_CLASS_PROCESSOR:
 559                 return "Processor";
 560                 break;
 561         case PCI_BASE_CLASS_SERIAL:
 562                 return "Serial bus controller";
 563                 break;
 564         case PCI_BASE_CLASS_INTELLIGENT:
 565                 return "Intelligent controller";
 566                 break;
 567         case PCI_BASE_CLASS_SATELLITE:
 568                 return "Satellite controller";
 569                 break;
 570         case PCI_BASE_CLASS_CRYPT:
 571                 return "Cryptographic device";
 572                 break;
 573         case PCI_BASE_CLASS_SIGNAL_PROCESSING:
 574                 return "DSP";
 575                 break;
 576         case PCI_CLASS_OTHERS:
 577                 return "Does not fit any class";
 578                 break;
 579         default:
 580         return  "???";
 581                 break;
 582         };
 583 }
 584 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
 585
 586 int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 587 {
 588         /*
 589          * Check if pci device should be skipped in configuration
 590          */
 591         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 592 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 593                 /*
 594                  * Only skip configuration if "pciconfighost" is not set
 595                  */
 596                 if (getenv("pciconfighost") == NULL)
 597                         return 1;
 598 #else
 599                 return 1;
 600 #endif
 601         }
 602
 603         return 0;
 604 }
 605 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 606         __attribute__((weak, alias("__pci_skip_dev")));
 607
 608 #ifdef CONFIG_PCI_SCAN_SHOW
 609 int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 610 {
 611         if (dev == PCI_BDF(hose->first_busno, 0, 0))
 612                 return 0;
 613
 614         return 1;
 615 }
 616 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 617         __attribute__((weak, alias("__pci_print_dev")));
 618 #endif /* CONFIG_PCI_SCAN_SHOW */
 619
 620 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 621 {
 622         unsigned int sub_bus, found_multi=0;
 623         unsigned short vendor, device, class;
 624         unsigned char header_type;
 625         struct pci_config_table *cfg;
 626         pci_dev_t dev;
 627 #ifdef CONFIG_PCI_SCAN_SHOW
 628         static int indent = 0;
 629 #endif
 630
 631         sub_bus = bus;
 632
 633         for (dev =  PCI_BDF(bus,0,0);
 634              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 635              dev += PCI_BDF(0,0,1)) {
 636
 637                 if (pci_skip_dev(hose, dev))
 638                         continue;
 639
 640                 if (PCI_FUNC(dev) && !found_multi)
 641                         continue;
 642
 643                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 644
 645                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 646
 647                 if (vendor == 0xffff || vendor == 0x0000)
 648                         continue;
 649
 650                 if (!PCI_FUNC(dev))
 651                         found_multi = header_type & 0x80;
 652
 653                 debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 654                         PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 655
 656                 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 657                 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 658
 659 #ifdef CONFIG_PCI_SCAN_SHOW
 660                 indent++;
 661
 662                 /* Print leading space, including bus indentation */
 663                 printf("%*c", indent + 1, ' ');
 664
 665                 if (pci_print_dev(hose, dev)) {
 666                         printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
 667                                PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
 668                                vendor, device, pci_class_str(class >> 8));
 669                 }
 670 #endif
 671
 672                 cfg = pci_find_config(hose, class, vendor, device,
 673                                       PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 674                 if (cfg) {
 675                         cfg->config_device(hose, dev, cfg);
 676                         sub_bus = max(sub_bus, hose->current_busno);
 677 #ifdef CONFIG_PCI_PNP
 678                 } else {
 679                         int n = pciauto_config_device(hose, dev);
 680
 681                         sub_bus = max(sub_bus, n);
 682 #endif
 683                 }
 684
 685 #ifdef CONFIG_PCI_SCAN_SHOW
 686                 indent--;
 687 #endif
 688
 689                 if (hose->fixup_irq)
 690                         hose->fixup_irq(hose, dev);
 691         }
 692
 693         return sub_bus;
 694 }
 695
 696 int pci_hose_scan(struct pci_controller *hose)
 697 {
 698 #if defined(CONFIG_PCI_BOOTDELAY)
 699         static int pcidelay_done;
 700         char *s;
 701         int i;
 702
 703         if (!pcidelay_done) {
 704                 /* wait "pcidelay" ms (if defined)... */
 705                 s = getenv("pcidelay");
 706                 if (s) {
 707                         int val = simple_strtoul(s, NULL, 10);
 708                         for (i = 0; i < val; i++)
 709                                 udelay(1000);
 710                 }
 711                 pcidelay_done = 1;
 712         }
 713 #endif /* CONFIG_PCI_BOOTDELAY */
 714
 715         /* Start scan at current_busno.
 716          * PCIe will start scan at first_busno+1.
 717          */
 718         /* For legacy support, ensure current>=first */
 719         if (hose->first_busno > hose->current_busno)
 720                 hose->current_busno = hose->first_busno;
 721 #ifdef CONFIG_PCI_PNP
 722         pciauto_config_init(hose);
 723 #endif
 724         return pci_hose_scan_bus(hose, hose->current_busno);
 725 }
 726
 727 void pci_init(void)
 728 {
 729         hose_head = NULL;
 730
 731         /* now call board specific pci_init()... */
 732         pci_init_board();
 733 }