drivers/pci/pci_gt64120.c

   1 /*
   2  * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
   3  *
   4  * Based on the Linux implementation.
   5  *   Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
   6  *   Authors: Carsten Langgaard <carstenl@mips.com>
   7  *            Maciej W. Rozycki <macro@mips.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14 #include <common.h>
  15 #include <gt64120.h>
  16 #include <pci.h>
  17 #include <pci_gt64120.h>
  18
  19 #include <asm/io.h>
  20
  21 #define PCI_ACCESS_READ  0
  22 #define PCI_ACCESS_WRITE 1
  23
  24 struct gt64120_regs {
  25         u8      unused_000[0xc18];
  26         u32     intrcause;
  27         u8      unused_c1c[0x0dc];
  28         u32     pci0_cfgaddr;
  29         u32     pci0_cfgdata;
  30 };
  31
  32 struct gt64120_pci_controller {
  33         struct pci_controller hose;
  34         struct gt64120_regs *regs;
  35 };
  36
  37 static inline struct gt64120_pci_controller *
  38 hose_to_gt64120(struct pci_controller *hose)
  39 {
  40         return container_of(hose, struct gt64120_pci_controller, hose);
  41 }
  42
  43 #define GT_INTRCAUSE_ABORT_BITS \
  44                 (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
  45
  46 static int gt_config_access(struct gt64120_pci_controller *gt,
  47                             unsigned char access_type, pci_dev_t bdf,
  48                             int where, u32 *data)
  49 {
  50         unsigned int bus = PCI_BUS(bdf);
  51         unsigned int dev = PCI_DEV(bdf);
  52         unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
  53         u32 intr;
  54         u32 addr;
  55         u32 val;
  56
  57         if (bus == 0 && dev >= 31) {
  58                 /* Because of a bug in the galileo (for slot 31). */
  59                 return -1;
  60         }
  61
  62         if (access_type == PCI_ACCESS_WRITE)
  63                 debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
  64                       PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
  65
  66         /* Clear cause register bits */
  67         writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
  68
  69         addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
  70         addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
  71         addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
  72         addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
  73
  74         /* Setup address */
  75         writel(addr, &gt->regs->pci0_cfgaddr);
  76
  77         if (access_type == PCI_ACCESS_WRITE) {
  78                 if (bus == 0 && dev == 0) {
  79                         /*
  80                          * The Galileo system controller is acting
  81                          * differently than other devices.
  82                          */
  83                         val = *data;
  84                 } else {
  85                         val = cpu_to_le32(*data);
  86                 }
  87
  88                 writel(val, &gt->regs->pci0_cfgdata);
  89         } else {
  90                 val = readl(&gt->regs->pci0_cfgdata);
  91
  92                 if (bus == 0 && dev == 0) {
  93                         /*
  94                          * The Galileo system controller is acting
  95                          * differently than other devices.
  96                          */
  97                         *data = val;
  98                 } else {
  99                         *data = le32_to_cpu(val);
 100                 }
 101         }
 102
 103         /* Check for master or target abort */
 104         intr = readl(&gt->regs->intrcause);
 105         if (intr & GT_INTRCAUSE_ABORT_BITS) {
 106                 /* Error occurred, clear abort bits */
 107                 writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
 108                 return -1;
 109         }
 110
 111         if (access_type == PCI_ACCESS_READ)
 112                 debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
 113                       PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
 114
 115         return 0;
 116 }
 117
 118 static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
 119                                 int where, u32 *value)
 120 {
 121         struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
 122
 123         *value = 0xffffffff;
 124         return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
 125 }
 126
 127 static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
 128                                  int where, u32 value)
 129 {
 130         struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
 131         u32 data = value;
 132
 133         return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
 134 }
 135
 136 void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
 137                      unsigned long sys_size, unsigned long mem_bus,
 138                      unsigned long mem_phys, unsigned long mem_size,
 139                      unsigned long io_bus, unsigned long io_phys,
 140                      unsigned long io_size)
 141 {
 142         static struct gt64120_pci_controller global_gt;
 143         struct gt64120_pci_controller *gt;
 144         struct pci_controller *hose;
 145
 146         gt = &global_gt;
 147         gt->regs = regs;
 148
 149         hose = &gt->hose;
 150
 151         hose->first_busno = 0;
 152         hose->last_busno = 0;
 153
 154         /* System memory space */
 155         pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
 156                        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 157
 158         /* PCI memory space */
 159         pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
 160                        PCI_REGION_MEM);
 161
 162         /* PCI I/O space */
 163         pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
 164                        PCI_REGION_IO);
 165
 166         hose->region_count = 3;
 167
 168         pci_set_ops(hose,
 169                     pci_hose_read_config_byte_via_dword,
 170                     pci_hose_read_config_word_via_dword,
 171                     gt_read_config_dword,
 172                     pci_hose_write_config_byte_via_dword,
 173                     pci_hose_write_config_word_via_dword,
 174                     gt_write_config_dword);
 175
 176         pci_register_hose(hose);
 177         hose->last_busno = pci_hose_scan(hose);
 178 }