2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "asm/errno.h"
27 #include "asm/immap_qe.h"
30 qe_map_t *qe_immr = NULL;
31 static qe_snum_t snums[QE_NUM_OF_SNUM];
33 DECLARE_GLOBAL_DATA_PTR;
35 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
39 if (cmd == QE_RESET) {
40 out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
42 out_be32(&qe_immr->cp.cecdr, cmd_data);
43 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
44 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
46 /* Wait for the QE_CR_FLG to clear */
48 cecr = in_be32(&qe_immr->cp.cecr);
49 } while (cecr & QE_CR_FLG);
54 uint qe_muram_alloc(uint size, uint align)
60 align_mask = align - 1;
61 savebase = gd->mp_alloc_base;
63 if ((off = (gd->mp_alloc_base & align_mask)) != 0)
64 gd->mp_alloc_base += (align - off);
66 if ((off = size & align_mask) != 0)
67 size += (align - off);
69 if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) {
70 gd->mp_alloc_base = savebase;
71 printf("%s: ran out of ram.\n", __FUNCTION__);
74 retloc = gd->mp_alloc_base;
75 gd->mp_alloc_base += size;
77 memset((void *)&qe_immr->muram[retloc], 0, size);
79 __asm__ __volatile__("sync");
84 void *qe_muram_addr(uint offset)
86 return (void *)&qe_immr->muram[offset];
89 static void qe_sdma_init(void)
92 uint sdma_buffer_base;
94 p = (volatile sdma_t *)&qe_immr->sdma;
96 /* All of DMA transaction in bus 1 */
97 out_be32(&p->sdaqr, 0);
98 out_be32(&p->sdaqmr, 0);
100 /* Allocate 2KB temporary buffer for sdma */
101 sdma_buffer_base = qe_muram_alloc(2048, 4096);
102 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
104 /* Clear sdma status */
105 out_be32(&p->sdsr, 0x03000000);
107 /* Enable global mode on bus 1, and 2KB buffer size */
108 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
111 static u8 thread_snum[QE_NUM_OF_SNUM] = {
112 0x04, 0x05, 0x0c, 0x0d,
113 0x14, 0x15, 0x1c, 0x1d,
114 0x24, 0x25, 0x2c, 0x2d,
115 0x34, 0x35, 0x88, 0x89,
116 0x98, 0x99, 0xa8, 0xa9,
117 0xb8, 0xb9, 0xc8, 0xc9,
118 0xd8, 0xd9, 0xe8, 0xe9
121 static void qe_snums_init(void)
125 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
126 snums[i].state = QE_SNUM_STATE_FREE;
127 snums[i].num = thread_snum[i];
131 int qe_get_snum(void)
136 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
137 if (snums[i].state == QE_SNUM_STATE_FREE) {
138 snums[i].state = QE_SNUM_STATE_USED;
147 void qe_put_snum(u8 snum)
151 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
152 if (snums[i].num == snum) {
153 snums[i].state = QE_SNUM_STATE_FREE;
159 void qe_init(uint qe_base)
161 /* Init the QE IMMR base */
162 qe_immr = (qe_map_t *)qe_base;
164 #ifdef CONFIG_SYS_QE_FW_ADDR
165 /* Upload microcode to IRAM for those SOCs which do not have ROM in QE.
167 qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR);
169 /* enable the microcode in IRAM */
170 out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
173 gd->mp_alloc_base = QE_DATAONLY_BASE;
174 gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
182 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
183 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
186 void qe_assign_page(uint snum, uint para_ram_base)
190 out_be32(&qe_immr->cp.cecdr, para_ram_base);
191 out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
192 | QE_CR_FLG | QE_ASSIGN_PAGE);
194 /* Wait for the QE_CR_FLG to clear */
196 cecr = in_be32(&qe_immr->cp.cecr);
197 } while (cecr & QE_CR_FLG );
203 * brg: 0~15 as BRG1~BRG16
205 * BRG input clock comes from the BRGCLK (internal clock generated from
206 the QE clock, it is one-half of the QE clock), If need the clock source
207 from CLKn pin, we have te change the function.
210 #define BRG_CLK (gd->brg_clk)
212 int qe_set_brg(uint brg, uint rate)
218 if (brg >= QE_NUM_OF_BRGS)
220 bp = (uint *)&qe_immr->brg.brgc1;
223 divisor = (BRG_CLK / rate);
224 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
229 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
230 __asm__ __volatile__("sync");
233 *bp |= QE_BRGC_DIV16;
234 __asm__ __volatile__("sync");
240 /* Set ethernet MII clock master
242 int qe_set_mii_clk_src(int ucc_num)
246 /* check if the UCC number is in range. */
247 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
248 printf("%s: ucc num not in ranges\n", __FUNCTION__);
252 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
253 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
254 cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
255 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
260 /* The maximum number of RISCs we support */
261 #define MAX_QE_RISC 2
263 /* Firmware information stored here for qe_get_firmware_info() */
264 static struct qe_firmware_info qe_firmware_info;
267 * Set to 1 if QE firmware has been uploaded, and therefore
268 * qe_firmware_info contains valid data.
270 static int qe_firmware_uploaded;
273 * Upload a QE microcode
275 * This function is a worker function for qe_upload_firmware(). It does
276 * the actual uploading of the microcode.
278 static void qe_upload_microcode(const void *base,
279 const struct qe_microcode *ucode)
281 const u32 *code = base + be32_to_cpu(ucode->code_offset);
284 if (ucode->major || ucode->minor || ucode->revision)
285 printf("QE: uploading microcode '%s' version %u.%u.%u\n",
286 ucode->id, ucode->major, ucode->minor, ucode->revision);
288 printf("QE: uploading microcode '%s'\n", ucode->id);
290 /* Use auto-increment */
291 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
292 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
294 for (i = 0; i < be32_to_cpu(ucode->count); i++)
295 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
299 * Upload a microcode to the I-RAM at a specific address.
301 * See docs/README.qe_firmware for information on QE microcode uploading.
303 * Currently, only version 1 is supported, so the 'version' field must be
306 * The SOC model and revision are not validated, they are only displayed for
307 * informational purposes.
309 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
310 * all of the microcode structures, minus the CRC.
312 * 'length' is the size that the structure says it is, including the CRC.
314 int qe_upload_firmware(const struct qe_firmware *firmware)
319 size_t calc_size = sizeof(struct qe_firmware);
321 const struct qe_header *hdr;
324 printf("Invalid address\n");
328 hdr = &firmware->header;
329 length = be32_to_cpu(hdr->length);
331 /* Check the magic */
332 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
333 (hdr->magic[2] != 'F')) {
334 printf("Not a microcode\n");
338 /* Check the version */
339 if (hdr->version != 1) {
340 printf("Unsupported version\n");
344 /* Validate some of the fields */
345 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
346 printf("Invalid data\n");
350 /* Validate the length and check if there's a CRC */
351 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
353 for (i = 0; i < firmware->count; i++)
355 * For situations where the second RISC uses the same microcode
356 * as the first, the 'code_offset' and 'count' fields will be
357 * zero, so it's okay to add those.
359 calc_size += sizeof(u32) *
360 be32_to_cpu(firmware->microcode[i].count);
362 /* Validate the length */
363 if (length != calc_size + sizeof(u32)) {
364 printf("Invalid length\n");
369 * Validate the CRC. We would normally call crc32_no_comp(), but that
370 * function isn't available unless you turn on JFFS support.
372 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
373 if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
374 printf("Firmware CRC is invalid\n");
379 * If the microcode calls for it, split the I-RAM.
381 if (!firmware->split) {
382 out_be16(&qe_immr->cp.cercr,
383 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
386 if (firmware->soc.model)
387 printf("Firmware '%s' for %u V%u.%u\n",
388 firmware->id, be16_to_cpu(firmware->soc.model),
389 firmware->soc.major, firmware->soc.minor);
391 printf("Firmware '%s'\n", firmware->id);
394 * The QE only supports one microcode per RISC, so clear out all the
395 * saved microcode information and put in the new.
397 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
398 strcpy(qe_firmware_info.id, (char *)firmware->id);
399 qe_firmware_info.extended_modes = firmware->extended_modes;
400 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
401 sizeof(firmware->vtraps));
402 qe_firmware_uploaded = 1;
404 /* Loop through each microcode. */
405 for (i = 0; i < firmware->count; i++) {
406 const struct qe_microcode *ucode = &firmware->microcode[i];
408 /* Upload a microcode if it's present */
409 if (ucode->code_offset)
410 qe_upload_microcode(firmware, ucode);
412 /* Program the traps for this processor */
413 for (j = 0; j < 16; j++) {
414 u32 trap = be32_to_cpu(ucode->traps[j]);
417 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
421 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
427 struct qe_firmware_info *qe_get_firmware_info(void)
429 return qe_firmware_uploaded ? &qe_firmware_info : NULL;
432 static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
441 if (strcmp(argv[1], "fw") == 0) {
442 addr = simple_strtoul(argv[2], NULL, 16);
445 printf("Invalid address\n");
450 * If a length was supplied, compare that with the 'length'
455 ulong length = simple_strtoul(argv[3], NULL, 16);
456 struct qe_firmware *firmware = (void *) addr;
458 if (length != be32_to_cpu(firmware->header.length)) {
459 printf("Length mismatch\n");
464 return qe_upload_firmware((const struct qe_firmware *) addr);
473 "QUICC Engine commands",
474 "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
475 "the QE,\n\twith optional length <length> verification.\n"