drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/errno.h>
  31 #include "cadence_qspi.h"
  32
  33 #define CQSPI_REG_POLL_US                       (1) /* 1us */
  34 #define CQSPI_REG_RETRY                         (10000)
  35 #define CQSPI_POLL_IDLE_RETRY                   (3)
  36
  37 #define CQSPI_FIFO_WIDTH                        (4)
  38
  39 #define CQSPI_REG_SRAM_THRESHOLD_WORDS          (50)
  40
  41 /* Transfer mode */
  42 #define CQSPI_INST_TYPE_SINGLE                  (0)
  43 #define CQSPI_INST_TYPE_DUAL                    (1)
  44 #define CQSPI_INST_TYPE_QUAD                    (2)
  45
  46 #define CQSPI_STIG_DATA_LEN_MAX                 (8)
  47 #define CQSPI_INDIRECTTRIGGER_ADDR_MASK         (0xFFFFF)
  48
  49 #define CQSPI_DUMMY_CLKS_PER_BYTE               (8)
  50 #define CQSPI_DUMMY_BYTES_MAX                   (4)
  51
  52
  53 #define CQSPI_REG_SRAM_FILL_THRESHOLD   \
  54         ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
  55 /****************************************************************************
  56  * Controller's configuration and status register (offset from QSPI_BASE)
  57  ****************************************************************************/
  58 #define CQSPI_REG_CONFIG                        0x00
  59 #define CQSPI_REG_CONFIG_CLK_POL_LSB            1
  60 #define CQSPI_REG_CONFIG_CLK_PHA_LSB            2
  61 #define CQSPI_REG_CONFIG_ENABLE_MASK            (1 << 0)
  62 #define CQSPI_REG_CONFIG_DIRECT_MASK            (1 << 7)
  63 #define CQSPI_REG_CONFIG_DECODE_MASK            (1 << 9)
  64 #define CQSPI_REG_CONFIG_XIP_IMM_MASK           (1 << 18)
  65 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  66 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  67 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  68 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  69 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  70
  71 #define CQSPI_REG_RD_INSTR                      0x04
  72 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  73 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  74 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  75 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  76 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  77 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  78 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  79 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  80 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  81 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  82
  83 #define CQSPI_REG_WR_INSTR                      0x08
  84 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  85
  86 #define CQSPI_REG_DELAY                         0x0C
  87 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  88 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  89 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  90 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  91 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  92 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  93 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  94 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  95
  96 #define CQSPI_READLCAPTURE                      0x10
  97 #define CQSPI_READLCAPTURE_BYPASS_LSB           0
  98 #define CQSPI_READLCAPTURE_DELAY_LSB            1
  99 #define CQSPI_READLCAPTURE_DELAY_MASK           0xF
 100
 101 #define CQSPI_REG_SIZE                          0x14
 102 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 103 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 104 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 105 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 106 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 107 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 108
 109 #define CQSPI_REG_SRAMPARTITION                 0x18
 110 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 111
 112 #define CQSPI_REG_REMAP                         0x24
 113 #define CQSPI_REG_MODE_BIT                      0x28
 114
 115 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 116 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 117 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 118 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 119 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 120
 121 #define CQSPI_REG_IRQSTATUS                     0x40
 122 #define CQSPI_REG_IRQMASK                       0x44
 123
 124 #define CQSPI_REG_INDIRECTRD                    0x60
 125 #define CQSPI_REG_INDIRECTRD_START_MASK         (1 << 0)
 126 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        (1 << 1)
 127 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK    (1 << 2)
 128 #define CQSPI_REG_INDIRECTRD_DONE_MASK          (1 << 5)
 129
 130 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 131 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 132 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 133
 134 #define CQSPI_REG_CMDCTRL                       0x90
 135 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          (1 << 0)
 136 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       (1 << 1)
 137 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 138 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 139 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 140 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 141 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 142 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 143 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 144 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 145 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 146 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 147 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 148 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 149 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 150
 151 #define CQSPI_REG_INDIRECTWR                    0x70
 152 #define CQSPI_REG_INDIRECTWR_START_MASK         (1 << 0)
 153 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        (1 << 1)
 154 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK    (1 << 2)
 155 #define CQSPI_REG_INDIRECTWR_DONE_MASK          (1 << 5)
 156
 157 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 158 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 159 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 160
 161 #define CQSPI_REG_CMDADDRESS                    0x94
 162 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 163 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 164 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 165 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 166
 167 #define CQSPI_REG_IS_IDLE(base)                                 \
 168         ((readl(base + CQSPI_REG_CONFIG) >>             \
 169                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 170
 171 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)           \
 172         ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
 173
 174 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 175         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 176         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 177
 178 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 179         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 180         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 181
 182 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 183         unsigned int addr_width)
 184 {
 185         unsigned int addr;
 186
 187         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 188
 189         if (addr_width == 4)
 190                 addr = (addr << 8) | addr_buf[3];
 191
 192         return addr;
 193 }
 194
 195 static void cadence_qspi_apb_read_fifo_data(void *dest,
 196         const void *src_ahb_addr, unsigned int bytes)
 197 {
 198         unsigned int temp;
 199         int remaining = bytes;
 200         unsigned int *dest_ptr = (unsigned int *)dest;
 201         unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
 202
 203         while (remaining >= sizeof(dest_ptr)) {
 204                 *dest_ptr = readl(src_ptr);
 205                 remaining -= sizeof(src_ptr);
 206                 dest_ptr++;
 207         }
 208         if (remaining) {
 209                 /* dangling bytes */
 210                 temp = readl(src_ptr);
 211                 memcpy(dest_ptr, &temp, remaining);
 212         }
 213
 214         return;
 215 }
 216
 217 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
 218         const void *src, unsigned int bytes)
 219 {
 220         unsigned int temp = 0;
 221         int i;
 222         int remaining = bytes;
 223         unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
 224         unsigned int *src_ptr = (unsigned int *)src;
 225
 226         while (remaining >= CQSPI_FIFO_WIDTH) {
 227                 for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
 228                         writel(*(src_ptr+i), dest_ptr+i);
 229                 src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
 230                 remaining -= CQSPI_FIFO_WIDTH;
 231         }
 232         if (remaining) {
 233                 /* dangling bytes */
 234                 i = remaining/sizeof(dest_ptr);
 235                 memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
 236                 writel(temp, dest_ptr+i);
 237                 for (--i; i >= 0; i--)
 238                         writel(*(src_ptr+i), dest_ptr+i);
 239         }
 240         return;
 241 }
 242
 243 /* Read from SRAM FIFO with polling SRAM fill level. */
 244 static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
 245                         const void *src_addr,  unsigned int num_bytes)
 246 {
 247         unsigned int remaining = num_bytes;
 248         unsigned int retry;
 249         unsigned int sram_level = 0;
 250         unsigned char *dest = (unsigned char *)dest_addr;
 251
 252         while (remaining > 0) {
 253                 retry = CQSPI_REG_RETRY;
 254                 while (retry--) {
 255                         sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
 256                         if (sram_level)
 257                                 break;
 258                         udelay(1);
 259                 }
 260
 261                 if (!retry) {
 262                         printf("QSPI: No receive data after polling for %d times\n",
 263                                CQSPI_REG_RETRY);
 264                         return -1;
 265                 }
 266
 267                 sram_level *= CQSPI_FIFO_WIDTH;
 268                 sram_level = sram_level > remaining ? remaining : sram_level;
 269
 270                 /* Read data from FIFO. */
 271                 cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
 272                 dest += sram_level;
 273                 remaining -= sram_level;
 274                 udelay(1);
 275         }
 276         return 0;
 277 }
 278
 279 /* Write to SRAM FIFO with polling SRAM fill level. */
 280 static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
 281                                 const void *src_addr, unsigned int num_bytes)
 282 {
 283         const void *reg_base = plat->regbase;
 284         void *dest_addr = plat->ahbbase;
 285         unsigned int retry = CQSPI_REG_RETRY;
 286         unsigned int sram_level;
 287         unsigned int wr_bytes;
 288         unsigned char *src = (unsigned char *)src_addr;
 289         int remaining = num_bytes;
 290         unsigned int page_size = plat->page_size;
 291         unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
 292
 293         while (remaining > 0) {
 294                 retry = CQSPI_REG_RETRY;
 295                 while (retry--) {
 296                         sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
 297                         if (sram_level <= sram_threshold_words)
 298                                 break;
 299                 }
 300                 if (!retry) {
 301                         printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
 302                                sram_level, sram_threshold_words);
 303                         return -1;
 304                 }
 305                 /* Write a page or remaining bytes. */
 306                 wr_bytes = (remaining > page_size) ?
 307                                         page_size : remaining;
 308
 309                 cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
 310                 src += wr_bytes;
 311                 remaining -= wr_bytes;
 312         }
 313
 314         return 0;
 315 }
 316
 317 void cadence_qspi_apb_controller_enable(void *reg_base)
 318 {
 319         unsigned int reg;
 320         reg = readl(reg_base + CQSPI_REG_CONFIG);
 321         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 322         writel(reg, reg_base + CQSPI_REG_CONFIG);
 323         return;
 324 }
 325
 326 void cadence_qspi_apb_controller_disable(void *reg_base)
 327 {
 328         unsigned int reg;
 329         reg = readl(reg_base + CQSPI_REG_CONFIG);
 330         reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 331         writel(reg, reg_base + CQSPI_REG_CONFIG);
 332         return;
 333 }
 334
 335 /* Return 1 if idle, otherwise return 0 (busy). */
 336 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 337 {
 338         unsigned int start, count = 0;
 339         /* timeout in unit of ms */
 340         unsigned int timeout = 5000;
 341
 342         start = get_timer(0);
 343         for ( ; get_timer(start) < timeout ; ) {
 344                 if (CQSPI_REG_IS_IDLE(reg_base))
 345                         count++;
 346                 else
 347                         count = 0;
 348                 /*
 349                  * Ensure the QSPI controller is in true idle state after
 350                  * reading back the same idle status consecutively
 351                  */
 352                 if (count >= CQSPI_POLL_IDLE_RETRY)
 353                         return 1;
 354         }
 355
 356         /* Timeout, still in busy mode. */
 357         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 358                CQSPI_REG_RETRY);
 359         return 0;
 360 }
 361
 362 void cadence_qspi_apb_readdata_capture(void *reg_base,
 363                                 unsigned int bypass, unsigned int delay)
 364 {
 365         unsigned int reg;
 366         cadence_qspi_apb_controller_disable(reg_base);
 367
 368         reg = readl(reg_base + CQSPI_READLCAPTURE);
 369
 370         if (bypass)
 371                 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 372         else
 373                 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 374
 375         reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
 376                 << CQSPI_READLCAPTURE_DELAY_LSB);
 377
 378         reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
 379                 << CQSPI_READLCAPTURE_DELAY_LSB);
 380
 381         writel(reg, reg_base + CQSPI_READLCAPTURE);
 382
 383         cadence_qspi_apb_controller_enable(reg_base);
 384         return;
 385 }
 386
 387 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 388         unsigned int ref_clk_hz, unsigned int sclk_hz)
 389 {
 390         unsigned int reg;
 391         unsigned int div;
 392
 393         cadence_qspi_apb_controller_disable(reg_base);
 394         reg = readl(reg_base + CQSPI_REG_CONFIG);
 395         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 396
 397         div = ref_clk_hz / sclk_hz;
 398
 399         if (div > 32)
 400                 div = 32;
 401
 402         /* Check if even number. */
 403         if ((div & 1)) {
 404                 div = (div / 2);
 405         } else {
 406                 if (ref_clk_hz % sclk_hz)
 407                         /* ensure generated SCLK doesn't exceed user
 408                         specified sclk_hz */
 409                         div = (div / 2);
 410                 else
 411                         div = (div / 2) - 1;
 412         }
 413
 414         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
 415               ref_clk_hz, sclk_hz, div);
 416
 417         div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 418         reg |= div;
 419         writel(reg, reg_base + CQSPI_REG_CONFIG);
 420
 421         cadence_qspi_apb_controller_enable(reg_base);
 422         return;
 423 }
 424
 425 void cadence_qspi_apb_set_clk_mode(void *reg_base,
 426         unsigned int clk_pol, unsigned int clk_pha)
 427 {
 428         unsigned int reg;
 429
 430         cadence_qspi_apb_controller_disable(reg_base);
 431         reg = readl(reg_base + CQSPI_REG_CONFIG);
 432         reg &= ~(1 <<
 433                 (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
 434
 435         reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
 436         reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
 437
 438         writel(reg, reg_base + CQSPI_REG_CONFIG);
 439
 440         cadence_qspi_apb_controller_enable(reg_base);
 441         return;
 442 }
 443
 444 void cadence_qspi_apb_chipselect(void *reg_base,
 445         unsigned int chip_select, unsigned int decoder_enable)
 446 {
 447         unsigned int reg;
 448
 449         cadence_qspi_apb_controller_disable(reg_base);
 450
 451         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 452               decoder_enable);
 453
 454         reg = readl(reg_base + CQSPI_REG_CONFIG);
 455         /* docoder */
 456         if (decoder_enable) {
 457                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 458         } else {
 459                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 460                 /* Convert CS if without decoder.
 461                  * CS0 to 4b'1110
 462                  * CS1 to 4b'1101
 463                  * CS2 to 4b'1011
 464                  * CS3 to 4b'0111
 465                  */
 466                 chip_select = 0xF & ~(1 << chip_select);
 467         }
 468
 469         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 470                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 471         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 472                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 473         writel(reg, reg_base + CQSPI_REG_CONFIG);
 474
 475         cadence_qspi_apb_controller_enable(reg_base);
 476         return;
 477 }
 478
 479 void cadence_qspi_apb_delay(void *reg_base,
 480         unsigned int ref_clk, unsigned int sclk_hz,
 481         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 482         unsigned int tchsh_ns, unsigned int tslch_ns)
 483 {
 484         unsigned int ref_clk_ns;
 485         unsigned int sclk_ns;
 486         unsigned int tshsl, tchsh, tslch, tsd2d;
 487         unsigned int reg;
 488
 489         cadence_qspi_apb_controller_disable(reg_base);
 490
 491         /* Convert to ns. */
 492         ref_clk_ns = (1000000000) / ref_clk;
 493
 494         /* Convert to ns. */
 495         sclk_ns = (1000000000) / sclk_hz;
 496
 497         /* Plus 1 to round up 1 clock cycle. */
 498         tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
 499         tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
 500         tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
 501         tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
 502
 503         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 504                         << CQSPI_REG_DELAY_TSHSL_LSB);
 505         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 506                         << CQSPI_REG_DELAY_TCHSH_LSB);
 507         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 508                         << CQSPI_REG_DELAY_TSLCH_LSB);
 509         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 510                         << CQSPI_REG_DELAY_TSD2D_LSB);
 511         writel(reg, reg_base + CQSPI_REG_DELAY);
 512
 513         cadence_qspi_apb_controller_enable(reg_base);
 514         return;
 515 }
 516
 517 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 518 {
 519         unsigned reg;
 520
 521         cadence_qspi_apb_controller_disable(plat->regbase);
 522
 523         /* Configure the device size and address bytes */
 524         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 525         /* Clear the previous value */
 526         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 527         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 528         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 529         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 530         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 531
 532         /* Configure the remap address register, no remap */
 533         writel(0, plat->regbase + CQSPI_REG_REMAP);
 534
 535         /* Indirect mode configurations */
 536         writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
 537
 538         /* Disable all interrupts */
 539         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 540
 541         cadence_qspi_apb_controller_enable(plat->regbase);
 542         return;
 543 }
 544
 545 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 546         unsigned int reg)
 547 {
 548         unsigned int retry = CQSPI_REG_RETRY;
 549
 550         /* Write the CMDCTRL without start execution. */
 551         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 552         /* Start execute */
 553         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 554         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 555
 556         while (retry--) {
 557                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 558                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
 559                         break;
 560                 udelay(1);
 561         }
 562
 563         if (!retry) {
 564                 printf("QSPI: flash command execution timeout\n");
 565                 return -EIO;
 566         }
 567
 568         /* Polling QSPI idle status. */
 569         if (!cadence_qspi_wait_idle(reg_base))
 570                 return -EIO;
 571
 572         return 0;
 573 }
 574
 575 /* For command RDID, RDSR. */
 576 int cadence_qspi_apb_command_read(void *reg_base,
 577         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 578         u8 *rxbuf)
 579 {
 580         unsigned int reg;
 581         unsigned int read_len;
 582         int status;
 583
 584         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 585                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 586                        cmdlen, rxlen);
 587                 return -EINVAL;
 588         }
 589
 590         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 591
 592         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 593
 594         /* 0 means 1 byte. */
 595         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 596                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 597         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 598         if (status != 0)
 599                 return status;
 600
 601         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 602
 603         /* Put the read value into rx_buf */
 604         read_len = (rxlen > 4) ? 4 : rxlen;
 605         memcpy(rxbuf, &reg, read_len);
 606         rxbuf += read_len;
 607
 608         if (rxlen > 4) {
 609                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 610
 611                 read_len = rxlen - read_len;
 612                 memcpy(rxbuf, &reg, read_len);
 613         }
 614         return 0;
 615 }
 616
 617 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 618 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 619         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 620 {
 621         unsigned int reg = 0;
 622         unsigned int addr_value;
 623         unsigned int wr_data;
 624         unsigned int wr_len;
 625
 626         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 627                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 628                        cmdlen, txlen);
 629                 return -EINVAL;
 630         }
 631
 632         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 633
 634         if (cmdlen == 4 || cmdlen == 5) {
 635                 /* Command with address */
 636                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 637                 /* Number of bytes to write. */
 638                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 639                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 640                 /* Get address */
 641                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 642                         cmdlen >= 5 ? 4 : 3);
 643
 644                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 645         }
 646
 647         if (txlen) {
 648                 /* writing data = yes */
 649                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 650                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 651                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 652
 653                 wr_len = txlen > 4 ? 4 : txlen;
 654                 memcpy(&wr_data, txbuf, wr_len);
 655                 writel(wr_data, reg_base +
 656                         CQSPI_REG_CMDWRITEDATALOWER);
 657
 658                 if (txlen > 4) {
 659                         txbuf += wr_len;
 660                         wr_len = txlen - wr_len;
 661                         memcpy(&wr_data, txbuf, wr_len);
 662                         writel(wr_data, reg_base +
 663                                 CQSPI_REG_CMDWRITEDATAUPPER);
 664                 }
 665         }
 666
 667         /* Execute the command */
 668         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 669 }
 670
 671 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 672 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 673         unsigned int cmdlen, const u8 *cmdbuf)
 674 {
 675         unsigned int reg;
 676         unsigned int rd_reg;
 677         unsigned int addr_value;
 678         unsigned int dummy_clk;
 679         unsigned int dummy_bytes;
 680         unsigned int addr_bytes;
 681
 682         /*
 683          * Identify addr_byte. All NOR flash device drivers are using fast read
 684          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 685          * With that, the length is in value of 5 or 6. Only FRAM chip from
 686          * ramtron using normal read (which won't need dummy byte).
 687          * Unlikely NOR flash using normal read due to performance issue.
 688          */
 689         if (cmdlen >= 5)
 690                 /* to cater fast read where cmd + addr + dummy */
 691                 addr_bytes = cmdlen - 2;
 692         else
 693                 /* for normal read (only ramtron as of now) */
 694                 addr_bytes = cmdlen - 1;
 695
 696         /* Setup the indirect trigger address */
 697         writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
 698                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 699
 700         /* Configure the opcode */
 701         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 702
 703 #if (CONFIG_SPI_FLASH_QUAD == 1)
 704         /* Instruction and address at DQ0, data at DQ0-3. */
 705         rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 706 #endif
 707
 708         /* Get address */
 709         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 710         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 711
 712         /* The remaining lenght is dummy bytes. */
 713         dummy_bytes = cmdlen - addr_bytes - 1;
 714         if (dummy_bytes) {
 715                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 716                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 717
 718                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 719 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 720                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 721 #else
 722                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 723 #endif
 724
 725                 /* Convert to clock cycles. */
 726                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 727                 /* Need to minus the mode byte (8 clocks). */
 728                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 729
 730                 if (dummy_clk)
 731                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 732                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 733         }
 734
 735         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 736
 737         /* set device size */
 738         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 739         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 740         reg |= (addr_bytes - 1);
 741         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 742         return 0;
 743 }
 744
 745 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 746         unsigned int rxlen, u8 *rxbuf)
 747 {
 748         unsigned int reg;
 749
 750         writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 751
 752         /* Start the indirect read transfer */
 753         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 754                plat->regbase + CQSPI_REG_INDIRECTRD);
 755
 756         if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
 757                                      (const void *)plat->ahbbase, rxlen))
 758                 goto failrd;
 759
 760         /* Check flash indirect controller */
 761         reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
 762         if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
 763                 reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
 764                 printf("QSPI: indirect completion status error with reg 0x%08x\n",
 765                        reg);
 766                 goto failrd;
 767         }
 768
 769         /* Clear indirect completion status */
 770         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 771                plat->regbase + CQSPI_REG_INDIRECTRD);
 772         return 0;
 773
 774 failrd:
 775         /* Cancel the indirect read */
 776         writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
 777                plat->regbase + CQSPI_REG_INDIRECTRD);
 778         return -1;
 779 }
 780
 781 /* Opcode + Address (3/4 bytes) */
 782 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 783         unsigned int cmdlen, const u8 *cmdbuf)
 784 {
 785         unsigned int reg;
 786         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 787
 788         if (cmdlen < 4 || cmdbuf == NULL) {
 789                 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
 790                        cmdlen, (unsigned int)cmdbuf);
 791                 return -EINVAL;
 792         }
 793         /* Setup the indirect trigger address */
 794         writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
 795                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 796
 797         /* Configure the opcode */
 798         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 799         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 800
 801         /* Setup write address. */
 802         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 803         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 804
 805         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 806         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 807         reg |= (addr_bytes - 1);
 808         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 809         return 0;
 810 }
 811
 812 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 813         unsigned int txlen, const u8 *txbuf)
 814 {
 815         unsigned int reg = 0;
 816         unsigned int retry;
 817
 818         /* Configure the indirect read transfer bytes */
 819         writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 820
 821         /* Start the indirect write transfer */
 822         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 823                plat->regbase + CQSPI_REG_INDIRECTWR);
 824
 825         if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
 826                 goto failwr;
 827
 828         /* Wait until last write is completed (FIFO empty) */
 829         retry = CQSPI_REG_RETRY;
 830         while (retry--) {
 831                 reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
 832                 if (reg == 0)
 833                         break;
 834
 835                 udelay(1);
 836         }
 837
 838         if (reg != 0) {
 839                 printf("QSPI: timeout for indirect write\n");
 840                 goto failwr;
 841         }
 842
 843         /* Check flash indirect controller status */
 844         retry = CQSPI_REG_RETRY;
 845         while (retry--) {
 846                 reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
 847                 if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
 848                         break;
 849                 udelay(1);
 850         }
 851
 852         if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
 853                 printf("QSPI: indirect completion status error with reg 0x%08x\n",
 854                        reg);
 855                 goto failwr;
 856         }
 857
 858         /* Clear indirect completion status */
 859         writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
 860                plat->regbase + CQSPI_REG_INDIRECTWR);
 861         return 0;
 862
 863 failwr:
 864         /* Cancel the indirect write */
 865         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 866                plat->regbase + CQSPI_REG_INDIRECTWR);
 867         return -1;
 868 }
 869
 870 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 871 {
 872         unsigned int reg;
 873
 874         /* enter XiP mode immediately and enable direct mode */
 875         reg = readl(reg_base + CQSPI_REG_CONFIG);
 876         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 877         reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
 878         reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
 879         writel(reg, reg_base + CQSPI_REG_CONFIG);
 880
 881         /* keep the XiP mode */
 882         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 883
 884         /* Enable mode bit at devrd */
 885         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 886         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 887         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 888 }