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[karo-tx-uboot.git] / drivers / spi / sh_spi.c
1 /*
2  * SH SPI driver
3  *
4  * Copyright (C) 2011 Renesas Solutions Corp.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
18  *
19  */
20
21 #include <common.h>
22 #include <malloc.h>
23 #include <spi.h>
24 #include <asm/io.h>
25 #include "sh_spi.h"
26
27 static void sh_spi_write(unsigned long data, unsigned long *reg)
28 {
29         writel(data, reg);
30 }
31
32 static unsigned long sh_spi_read(unsigned long *reg)
33 {
34         return readl(reg);
35 }
36
37 static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
38 {
39         unsigned long tmp;
40
41         tmp = sh_spi_read(reg);
42         tmp |= val;
43         sh_spi_write(tmp, reg);
44 }
45
46 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
47 {
48         unsigned long tmp;
49
50         tmp = sh_spi_read(reg);
51         tmp &= ~val;
52         sh_spi_write(tmp, reg);
53 }
54
55 static void clear_fifo(struct sh_spi *ss)
56 {
57         sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
58         sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
59 }
60
61 static int recvbuf_wait(struct sh_spi *ss)
62 {
63         while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
64                 if (ctrlc())
65                         return 1;
66                 udelay(10);
67         }
68         return 0;
69 }
70
71 static int write_fifo_empty_wait(struct sh_spi *ss)
72 {
73         while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
74                 if (ctrlc())
75                         return 1;
76                 udelay(10);
77         }
78         return 0;
79 }
80
81 void spi_init(void)
82 {
83 }
84
85 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
86                 unsigned int max_hz, unsigned int mode)
87 {
88         struct sh_spi *ss;
89
90         if (!spi_cs_is_valid(bus, cs))
91                 return NULL;
92
93         ss = malloc(sizeof(struct spi_slave));
94         if (!ss)
95                 return NULL;
96
97         ss->slave.bus = bus;
98         ss->slave.cs = cs;
99         ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
100
101         /* SPI sycle stop */
102         sh_spi_write(0xfe, &ss->regs->cr1);
103         /* CR1 init */
104         sh_spi_write(0x00, &ss->regs->cr1);
105         /* CR3 init */
106         sh_spi_write(0x00, &ss->regs->cr3);
107
108         clear_fifo(ss);
109
110         /* 1/8 clock */
111         sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
112         udelay(10);
113
114         return &ss->slave;
115 }
116
117 void spi_free_slave(struct spi_slave *slave)
118 {
119         struct sh_spi *spi = to_sh_spi(slave);
120
121         free(spi);
122 }
123
124 int spi_claim_bus(struct spi_slave *slave)
125 {
126         return 0;
127 }
128
129 void spi_release_bus(struct spi_slave *slave)
130 {
131         struct sh_spi *ss = to_sh_spi(slave);
132
133         sh_spi_write(sh_spi_read(&ss->regs->cr1) &
134                 ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
135 }
136
137 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
138                         unsigned int len, unsigned long flags)
139 {
140         int i, cur_len, ret = 0;
141         int remain = (int)len;
142         unsigned long tmp;
143
144         if (len >= SH_SPI_FIFO_SIZE)
145                 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
146
147         while (remain > 0) {
148                 cur_len = (remain < SH_SPI_FIFO_SIZE) ?
149                                 remain : SH_SPI_FIFO_SIZE;
150                 for (i = 0; i < cur_len &&
151                         !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
152                         !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
153                                 i++)
154                         sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
155
156                 cur_len = i;
157
158                 if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
159                         /* Abort the transaction */
160                         flags |= SPI_XFER_END;
161                         sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
162                         ret = 1;
163                         break;
164                 }
165
166                 remain -= cur_len;
167                 tx_data += cur_len;
168
169                 if (remain > 0)
170                         write_fifo_empty_wait(ss);
171         }
172
173         if (flags & SPI_XFER_END) {
174                 tmp = sh_spi_read(&ss->regs->cr1);
175                 tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
176                 sh_spi_write(tmp, &ss->regs->cr1);
177                 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
178                 udelay(100);
179                 write_fifo_empty_wait(ss);
180         }
181
182         return ret;
183 }
184
185 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
186                           unsigned int len, unsigned long flags)
187 {
188         int i;
189         unsigned long tmp;
190
191         if (len > SH_SPI_MAX_BYTE)
192                 sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
193         else
194                 sh_spi_write(len, &ss->regs->cr3);
195
196         tmp = sh_spi_read(&ss->regs->cr1);
197         tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
198         sh_spi_write(tmp, &ss->regs->cr1);
199         sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
200
201         for (i = 0; i < len; i++) {
202                 if (recvbuf_wait(ss))
203                         return 0;
204
205                 rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
206         }
207         sh_spi_write(0, &ss->regs->cr3);
208
209         return 0;
210 }
211
212 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
213                 void *din, unsigned long flags)
214 {
215         struct sh_spi *ss = to_sh_spi(slave);
216         const unsigned char *tx_data = dout;
217         unsigned char *rx_data = din;
218         unsigned int len = bitlen / 8;
219         int ret = 0;
220
221         if (flags & SPI_XFER_BEGIN)
222                 sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
223                                 &ss->regs->cr1);
224
225         if (tx_data)
226                 ret = sh_spi_send(ss, tx_data, len, flags);
227
228         if (ret == 0 && rx_data)
229                 ret = sh_spi_receive(ss, rx_data, len, flags);
230
231         if (flags & SPI_XFER_END) {
232                 sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
233                 udelay(100);
234
235                 sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
236                                  &ss->regs->cr1);
237                 clear_fifo(ss);
238         }
239
240         return ret;
241 }
242
243 int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
244 {
245         /* This driver supports "bus = 0" and "cs = 0" only. */
246         if (!bus && !cs)
247                 return 1;
248         else
249                 return 0;
250 }
251
252 void spi_cs_activate(struct spi_slave *slave)
253 {
254
255 }
256
257 void spi_cs_deactivate(struct spi_slave *slave)
258 {
259
260 }
261