drivers/spi/sh_spi.c

   1 /*
   2  * SH SPI driver
   3  *
   4  * Copyright (C) 2011-2012 Renesas Solutions Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  *
  19  */
  20
  21 #include <common.h>
  22 #include <malloc.h>
  23 #include <spi.h>
  24 #include <asm/io.h>
  25 #include "sh_spi.h"
  26
  27 static void sh_spi_write(unsigned long data, unsigned long *reg)
  28 {
  29         writel(data, reg);
  30 }
  31
  32 static unsigned long sh_spi_read(unsigned long *reg)
  33 {
  34         return readl(reg);
  35 }
  36
  37 static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
  38 {
  39         unsigned long tmp;
  40
  41         tmp = sh_spi_read(reg);
  42         tmp |= val;
  43         sh_spi_write(tmp, reg);
  44 }
  45
  46 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
  47 {
  48         unsigned long tmp;
  49
  50         tmp = sh_spi_read(reg);
  51         tmp &= ~val;
  52         sh_spi_write(tmp, reg);
  53 }
  54
  55 static void clear_fifo(struct sh_spi *ss)
  56 {
  57         sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
  58         sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
  59 }
  60
  61 static int recvbuf_wait(struct sh_spi *ss)
  62 {
  63         while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
  64                 if (ctrlc())
  65                         return 1;
  66                 udelay(10);
  67         }
  68         return 0;
  69 }
  70
  71 static int write_fifo_empty_wait(struct sh_spi *ss)
  72 {
  73         while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
  74                 if (ctrlc())
  75                         return 1;
  76                 udelay(10);
  77         }
  78         return 0;
  79 }
  80
  81 void spi_init(void)
  82 {
  83 }
  84
  85 static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
  86 {
  87         unsigned long val = 0;
  88
  89         if (cs & 0x01)
  90                 val |= SH_SPI_SSS0;
  91         if (cs & 0x02)
  92                 val |= SH_SPI_SSS1;
  93
  94         sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
  95         sh_spi_set_bit(val, &ss->regs->cr4);
  96 }
  97
  98 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  99                 unsigned int max_hz, unsigned int mode)
 100 {
 101         struct sh_spi *ss;
 102
 103         if (!spi_cs_is_valid(bus, cs))
 104                 return NULL;
 105
 106         ss = malloc(sizeof(struct spi_slave));
 107         if (!ss)
 108                 return NULL;
 109
 110         ss->slave.bus = bus;
 111         ss->slave.cs = cs;
 112         ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
 113
 114         /* SPI sycle stop */
 115         sh_spi_write(0xfe, &ss->regs->cr1);
 116         /* CR1 init */
 117         sh_spi_write(0x00, &ss->regs->cr1);
 118         /* CR3 init */
 119         sh_spi_write(0x00, &ss->regs->cr3);
 120         sh_spi_set_cs(ss, cs);
 121
 122         clear_fifo(ss);
 123
 124         /* 1/8 clock */
 125         sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
 126         udelay(10);
 127
 128         return &ss->slave;
 129 }
 130
 131 void spi_free_slave(struct spi_slave *slave)
 132 {
 133         struct sh_spi *spi = to_sh_spi(slave);
 134
 135         free(spi);
 136 }
 137
 138 int spi_claim_bus(struct spi_slave *slave)
 139 {
 140         return 0;
 141 }
 142
 143 void spi_release_bus(struct spi_slave *slave)
 144 {
 145         struct sh_spi *ss = to_sh_spi(slave);
 146
 147         sh_spi_write(sh_spi_read(&ss->regs->cr1) &
 148                 ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
 149 }
 150
 151 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
 152                         unsigned int len, unsigned long flags)
 153 {
 154         int i, cur_len, ret = 0;
 155         int remain = (int)len;
 156         unsigned long tmp;
 157
 158         if (len >= SH_SPI_FIFO_SIZE)
 159                 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 160
 161         while (remain > 0) {
 162                 cur_len = (remain < SH_SPI_FIFO_SIZE) ?
 163                                 remain : SH_SPI_FIFO_SIZE;
 164                 for (i = 0; i < cur_len &&
 165                         !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
 166                         !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
 167                                 i++)
 168                         sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
 169
 170                 cur_len = i;
 171
 172                 if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
 173                         /* Abort the transaction */
 174                         flags |= SPI_XFER_END;
 175                         sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
 176                         ret = 1;
 177                         break;
 178                 }
 179
 180                 remain -= cur_len;
 181                 tx_data += cur_len;
 182
 183                 if (remain > 0)
 184                         write_fifo_empty_wait(ss);
 185         }
 186
 187         if (flags & SPI_XFER_END) {
 188                 tmp = sh_spi_read(&ss->regs->cr1);
 189                 tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
 190                 sh_spi_write(tmp, &ss->regs->cr1);
 191                 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 192                 udelay(100);
 193                 write_fifo_empty_wait(ss);
 194         }
 195
 196         return ret;
 197 }
 198
 199 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
 200                           unsigned int len, unsigned long flags)
 201 {
 202         int i;
 203         unsigned long tmp;
 204
 205         if (len > SH_SPI_MAX_BYTE)
 206                 sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
 207         else
 208                 sh_spi_write(len, &ss->regs->cr3);
 209
 210         tmp = sh_spi_read(&ss->regs->cr1);
 211         tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
 212         sh_spi_write(tmp, &ss->regs->cr1);
 213         sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 214
 215         for (i = 0; i < len; i++) {
 216                 if (recvbuf_wait(ss))
 217                         return 0;
 218
 219                 rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
 220         }
 221         sh_spi_write(0, &ss->regs->cr3);
 222
 223         return 0;
 224 }
 225
 226 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 227                 void *din, unsigned long flags)
 228 {
 229         struct sh_spi *ss = to_sh_spi(slave);
 230         const unsigned char *tx_data = dout;
 231         unsigned char *rx_data = din;
 232         unsigned int len = bitlen / 8;
 233         int ret = 0;
 234
 235         if (flags & SPI_XFER_BEGIN)
 236                 sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
 237                                 &ss->regs->cr1);
 238
 239         if (tx_data)
 240                 ret = sh_spi_send(ss, tx_data, len, flags);
 241
 242         if (ret == 0 && rx_data)
 243                 ret = sh_spi_receive(ss, rx_data, len, flags);
 244
 245         if (flags & SPI_XFER_END) {
 246                 sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
 247                 udelay(100);
 248
 249                 sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
 250                                  &ss->regs->cr1);
 251                 clear_fifo(ss);
 252         }
 253
 254         return ret;
 255 }
 256
 257 int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
 258 {
 259         if (!bus && cs < SH_SPI_NUM_CS)
 260                 return 1;
 261         else
 262                 return 0;
 263 }
 264
 265 void spi_cs_activate(struct spi_slave *slave)
 266 {
 267
 268 }
 269
 270 void spi_cs_deactivate(struct spi_slave *slave)
 271 {
 272
 273 }