drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
  10  * to uboot.
  11  *
  12  * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <common.h>
  18 #include <malloc.h>
  19 #include <asm/io.h>
  20 #include <linux/usb/dwc3-omap.h>
  21 #include <linux/ioport.h>
  22
  23 #include <linux/usb/otg.h>
  24 #include <linux/compat.h>
  25
  26 #include "linux-compat.h"
  27
  28 /*
  29  * All these registers belong to OMAP's Wrapper around the
  30  * DesignWare USB3 Core.
  31  */
  32
  33 #define USBOTGSS_REVISION                       0x0000
  34 #define USBOTGSS_SYSCONFIG                      0x0010
  35 #define USBOTGSS_IRQ_EOI                        0x0020
  36 #define USBOTGSS_EOI_OFFSET                     0x0008
  37 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  38 #define USBOTGSS_IRQSTATUS_0                    0x0028
  39 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  40 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  41 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  42 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  43 #define USBOTGSS_IRQSTATUS_1                    0x0034
  44 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  45 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  46 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  47 #define USBOTGSS_IRQSTATUS_2                    0x0044
  48 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  49 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  50 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  51 #define USBOTGSS_IRQSTATUS_3                    0x0054
  52 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  53 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  54 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  55 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  56 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  57 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  58 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  59 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  60 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  61 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  62 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  63 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  64 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  65 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  66 #define USBOTGSS_FLADJ                          0x0104
  67 #define USBOTGSS_DEBUG_CFG                      0x0108
  68 #define USBOTGSS_DEBUG_DATA                     0x010c
  69 #define USBOTGSS_DEV_EBC_EN                     0x0110
  70 #define USBOTGSS_DEBUG_OFFSET                   0x0600
  71
  72 /* SYSCONFIG REGISTER */
  73 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  74
  75 /* IRQ_EOI REGISTER */
  76 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  77
  78 /* IRQS0 BITS */
  79 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  80
  81 /* IRQMISC BITS */
  82 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
  83 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
  84 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
  85 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
  86 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
  87 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
  88 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
  89 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
  90 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
  91 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
  92
  93 /* UTMI_OTG_CTRL REGISTER */
  94 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
  95 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
  96 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
  97 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
  98
  99 /* UTMI_OTG_STATUS REGISTER */
 100 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 101 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 102 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 103 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 104 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 105 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 106 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 107
 108 struct dwc3_omap {
 109         struct device           *dev;
 110
 111         void __iomem            *base;
 112
 113         u32                     utmi_otg_status;
 114         u32                     utmi_otg_offset;
 115         u32                     irqmisc_offset;
 116         u32                     irq_eoi_offset;
 117         u32                     debug_offset;
 118         u32                     irq0_offset;
 119
 120         u32                     dma_status:1;
 121 };
 122
 123 enum omap_dwc3_vbus_id_status {
 124         OMAP_DWC3_ID_FLOAT,
 125         OMAP_DWC3_ID_GROUND,
 126         OMAP_DWC3_VBUS_OFF,
 127         OMAP_DWC3_VBUS_VALID,
 128 };
 129
 130 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 131 {
 132         return readl(base + offset);
 133 }
 134
 135 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 136 {
 137         writel(value, base + offset);
 138 }
 139
 140 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
 141 {
 142         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 143                                                         omap->utmi_otg_offset);
 144 }
 145
 146 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
 147 {
 148         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 149                                         omap->utmi_otg_offset, value);
 150
 151 }
 152
 153 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 154 {
 155         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
 156                                                 omap->irq0_offset);
 157 }
 158
 159 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 160 {
 161         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 162                                                 omap->irq0_offset, value);
 163
 164 }
 165
 166 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 167 {
 168         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
 169                                                 omap->irqmisc_offset);
 170 }
 171
 172 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 173 {
 174         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 175                                         omap->irqmisc_offset, value);
 176
 177 }
 178
 179 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 180 {
 181         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 182                                                 omap->irqmisc_offset, value);
 183
 184 }
 185
 186 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 187 {
 188         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 189                                                 omap->irq0_offset, value);
 190 }
 191
 192 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 193         enum omap_dwc3_vbus_id_status status)
 194 {
 195         u32     val;
 196
 197         switch (status) {
 198         case OMAP_DWC3_ID_GROUND:
 199                 dev_dbg(omap->dev, "ID GND\n");
 200
 201                 val = dwc3_omap_read_utmi_status(omap);
 202                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
 203                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 204                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
 205                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 206                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 207                 dwc3_omap_write_utmi_status(omap, val);
 208                 break;
 209
 210         case OMAP_DWC3_VBUS_VALID:
 211                 dev_dbg(omap->dev, "VBUS Connect\n");
 212
 213                 val = dwc3_omap_read_utmi_status(omap);
 214                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
 215                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
 216                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 217                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 218                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 219                 dwc3_omap_write_utmi_status(omap, val);
 220                 break;
 221
 222         case OMAP_DWC3_ID_FLOAT:
 223         case OMAP_DWC3_VBUS_OFF:
 224                 dev_dbg(omap->dev, "VBUS Disconnect\n");
 225
 226                 val = dwc3_omap_read_utmi_status(omap);
 227                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 228                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 229                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
 230                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
 231                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
 232                 dwc3_omap_write_utmi_status(omap, val);
 233                 break;
 234
 235         default:
 236                 dev_dbg(omap->dev, "invalid state\n");
 237         }
 238 }
 239
 240 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 241 {
 242         struct dwc3_omap        *omap = _omap;
 243         u32                     reg;
 244
 245         reg = dwc3_omap_read_irqmisc_status(omap);
 246
 247         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
 248                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 249                 omap->dma_status = false;
 250         }
 251
 252         if (reg & USBOTGSS_IRQMISC_OEVT)
 253                 dev_dbg(omap->dev, "OTG Event\n");
 254
 255         if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
 256                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 257
 258         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
 259                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 260
 261         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
 262                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 263
 264         if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
 265                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 266
 267         if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
 268                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 269
 270         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
 271                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 272
 273         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
 274                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 275
 276         if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
 277                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 278
 279         dwc3_omap_write_irqmisc_status(omap, reg);
 280
 281         reg = dwc3_omap_read_irq0_status(omap);
 282
 283         dwc3_omap_write_irq0_status(omap, reg);
 284
 285         return IRQ_HANDLED;
 286 }
 287
 288 static int dwc3_omap_remove_core(struct device *dev, void *c)
 289 {
 290         struct platform_device *pdev = to_platform_device(dev);
 291
 292         of_device_unregister(pdev);
 293
 294         return 0;
 295 }
 296
 297 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 298 {
 299         u32                     reg;
 300
 301         /* enable all IRQs */
 302         reg = USBOTGSS_IRQO_COREIRQ_ST;
 303         dwc3_omap_write_irq0_set(omap, reg);
 304
 305         reg = (USBOTGSS_IRQMISC_OEVT |
 306                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 307                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 308                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 309                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 310                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 311                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 312                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 313                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 314
 315         dwc3_omap_write_irqmisc_set(omap, reg);
 316 }
 317
 318 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 319 {
 320         /* disable all IRQs */
 321         dwc3_omap_write_irqmisc_set(omap, 0x00);
 322         dwc3_omap_write_irq0_set(omap, 0x00);
 323 }
 324
 325 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
 326
 327 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
 328 {
 329         struct device_node      *node = omap->dev->of_node;
 330
 331         /*
 332          * Differentiate between OMAP5 and AM437x.
 333          *
 334          * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
 335          * though there are changes in wrapper register offsets.
 336          *
 337          * Using dt compatible to differentiate AM437x.
 338          */
 339         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
 340                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 341                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 342                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 343                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 344                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 345         }
 346 }
 347
 348 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
 349 {
 350         u32                     reg;
 351         struct device_node      *node = omap->dev->of_node;
 352         int                     utmi_mode = 0;
 353
 354         reg = dwc3_omap_read_utmi_status(omap);
 355
 356         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 357
 358         switch (utmi_mode) {
 359         case DWC3_OMAP_UTMI_MODE_SW:
 360                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 361                 break;
 362         case DWC3_OMAP_UTMI_MODE_HW:
 363                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 364                 break;
 365         default:
 366                 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 367         }
 368
 369         dwc3_omap_write_utmi_status(omap, reg);
 370 }
 371
 372 static int dwc3_omap_probe(struct platform_device *pdev)
 373 {
 374         struct device_node      *node = pdev->dev.of_node;
 375
 376         struct dwc3_omap        *omap;
 377         struct resource         *res;
 378         struct device           *dev = &pdev->dev;
 379
 380         int                     ret;
 381         u32                     reg;
 382
 383         void __iomem            *base;
 384
 385         if (!node) {
 386                 dev_err(dev, "device node not found\n");
 387                 return -EINVAL;
 388         }
 389
 390         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 391         if (!omap)
 392                 return -ENOMEM;
 393
 394         platform_set_drvdata(pdev, omap);
 395
 396         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 397         base = devm_ioremap_resource(dev, res);
 398         if (IS_ERR(base))
 399                 return PTR_ERR(base);
 400
 401         omap->dev       = dev;
 402         omap->base      = base;
 403         dev->dma_mask   = &dwc3_omap_dma_mask;
 404
 405         dwc3_omap_map_offset(omap);
 406         dwc3_omap_set_utmi_mode(omap);
 407
 408         /* check the DMA Status */
 409         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 410         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 411
 412         dwc3_omap_enable_irqs(omap);
 413
 414         ret = of_platform_populate(node, NULL, NULL, dev);
 415         if (ret) {
 416                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 417                 goto err1;
 418         }
 419
 420         return 0;
 421
 422 err1:
 423         dwc3_omap_disable_irqs(omap);
 424
 425 err0:
 426         return ret;
 427 }
 428
 429 static int dwc3_omap_remove(struct platform_device *pdev)
 430 {
 431         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 432
 433         dwc3_omap_disable_irqs(omap);
 434         device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
 435
 436         return 0;
 437 }
 438
 439 static const struct of_device_id of_dwc3_match[] = {
 440         {
 441                 .compatible =   "ti,dwc3"
 442         },
 443         {
 444                 .compatible =   "ti,am437x-dwc3"
 445         },
 446         { },
 447 };
 448 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 449
 450 static struct platform_driver dwc3_omap_driver = {
 451         .probe          = dwc3_omap_probe,
 452         .remove         = dwc3_omap_remove,
 453         .driver         = {
 454                 .name   = "omap-dwc3",
 455                 .of_match_table = of_dwc3_match,
 456         },
 457 };
 458
 459 module_platform_driver(dwc3_omap_driver);
 460
 461 MODULE_ALIAS("platform:omap-dwc3");
 462 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 463 MODULE_LICENSE("GPL v2");
 464 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");