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USB: EXYNOS: Set USB 2.0 HOST Link mode
[karo-tx-uboot.git] / drivers / usb / host / ehci-exynos.c
1 /*
2  * SAMSUNG EXYNOS USB HOST EHCI Controller
3  *
4  * Copyright (C) 2012 Samsung Electronics Co.Ltd
5  *      Vivek Gautam <gautam.vivek@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20  * MA 02110-1301 USA
21  */
22
23 #include <common.h>
24 #include <usb.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/ehci.h>
27 #include <asm/arch/system.h>
28 #include "ehci.h"
29 #include "ehci-core.h"
30
31 /* Setup the EHCI host controller. */
32 static void setup_usb_phy(struct exynos_usb_phy *usb)
33 {
34         set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
35
36         clrbits_le32(&usb->usbphyctrl0,
37                         HOST_CTRL0_FSEL_MASK |
38                         HOST_CTRL0_COMMONON_N |
39                         /* HOST Phy setting */
40                         HOST_CTRL0_PHYSWRST |
41                         HOST_CTRL0_PHYSWRSTALL |
42                         HOST_CTRL0_SIDDQ |
43                         HOST_CTRL0_FORCESUSPEND |
44                         HOST_CTRL0_FORCESLEEP);
45
46         setbits_le32(&usb->usbphyctrl0,
47                         /* Setting up the ref freq */
48                         (CLK_24MHZ << 16) |
49                         /* HOST Phy setting */
50                         HOST_CTRL0_LINKSWRST |
51                         HOST_CTRL0_UTMISWRST);
52         udelay(10);
53         clrbits_le32(&usb->usbphyctrl0,
54                         HOST_CTRL0_LINKSWRST |
55                         HOST_CTRL0_UTMISWRST);
56         udelay(20);
57
58         /* EHCI Ctrl setting */
59         setbits_le32(&usb->ehcictrl,
60                         EHCICTRL_ENAINCRXALIGN |
61                         EHCICTRL_ENAINCR4 |
62                         EHCICTRL_ENAINCR8 |
63                         EHCICTRL_ENAINCR16);
64 }
65
66 /* Reset the EHCI host controller. */
67 static void reset_usb_phy(struct exynos_usb_phy *usb)
68 {
69         /* HOST_PHY reset */
70         setbits_le32(&usb->usbphyctrl0,
71                         HOST_CTRL0_PHYSWRST |
72                         HOST_CTRL0_PHYSWRSTALL |
73                         HOST_CTRL0_SIDDQ |
74                         HOST_CTRL0_FORCESUSPEND |
75                         HOST_CTRL0_FORCESLEEP);
76 }
77
78 /*
79  * EHCI-initialization
80  * Create the appropriate control structures to manage
81  * a new EHCI host controller.
82  */
83 int ehci_hcd_init(void)
84 {
85         struct exynos_usb_phy *usb;
86
87         usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
88         setup_usb_phy(usb);
89
90         hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
91         hcor = (struct ehci_hcor *)((uint32_t) hccr
92                                 + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
93
94         debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
95                 (uint32_t)hccr, (uint32_t)hcor,
96                 (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
97
98         return 0;
99 }
100
101 /*
102  * Destroy the appropriate control structures corresponding
103  * the EHCI host controller.
104  */
105 int ehci_hcd_stop()
106 {
107         struct exynos_usb_phy *usb;
108
109         usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
110         reset_usb_phy(usb);
111
112         return 0;
113 }