drivers/usb/host/ehci-marvell.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <usb.h>
  28 #include "ehci.h"
  29 #include "ehci-core.h"
  30 #include <asm/arch/cpu.h>
  31 #include <asm/arch/kirkwood.h>
  32
  33 #define rdl(off)        readl(KW_USB20_BASE + (off))
  34 #define wrl(off, val)   writel((val), KW_USB20_BASE + (off))
  35
  36 #define USB_WINDOW_CTRL(i)      (0x320 + ((i) << 4))
  37 #define USB_WINDOW_BASE(i)      (0x324 + ((i) << 4))
  38 #define USB_TARGET_DRAM         0x0
  39
  40 /*
  41  * USB 2.0 Bridge Address Decoding registers setup
  42  */
  43 static void usb_brg_adrdec_setup(void)
  44 {
  45         int i;
  46         u32 size, attrib;
  47
  48         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  49
  50                 /* Enable DRAM bank */
  51                 switch (i) {
  52                 case 0:
  53                         attrib = KWCPU_ATTR_DRAM_CS0;
  54                         break;
  55                 case 1:
  56                         attrib = KWCPU_ATTR_DRAM_CS1;
  57                         break;
  58                 case 2:
  59                         attrib = KWCPU_ATTR_DRAM_CS2;
  60                         break;
  61                 case 3:
  62                         attrib = KWCPU_ATTR_DRAM_CS3;
  63                         break;
  64                 default:
  65                         /* invalide bank, disable access */
  66                         attrib = 0;
  67                         break;
  68                 }
  69
  70                 size = kw_sdram_bs(i);
  71                 if ((size) && (attrib))
  72                         wrl(USB_WINDOW_CTRL(i),
  73                                 KWCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
  74                                         attrib, KWCPU_WIN_ENABLE));
  75                 else
  76                         wrl(USB_WINDOW_CTRL(i), KWCPU_WIN_DISABLE);
  77
  78                 wrl(USB_WINDOW_BASE(i), kw_sdram_bar(i));
  79         }
  80 }
  81
  82 /*
  83  * Create the appropriate control structures to manage
  84  * a new EHCI host controller.
  85  */
  86 int ehci_hcd_init(void)
  87 {
  88         usb_brg_adrdec_setup();
  89
  90         hccr = (struct ehci_hccr *)(KW_USB20_BASE + 0x100);
  91         hcor = (struct ehci_hcor *)((uint32_t) hccr
  92                         + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  93
  94         debug("Kirkwood-ehci: init hccr %x and hcor %x hc_length %d\n",
  95                 (uint32_t)hccr, (uint32_t)hcor,
  96                 (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  97
  98         return 0;
  99 }
 100
 101 /*
 102  * Destroy the appropriate control structures corresponding
 103  * the the EHCI host controller.
 104  */
 105 int ehci_hcd_stop(void)
 106 {
 107         return 0;
 108 }