drivers/usb/host/ohci-hcd.c

   1 /*
   2  * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
   3  *
   4  * Interrupt support is added. Now, it has been tested
   5  * on ULI1575 chip and works well with USB keyboard.
   6  *
   7  * (C) Copyright 2007
   8  * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
   9  *
  10  * (C) Copyright 2003
  11  * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  12  *
  13  * Note: Much of this code has been derived from Linux 2.4
  14  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  15  * (C) Copyright 2000-2002 David Brownell
  16  *
  17  * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  18  * ebenard@eukrea.com - based on s3c24x0's driver
  19  *
  20  * SPDX-License-Identifier:     GPL-2.0+
  21  */
  22 /*
  23  * IMPORTANT NOTES
  24  * 1 - Read doc/README.generic_usb_ohci
  25  * 2 - this driver is intended for use with USB Mass Storage Devices
  26  *     (BBB) and USB keyboard. There is NO support for Isochronous pipes!
  27  * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  28  *     to activate workaround for bug #41 or this driver will NOT work!
  29  */
  30
  31 #include <common.h>
  32 #include <asm/byteorder.h>
  33
  34 #if defined(CONFIG_PCI_OHCI)
  35 # include <pci.h>
  36 #if !defined(CONFIG_PCI_OHCI_DEVNO)
  37 #define CONFIG_PCI_OHCI_DEVNO   0
  38 #endif
  39 #endif
  40
  41 #include <malloc.h>
  42 #include <usb.h>
  43
  44 #include "ohci.h"
  45
  46 #ifdef CONFIG_AT91RM9200
  47 #include <asm/arch/hardware.h>  /* needed for AT91_USB_HOST_BASE */
  48 #endif
  49
  50 #if defined(CONFIG_CPU_ARM920T) || \
  51     defined(CONFIG_S3C24X0) || \
  52     defined(CONFIG_440EP) || \
  53     defined(CONFIG_PCI_OHCI) || \
  54     defined(CONFIG_MPC5200) || \
  55     defined(CONFIG_SYS_OHCI_USE_NPS)
  56 # define OHCI_USE_NPS           /* force NoPowerSwitching mode */
  57 #endif
  58
  59 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  60 #undef DEBUG
  61 #undef SHOW_INFO
  62 #undef OHCI_FILL_TRACE
  63
  64 /* For initializing controller (mask in an HCFS mode too) */
  65 #define OHCI_CONTROL_INIT \
  66         (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  67
  68 #ifdef CONFIG_PCI_OHCI
  69 static struct pci_device_id ohci_pci_ids[] = {
  70         {0x10b9, 0x5237},       /* ULI1575 PCI OHCI module ids */
  71         {0x1033, 0x0035},       /* NEC PCI OHCI module ids */
  72         {0x1131, 0x1561},       /* Philips 1561 PCI OHCI module ids */
  73         /* Please add supported PCI OHCI controller ids here */
  74         {0, 0}
  75 };
  76 #endif
  77
  78 #ifdef CONFIG_PCI_EHCI_DEVNO
  79 static struct pci_device_id ehci_pci_ids[] = {
  80         {0x1131, 0x1562},       /* Philips 1562 PCI EHCI module ids */
  81         /* Please add supported PCI EHCI controller ids here */
  82         {0, 0}
  83 };
  84 #endif
  85
  86 #ifdef DEBUG
  87 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  88 #else
  89 #define dbg(format, arg...) do {} while (0)
  90 #endif /* DEBUG */
  91 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  92 #ifdef SHOW_INFO
  93 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  94 #else
  95 #define info(format, arg...) do {} while (0)
  96 #endif
  97
  98 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
  99 # define m16_swap(x) cpu_to_be16(x)
 100 # define m32_swap(x) cpu_to_be32(x)
 101 #else
 102 # define m16_swap(x) cpu_to_le16(x)
 103 # define m32_swap(x) cpu_to_le32(x)
 104 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
 105
 106 #ifdef CONFIG_DM_USB
 107 /*
 108  * We really should do proper cache flushing everywhere, but for now we only
 109  * do it for new (driver-model) usb code to avoid regressions.
 110  */
 111 #define flush_dcache_buffer(addr, size) \
 112         flush_dcache_range((unsigned long)(addr), \
 113                 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
 114 #define invalidate_dcache_buffer(addr, size) \
 115         invalidate_dcache_range((unsigned long)(addr), \
 116                 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
 117 #else
 118 #define flush_dcache_buffer(addr, size)
 119 #define invalidate_dcache_buffer(addr, size)
 120 #endif
 121
 122 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
 123 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
 124 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16)
 125 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32)
 126 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256)
 127 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16)
 128 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16)
 129 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32)
 130 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256)
 131
 132 /* global ohci_t */
 133 static ohci_t gohci;
 134 /* this must be aligned to a 256 byte boundary */
 135 struct ohci_hcca ghcca[1];
 136
 137 /* mapping of the OHCI CC status to error codes */
 138 static int cc_to_error[16] = {
 139         /* No  Error  */               0,
 140         /* CRC Error  */               USB_ST_CRC_ERR,
 141         /* Bit Stuff  */               USB_ST_BIT_ERR,
 142         /* Data Togg  */               USB_ST_CRC_ERR,
 143         /* Stall      */               USB_ST_STALLED,
 144         /* DevNotResp */               -1,
 145         /* PIDCheck   */               USB_ST_BIT_ERR,
 146         /* UnExpPID   */               USB_ST_BIT_ERR,
 147         /* DataOver   */               USB_ST_BUF_ERR,
 148         /* DataUnder  */               USB_ST_BUF_ERR,
 149         /* reservd    */               -1,
 150         /* reservd    */               -1,
 151         /* BufferOver */               USB_ST_BUF_ERR,
 152         /* BuffUnder  */               USB_ST_BUF_ERR,
 153         /* Not Access */               -1,
 154         /* Not Access */               -1
 155 };
 156
 157 static const char *cc_to_string[16] = {
 158         "No Error",
 159         "CRC: Last data packet from endpoint contained a CRC error.",
 160         "BITSTUFFING: Last data packet from endpoint contained a bit " \
 161                      "stuffing violation",
 162         "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
 163                      "that did not match the expected value.",
 164         "STALL: TD was moved to the Done Queue because the endpoint returned" \
 165                      " a STALL PID",
 166         "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
 167                      "not provide a handshake (OUT)",
 168         "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
 169                      "(IN) or handshake (OUT)",
 170         "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
 171                      "value is not defined.",
 172         "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
 173                      "either the size of the maximum data packet allowed\n" \
 174                      "from the endpoint (found in MaximumPacketSize field\n" \
 175                      "of ED) or the remaining buffer size.",
 176         "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
 177                      "and that amount was not sufficient to fill the\n" \
 178                      "specified buffer",
 179         "reserved1",
 180         "reserved2",
 181         "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
 182                      "than it could be written to system memory",
 183         "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
 184                      "system memory fast enough to keep up with data USB " \
 185                      "data rate.",
 186         "NOT ACCESSED: This code is set by software before the TD is placed" \
 187                      "on a list to be processed by the HC.(1)",
 188         "NOT ACCESSED: This code is set by software before the TD is placed" \
 189                      "on a list to be processed by the HC.(2)",
 190 };
 191
 192 static inline u32 roothub_a(struct ohci *hc)
 193         { return ohci_readl(&hc->regs->roothub.a); }
 194 static inline u32 roothub_b(struct ohci *hc)
 195         { return ohci_readl(&hc->regs->roothub.b); }
 196 static inline u32 roothub_status(struct ohci *hc)
 197         { return ohci_readl(&hc->regs->roothub.status); }
 198 static inline u32 roothub_portstatus(struct ohci *hc, int i)
 199         { return ohci_readl(&hc->regs->roothub.portstatus[i]); }
 200
 201 /* forward declaration */
 202 static int hc_interrupt(ohci_t *ohci);
 203 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
 204                           unsigned long pipe, void *buffer, int transfer_len,
 205                           struct devrequest *setup, urb_priv_t *urb,
 206                           int interval);
 207 static int ep_link(ohci_t * ohci, ed_t * ed);
 208 static int ep_unlink(ohci_t * ohci, ed_t * ed);
 209 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
 210                        unsigned long pipe, int interval, int load);
 211
 212 /*-------------------------------------------------------------------------*/
 213
 214 /* TDs ... */
 215 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev)
 216 {
 217         int i;
 218         struct td *td;
 219
 220         td = NULL;
 221         for (i = 0; i < NUM_TD; i++)
 222         {
 223                 if (ohci_dev->tds[i].usb_dev == NULL)
 224                 {
 225                         td = &ohci_dev->tds[i];
 226                         td->usb_dev = usb_dev;
 227                         break;
 228                 }
 229         }
 230
 231         return td;
 232 }
 233
 234 static inline void ed_free(struct ed *ed)
 235 {
 236         ed->usb_dev = NULL;
 237 }
 238
 239 /*-------------------------------------------------------------------------*
 240  * URB support functions
 241  *-------------------------------------------------------------------------*/
 242
 243 /* free HCD-private data associated with this URB */
 244
 245 static void urb_free_priv(urb_priv_t *urb)
 246 {
 247         int             i;
 248         int             last;
 249         struct td       *td;
 250
 251         last = urb->length - 1;
 252         if (last >= 0) {
 253                 for (i = 0; i <= last; i++) {
 254                         td = urb->td[i];
 255                         if (td) {
 256                                 td->usb_dev = NULL;
 257                                 urb->td[i] = NULL;
 258                         }
 259                 }
 260         }
 261         free(urb);
 262 }
 263
 264 /*-------------------------------------------------------------------------*/
 265
 266 #ifdef DEBUG
 267 static int sohci_get_current_frame_number(ohci_t *ohci);
 268
 269 /* debug| print the main components of an URB
 270  * small: 0) header + data packets 1) just header */
 271
 272 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
 273                       unsigned long pipe, void *buffer, int transfer_len,
 274                       struct devrequest *setup, char *str, int small)
 275 {
 276         dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
 277                         str,
 278                         sohci_get_current_frame_number(ohci),
 279                         usb_pipedevice(pipe),
 280                         usb_pipeendpoint(pipe),
 281                         usb_pipeout(pipe)? 'O': 'I',
 282                         usb_pipetype(pipe) < 2 ? \
 283                                 (usb_pipeint(pipe)? "INTR": "ISOC"): \
 284                                 (usb_pipecontrol(pipe)? "CTRL": "BULK"),
 285                         (purb ? purb->actual_length : 0),
 286                         transfer_len, dev->status);
 287 #ifdef  OHCI_VERBOSE_DEBUG
 288         if (!small) {
 289                 int i, len;
 290
 291                 if (usb_pipecontrol(pipe)) {
 292                         printf(__FILE__ ": cmd(8):");
 293                         for (i = 0; i < 8 ; i++)
 294                                 printf(" %02x", ((__u8 *) setup) [i]);
 295                         printf("\n");
 296                 }
 297                 if (transfer_len > 0 && buffer) {
 298                         printf(__FILE__ ": data(%d/%d):",
 299                                 (purb ? purb->actual_length : 0),
 300                                 transfer_len);
 301                         len = usb_pipeout(pipe)? transfer_len:
 302                                         (purb ? purb->actual_length : 0);
 303                         for (i = 0; i < 16 && i < len; i++)
 304                                 printf(" %02x", ((__u8 *) buffer) [i]);
 305                         printf("%s\n", i < len? "...": "");
 306                 }
 307         }
 308 #endif
 309 }
 310
 311 /* just for debugging; prints non-empty branches of the int ed tree
 312  * inclusive iso eds */
 313 void ep_print_int_eds(ohci_t *ohci, char *str)
 314 {
 315         int i, j;
 316          __u32 *ed_p;
 317         for (i = 0; i < 32; i++) {
 318                 j = 5;
 319                 ed_p = &(ohci->hcca->int_table [i]);
 320                 if (*ed_p == 0)
 321                     continue;
 322                 invalidate_dcache_ed(ed_p);
 323                 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
 324                 while (*ed_p != 0 && j--) {
 325                         ed_t *ed = (ed_t *)m32_swap(ed_p);
 326                         invalidate_dcache_ed(ed);
 327                         printf(" ed: %4x;", ed->hwINFO);
 328                         ed_p = &ed->hwNextED;
 329                 }
 330                 printf("\n");
 331         }
 332 }
 333
 334 static void ohci_dump_intr_mask(char *label, __u32 mask)
 335 {
 336         dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
 337                 label,
 338                 mask,
 339                 (mask & OHCI_INTR_MIE) ? " MIE" : "",
 340                 (mask & OHCI_INTR_OC) ? " OC" : "",
 341                 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
 342                 (mask & OHCI_INTR_FNO) ? " FNO" : "",
 343                 (mask & OHCI_INTR_UE) ? " UE" : "",
 344                 (mask & OHCI_INTR_RD) ? " RD" : "",
 345                 (mask & OHCI_INTR_SF) ? " SF" : "",
 346                 (mask & OHCI_INTR_WDH) ? " WDH" : "",
 347                 (mask & OHCI_INTR_SO) ? " SO" : ""
 348                 );
 349 }
 350
 351 static void maybe_print_eds(char *label, __u32 value)
 352 {
 353         ed_t *edp = (ed_t *)value;
 354
 355         if (value) {
 356                 dbg("%s %08x", label, value);
 357                 invalidate_dcache_ed(edp);
 358                 dbg("%08x", edp->hwINFO);
 359                 dbg("%08x", edp->hwTailP);
 360                 dbg("%08x", edp->hwHeadP);
 361                 dbg("%08x", edp->hwNextED);
 362         }
 363 }
 364
 365 static char *hcfs2string(int state)
 366 {
 367         switch (state) {
 368         case OHCI_USB_RESET:    return "reset";
 369         case OHCI_USB_RESUME:   return "resume";
 370         case OHCI_USB_OPER:     return "operational";
 371         case OHCI_USB_SUSPEND:  return "suspend";
 372         }
 373         return "?";
 374 }
 375
 376 /* dump control and status registers */
 377 static void ohci_dump_status(ohci_t *controller)
 378 {
 379         struct ohci_regs        *regs = controller->regs;
 380         __u32                   temp;
 381
 382         temp = ohci_readl(&regs->revision) & 0xff;
 383         if (temp != 0x10)
 384                 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
 385
 386         temp = ohci_readl(&regs->control);
 387         dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
 388                 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
 389                 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
 390                 (temp & OHCI_CTRL_IR) ? " IR" : "",
 391                 hcfs2string(temp & OHCI_CTRL_HCFS),
 392                 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
 393                 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
 394                 (temp & OHCI_CTRL_IE) ? " IE" : "",
 395                 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
 396                 temp & OHCI_CTRL_CBSR
 397                 );
 398
 399         temp = ohci_readl(&regs->cmdstatus);
 400         dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
 401                 (temp & OHCI_SOC) >> 16,
 402                 (temp & OHCI_OCR) ? " OCR" : "",
 403                 (temp & OHCI_BLF) ? " BLF" : "",
 404                 (temp & OHCI_CLF) ? " CLF" : "",
 405                 (temp & OHCI_HCR) ? " HCR" : ""
 406                 );
 407
 408         ohci_dump_intr_mask("intrstatus", ohci_readl(&regs->intrstatus));
 409         ohci_dump_intr_mask("intrenable", ohci_readl(&regs->intrenable));
 410
 411         maybe_print_eds("ed_periodcurrent",
 412                         ohci_readl(&regs->ed_periodcurrent));
 413
 414         maybe_print_eds("ed_controlhead", ohci_readl(&regs->ed_controlhead));
 415         maybe_print_eds("ed_controlcurrent",
 416                         ohci_readl(&regs->ed_controlcurrent));
 417
 418         maybe_print_eds("ed_bulkhead", ohci_readl(&regs->ed_bulkhead));
 419         maybe_print_eds("ed_bulkcurrent", ohci_readl(&regs->ed_bulkcurrent));
 420
 421         maybe_print_eds("donehead", ohci_readl(&regs->donehead));
 422 }
 423
 424 static void ohci_dump_roothub(ohci_t *controller, int verbose)
 425 {
 426         __u32                   temp, ndp, i;
 427
 428         temp = roothub_a(controller);
 429         ndp = (temp & RH_A_NDP);
 430 #ifdef CONFIG_AT91C_PQFP_UHPBUG
 431         ndp = (ndp == 2) ? 1:0;
 432 #endif
 433         if (verbose) {
 434                 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
 435                         ((temp & RH_A_POTPGT) >> 24) & 0xff,
 436                         (temp & RH_A_NOCP) ? " NOCP" : "",
 437                         (temp & RH_A_OCPM) ? " OCPM" : "",
 438                         (temp & RH_A_DT) ? " DT" : "",
 439                         (temp & RH_A_NPS) ? " NPS" : "",
 440                         (temp & RH_A_PSM) ? " PSM" : "",
 441                         ndp
 442                         );
 443                 temp = roothub_b(controller);
 444                 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
 445                         temp,
 446                         (temp & RH_B_PPCM) >> 16,
 447                         (temp & RH_B_DR)
 448                         );
 449                 temp = roothub_status(controller);
 450                 dbg("roothub.status: %08x%s%s%s%s%s%s",
 451                         temp,
 452                         (temp & RH_HS_CRWE) ? " CRWE" : "",
 453                         (temp & RH_HS_OCIC) ? " OCIC" : "",
 454                         (temp & RH_HS_LPSC) ? " LPSC" : "",
 455                         (temp & RH_HS_DRWE) ? " DRWE" : "",
 456                         (temp & RH_HS_OCI) ? " OCI" : "",
 457                         (temp & RH_HS_LPS) ? " LPS" : ""
 458                         );
 459         }
 460
 461         for (i = 0; i < ndp; i++) {
 462                 temp = roothub_portstatus(controller, i);
 463                 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
 464                         i,
 465                         temp,
 466                         (temp & RH_PS_PRSC) ? " PRSC" : "",
 467                         (temp & RH_PS_OCIC) ? " OCIC" : "",
 468                         (temp & RH_PS_PSSC) ? " PSSC" : "",
 469                         (temp & RH_PS_PESC) ? " PESC" : "",
 470                         (temp & RH_PS_CSC) ? " CSC" : "",
 471
 472                         (temp & RH_PS_LSDA) ? " LSDA" : "",
 473                         (temp & RH_PS_PPS) ? " PPS" : "",
 474                         (temp & RH_PS_PRS) ? " PRS" : "",
 475                         (temp & RH_PS_POCI) ? " POCI" : "",
 476                         (temp & RH_PS_PSS) ? " PSS" : "",
 477
 478                         (temp & RH_PS_PES) ? " PES" : "",
 479                         (temp & RH_PS_CCS) ? " CCS" : ""
 480                         );
 481         }
 482 }
 483
 484 static void ohci_dump(ohci_t *controller, int verbose)
 485 {
 486         dbg("OHCI controller usb-%s state", controller->slot_name);
 487
 488         /* dumps some of the state we know about */
 489         ohci_dump_status(controller);
 490         if (verbose)
 491                 ep_print_int_eds(controller, "hcca");
 492         invalidate_dcache_hcca(controller->hcca);
 493         dbg("hcca frame #%04x", controller->hcca->frame_no);
 494         ohci_dump_roothub(controller, 1);
 495 }
 496 #endif /* DEBUG */
 497
 498 /*-------------------------------------------------------------------------*
 499  * Interface functions (URB)
 500  *-------------------------------------------------------------------------*/
 501
 502 /* get a transfer request */
 503
 504 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb,
 505                      struct devrequest *setup)
 506 {
 507         ed_t *ed;
 508         urb_priv_t *purb_priv = urb;
 509         int i, size = 0;
 510         struct usb_device *dev = urb->dev;
 511         unsigned long pipe = urb->pipe;
 512         void *buffer = urb->transfer_buffer;
 513         int transfer_len = urb->transfer_buffer_length;
 514         int interval = urb->interval;
 515
 516         /* when controller's hung, permit only roothub cleanup attempts
 517          * such as powering down ports */
 518         if (ohci->disabled) {
 519                 err("sohci_submit_job: EPIPE");
 520                 return -1;
 521         }
 522
 523         /* we're about to begin a new transaction here so mark the
 524          * URB unfinished */
 525         urb->finished = 0;
 526
 527         /* every endpoint has a ed, locate and fill it */
 528         ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1);
 529         if (!ed) {
 530                 err("sohci_submit_job: ENOMEM");
 531                 return -1;
 532         }
 533
 534         /* for the private part of the URB we need the number of TDs (size) */
 535         switch (usb_pipetype(pipe)) {
 536         case PIPE_BULK: /* one TD for every 4096 Byte */
 537                 size = (transfer_len - 1) / 4096 + 1;
 538                 break;
 539         case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
 540                 size = (transfer_len == 0)? 2:
 541                                         (transfer_len - 1) / 4096 + 3;
 542                 break;
 543         case PIPE_INTERRUPT: /* 1 TD */
 544                 size = 1;
 545                 break;
 546         }
 547
 548         ed->purb = urb;
 549
 550         if (size >= (N_URB_TD - 1)) {
 551                 err("need %d TDs, only have %d", size, N_URB_TD);
 552                 return -1;
 553         }
 554         purb_priv->pipe = pipe;
 555
 556         /* fill the private part of the URB */
 557         purb_priv->length = size;
 558         purb_priv->ed = ed;
 559         purb_priv->actual_length = 0;
 560
 561         /* allocate the TDs */
 562         /* note that td[0] was allocated in ep_add_ed */
 563         for (i = 0; i < size; i++) {
 564                 purb_priv->td[i] = td_alloc(ohci_dev, dev);
 565                 if (!purb_priv->td[i]) {
 566                         purb_priv->length = i;
 567                         urb_free_priv(purb_priv);
 568                         err("sohci_submit_job: ENOMEM");
 569                         return -1;
 570                 }
 571         }
 572
 573         if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
 574                 urb_free_priv(purb_priv);
 575                 err("sohci_submit_job: EINVAL");
 576                 return -1;
 577         }
 578
 579         /* link the ed into a chain if is not already */
 580         if (ed->state != ED_OPER)
 581                 ep_link(ohci, ed);
 582
 583         /* fill the TDs and link it to the ed */
 584         td_submit_job(ohci, dev, pipe, buffer, transfer_len,
 585                       setup, purb_priv, interval);
 586
 587         return 0;
 588 }
 589
 590 /*-------------------------------------------------------------------------*/
 591
 592 #ifdef DEBUG
 593 /* tell us the current USB frame number */
 594 static int sohci_get_current_frame_number(ohci_t *ohci)
 595 {
 596         invalidate_dcache_hcca(ohci->hcca);
 597         return m16_swap(ohci->hcca->frame_no);
 598 }
 599 #endif
 600
 601 /*-------------------------------------------------------------------------*
 602  * ED handling functions
 603  *-------------------------------------------------------------------------*/
 604
 605 /* search for the right branch to insert an interrupt ed into the int tree
 606  * do some load ballancing;
 607  * returns the branch and
 608  * sets the interval to interval = 2^integer (ld (interval)) */
 609
 610 static int ep_int_ballance(ohci_t *ohci, int interval, int load)
 611 {
 612         int i, branch = 0;
 613
 614         /* search for the least loaded interrupt endpoint
 615          * branch of all 32 branches
 616          */
 617         for (i = 0; i < 32; i++)
 618                 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
 619                         branch = i;
 620
 621         branch = branch % interval;
 622         for (i = branch; i < 32; i += interval)
 623                 ohci->ohci_int_load [i] += load;
 624
 625         return branch;
 626 }
 627
 628 /*-------------------------------------------------------------------------*/
 629
 630 /*  2^int( ld (inter)) */
 631
 632 static int ep_2_n_interval(int inter)
 633 {
 634         int i;
 635         for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
 636         return 1 << i;
 637 }
 638
 639 /*-------------------------------------------------------------------------*/
 640
 641 /* the int tree is a binary tree
 642  * in order to process it sequentially the indexes of the branches have to
 643  * be mapped the mapping reverses the bits of a word of num_bits length */
 644 static int ep_rev(int num_bits, int word)
 645 {
 646         int i, wout = 0;
 647
 648         for (i = 0; i < num_bits; i++)
 649                 wout |= (((word >> i) & 1) << (num_bits - i - 1));
 650         return wout;
 651 }
 652
 653 /*-------------------------------------------------------------------------*
 654  * ED handling functions
 655  *-------------------------------------------------------------------------*/
 656
 657 /* link an ed into one of the HC chains */
 658
 659 static int ep_link(ohci_t *ohci, ed_t *edi)
 660 {
 661         volatile ed_t *ed = edi;
 662         int int_branch;
 663         int i;
 664         int inter;
 665         int interval;
 666         int load;
 667         __u32 *ed_p;
 668
 669         ed->state = ED_OPER;
 670         ed->int_interval = 0;
 671
 672         switch (ed->type) {
 673         case PIPE_CONTROL:
 674                 ed->hwNextED = 0;
 675                 flush_dcache_ed(ed);
 676                 if (ohci->ed_controltail == NULL)
 677                         ohci_writel(ed, &ohci->regs->ed_controlhead);
 678                 else
 679                         ohci->ed_controltail->hwNextED =
 680                                                    m32_swap((unsigned long)ed);
 681
 682                 ed->ed_prev = ohci->ed_controltail;
 683                 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
 684                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 685                         ohci->hc_control |= OHCI_CTRL_CLE;
 686                         ohci_writel(ohci->hc_control, &ohci->regs->control);
 687                 }
 688                 ohci->ed_controltail = edi;
 689                 break;
 690
 691         case PIPE_BULK:
 692                 ed->hwNextED = 0;
 693                 flush_dcache_ed(ed);
 694                 if (ohci->ed_bulktail == NULL)
 695                         ohci_writel(ed, &ohci->regs->ed_bulkhead);
 696                 else
 697                         ohci->ed_bulktail->hwNextED =
 698                                                    m32_swap((unsigned long)ed);
 699
 700                 ed->ed_prev = ohci->ed_bulktail;
 701                 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
 702                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 703                         ohci->hc_control |= OHCI_CTRL_BLE;
 704                         ohci_writel(ohci->hc_control, &ohci->regs->control);
 705                 }
 706                 ohci->ed_bulktail = edi;
 707                 break;
 708
 709         case PIPE_INTERRUPT:
 710                 load = ed->int_load;
 711                 interval = ep_2_n_interval(ed->int_period);
 712                 ed->int_interval = interval;
 713                 int_branch = ep_int_ballance(ohci, interval, load);
 714                 ed->int_branch = int_branch;
 715
 716                 for (i = 0; i < ep_rev(6, interval); i += inter) {
 717                         inter = 1;
 718                         for (ed_p = &(ohci->hcca->int_table[\
 719                                                 ep_rev(5, i) + int_branch]);
 720                                 (*ed_p != 0) &&
 721                                 (((ed_t *)ed_p)->int_interval >= interval);
 722                                 ed_p = &(((ed_t *)ed_p)->hwNextED))
 723                                         inter = ep_rev(6,
 724                                                  ((ed_t *)ed_p)->int_interval);
 725                         ed->hwNextED = *ed_p;
 726                         flush_dcache_ed(ed);
 727                         *ed_p = m32_swap((unsigned long)ed);
 728                         flush_dcache_hcca(ohci->hcca);
 729                 }
 730                 break;
 731         }
 732         return 0;
 733 }
 734
 735 /*-------------------------------------------------------------------------*/
 736
 737 /* scan the periodic table to find and unlink this ED */
 738 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
 739                             unsigned index, unsigned period)
 740 {
 741         __maybe_unused unsigned long aligned_ed_p;
 742
 743         for (; index < NUM_INTS; index += period) {
 744                 __u32   *ed_p = &ohci->hcca->int_table [index];
 745
 746                 /* ED might have been unlinked through another path */
 747                 while (*ed_p != 0) {
 748                         if (((struct ed *)
 749                                         m32_swap((unsigned long)ed_p)) == ed) {
 750                                 *ed_p = ed->hwNextED;
 751 #ifdef CONFIG_DM_USB
 752                                 aligned_ed_p = (unsigned long)ed_p;
 753                                 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
 754                                 flush_dcache_range(aligned_ed_p,
 755                                         aligned_ed_p + ARCH_DMA_MINALIGN);
 756 #endif
 757                                 break;
 758                         }
 759                         ed_p = &(((struct ed *)
 760                                      m32_swap((unsigned long)ed_p))->hwNextED);
 761                 }
 762         }
 763 }
 764
 765 /* unlink an ed from one of the HC chains.
 766  * just the link to the ed is unlinked.
 767  * the link from the ed still points to another operational ed or 0
 768  * so the HC can eventually finish the processing of the unlinked ed */
 769
 770 static int ep_unlink(ohci_t *ohci, ed_t *edi)
 771 {
 772         volatile ed_t *ed = edi;
 773         int i;
 774
 775         ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
 776         flush_dcache_ed(ed);
 777
 778         switch (ed->type) {
 779         case PIPE_CONTROL:
 780                 if (ed->ed_prev == NULL) {
 781                         if (!ed->hwNextED) {
 782                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 783                                 ohci_writel(ohci->hc_control,
 784                                             &ohci->regs->control);
 785                         }
 786                         ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
 787                                 &ohci->regs->ed_controlhead);
 788                 } else {
 789                         ed->ed_prev->hwNextED = ed->hwNextED;
 790                         flush_dcache_ed(ed->ed_prev);
 791                 }
 792                 if (ohci->ed_controltail == ed) {
 793                         ohci->ed_controltail = ed->ed_prev;
 794                 } else {
 795                         ((ed_t *)m32_swap(
 796                             *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 797                 }
 798                 break;
 799
 800         case PIPE_BULK:
 801                 if (ed->ed_prev == NULL) {
 802                         if (!ed->hwNextED) {
 803                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 804                                 ohci_writel(ohci->hc_control,
 805                                             &ohci->regs->control);
 806                         }
 807                         ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
 808                                &ohci->regs->ed_bulkhead);
 809                 } else {
 810                         ed->ed_prev->hwNextED = ed->hwNextED;
 811                         flush_dcache_ed(ed->ed_prev);
 812                 }
 813                 if (ohci->ed_bulktail == ed) {
 814                         ohci->ed_bulktail = ed->ed_prev;
 815                 } else {
 816                         ((ed_t *)m32_swap(
 817                              *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 818                 }
 819                 break;
 820
 821         case PIPE_INTERRUPT:
 822                 periodic_unlink(ohci, ed, 0, 1);
 823                 for (i = ed->int_branch; i < 32; i += ed->int_interval)
 824                     ohci->ohci_int_load[i] -= ed->int_load;
 825                 break;
 826         }
 827         ed->state = ED_UNLINK;
 828         return 0;
 829 }
 830
 831 /*-------------------------------------------------------------------------*/
 832
 833 /* add/reinit an endpoint; this should be done once at the
 834  * usb_set_configuration command, but the USB stack is a little bit
 835  * stateless so we do it at every transaction if the state of the ed
 836  * is ED_NEW then a dummy td is added and the state is changed to
 837  * ED_UNLINK in all other cases the state is left unchanged the ed
 838  * info fields are setted anyway even though most of them should not
 839  * change
 840  */
 841 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
 842                        unsigned long pipe, int interval, int load)
 843 {
 844         td_t *td;
 845         ed_t *ed_ret;
 846         volatile ed_t *ed;
 847
 848         ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) |
 849                         (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
 850
 851         if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
 852                 err("ep_add_ed: pending delete");
 853                 /* pending delete request */
 854                 return NULL;
 855         }
 856
 857         if (ed->state == ED_NEW) {
 858                 /* dummy td; end of td list for ed */
 859                 td = td_alloc(ohci_dev, usb_dev);
 860                 ed->hwTailP = m32_swap((unsigned long)td);
 861                 ed->hwHeadP = ed->hwTailP;
 862                 ed->state = ED_UNLINK;
 863                 ed->type = usb_pipetype(pipe);
 864                 ohci_dev->ed_cnt++;
 865         }
 866
 867         ed->hwINFO = m32_swap(usb_pipedevice(pipe)
 868                         | usb_pipeendpoint(pipe) << 7
 869                         | (usb_pipeisoc(pipe)? 0x8000: 0)
 870                         | (usb_pipecontrol(pipe)? 0: \
 871                                            (usb_pipeout(pipe)? 0x800: 0x1000))
 872                         | (usb_dev->speed == USB_SPEED_LOW) << 13
 873                         | usb_maxpacket(usb_dev, pipe) << 16);
 874
 875         if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
 876                 ed->int_period = interval;
 877                 ed->int_load = load;
 878         }
 879
 880         flush_dcache_ed(ed);
 881
 882         return ed_ret;
 883 }
 884
 885 /*-------------------------------------------------------------------------*
 886  * TD handling functions
 887  *-------------------------------------------------------------------------*/
 888
 889 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 890
 891 static void td_fill(ohci_t *ohci, unsigned int info,
 892         void *data, int len,
 893         struct usb_device *dev, int index, urb_priv_t *urb_priv)
 894 {
 895         volatile td_t  *td, *td_pt;
 896 #ifdef OHCI_FILL_TRACE
 897         int i;
 898 #endif
 899
 900         if (index > urb_priv->length) {
 901                 err("index > length");
 902                 return;
 903         }
 904         /* use this td as the next dummy */
 905         td_pt = urb_priv->td [index];
 906         td_pt->hwNextTD = 0;
 907         flush_dcache_td(td_pt);
 908
 909         /* fill the old dummy TD */
 910         td = urb_priv->td [index] =
 911                              (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
 912
 913         td->ed = urb_priv->ed;
 914         td->next_dl_td = NULL;
 915         td->index = index;
 916         td->data = (__u32)data;
 917 #ifdef OHCI_FILL_TRACE
 918         if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
 919                 for (i = 0; i < len; i++)
 920                 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
 921                 printf("\n");
 922         }
 923 #endif
 924         if (!len)
 925                 data = 0;
 926
 927         td->hwINFO = m32_swap(info);
 928         td->hwCBP = m32_swap((unsigned long)data);
 929         if (data)
 930                 td->hwBE = m32_swap((unsigned long)(data + len - 1));
 931         else
 932                 td->hwBE = 0;
 933
 934         td->hwNextTD = m32_swap((unsigned long)td_pt);
 935         flush_dcache_td(td);
 936
 937         /* append to queue */
 938         td->ed->hwTailP = td->hwNextTD;
 939         flush_dcache_ed(td->ed);
 940 }
 941
 942 /*-------------------------------------------------------------------------*/
 943
 944 /* prepare all TDs of a transfer */
 945
 946 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
 947                           unsigned long pipe, void *buffer, int transfer_len,
 948                           struct devrequest *setup, urb_priv_t *urb,
 949                           int interval)
 950 {
 951         int data_len = transfer_len;
 952         void *data;
 953         int cnt = 0;
 954         __u32 info = 0;
 955         unsigned int toggle = 0;
 956
 957         flush_dcache_buffer(buffer, data_len);
 958
 959         /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
 960          * bits for reseting */
 961         if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
 962                 toggle = TD_T_TOGGLE;
 963         } else {
 964                 toggle = TD_T_DATA0;
 965                 usb_settoggle(dev, usb_pipeendpoint(pipe),
 966                                 usb_pipeout(pipe), 1);
 967         }
 968         urb->td_cnt = 0;
 969         if (data_len)
 970                 data = buffer;
 971         else
 972                 data = 0;
 973
 974         switch (usb_pipetype(pipe)) {
 975         case PIPE_BULK:
 976                 info = usb_pipeout(pipe)?
 977                         TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
 978                 while (data_len > 4096) {
 979                         td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
 980                                 data, 4096, dev, cnt, urb);
 981                         data += 4096; data_len -= 4096; cnt++;
 982                 }
 983                 info = usb_pipeout(pipe)?
 984                         TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
 985                 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
 986                         data_len, dev, cnt, urb);
 987                 cnt++;
 988
 989                 if (!ohci->sleeping) {
 990                         /* start bulk list */
 991                         ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
 992                 }
 993                 break;
 994
 995         case PIPE_CONTROL:
 996                 /* Setup phase */
 997                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 998                 flush_dcache_buffer(setup, 8);
 999                 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
1000
1001                 /* Optional Data phase */
1002                 if (data_len > 0) {
1003                         info = usb_pipeout(pipe)?
1004                                 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
1005                                 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
1006                         /* NOTE:  mishandles transfers >8K, some >4K */
1007                         td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1008                 }
1009
1010                 /* Status phase */
1011                 info = (usb_pipeout(pipe) || data_len == 0) ?
1012                         TD_CC | TD_DP_IN | TD_T_DATA1:
1013                         TD_CC | TD_DP_OUT | TD_T_DATA1;
1014                 td_fill(ohci, info, data, 0, dev, cnt++, urb);
1015
1016                 if (!ohci->sleeping) {
1017                         /* start Control list */
1018                         ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
1019                 }
1020                 break;
1021
1022         case PIPE_INTERRUPT:
1023                 info = usb_pipeout(urb->pipe)?
1024                         TD_CC | TD_DP_OUT | toggle:
1025                         TD_CC | TD_R | TD_DP_IN | toggle;
1026                 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1027                 break;
1028         }
1029         if (urb->length != cnt)
1030                 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
1031 }
1032
1033 /*-------------------------------------------------------------------------*
1034  * Done List handling functions
1035  *-------------------------------------------------------------------------*/
1036
1037 /* calculate the transfer length and update the urb */
1038
1039 static void dl_transfer_length(td_t *td)
1040 {
1041         __u32 tdBE, tdCBP;
1042         urb_priv_t *lurb_priv = td->ed->purb;
1043
1044         tdBE   = m32_swap(td->hwBE);
1045         tdCBP  = m32_swap(td->hwCBP);
1046
1047         if (!(usb_pipecontrol(lurb_priv->pipe) &&
1048             ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
1049                 if (tdBE != 0) {
1050                         if (td->hwCBP == 0)
1051                                 lurb_priv->actual_length += tdBE - td->data + 1;
1052                         else
1053                                 lurb_priv->actual_length += tdCBP - td->data;
1054                 }
1055         }
1056 }
1057
1058 /*-------------------------------------------------------------------------*/
1059 static void check_status(td_t *td_list)
1060 {
1061         urb_priv_t *lurb_priv = td_list->ed->purb;
1062         int        urb_len    = lurb_priv->length;
1063         __u32      *phwHeadP  = &td_list->ed->hwHeadP;
1064         int        cc;
1065
1066         cc = TD_CC_GET(m32_swap(td_list->hwINFO));
1067         if (cc) {
1068                 err(" USB-error: %s (%x)", cc_to_string[cc], cc);
1069
1070                 invalidate_dcache_ed(td_list->ed);
1071                 if (*phwHeadP & m32_swap(0x1)) {
1072                         if (lurb_priv &&
1073                             ((td_list->index + 1) < urb_len)) {
1074                                 *phwHeadP =
1075                                         (lurb_priv->td[urb_len - 1]->hwNextTD &\
1076                                                         m32_swap(0xfffffff0)) |
1077                                                    (*phwHeadP & m32_swap(0x2));
1078
1079                                 lurb_priv->td_cnt += urb_len -
1080                                                      td_list->index - 1;
1081                         } else
1082                                 *phwHeadP &= m32_swap(0xfffffff2);
1083                         flush_dcache_ed(td_list->ed);
1084                 }
1085 #ifdef CONFIG_MPC5200
1086                 td_list->hwNextTD = 0;
1087                 flush_dcache_td(td_list);
1088 #endif
1089         }
1090 }
1091
1092 /* replies to the request have to be on a FIFO basis so
1093  * we reverse the reversed done-list */
1094 static td_t *dl_reverse_done_list(ohci_t *ohci)
1095 {
1096         __u32 td_list_hc;
1097         td_t *td_rev = NULL;
1098         td_t *td_list = NULL;
1099
1100         invalidate_dcache_hcca(ohci->hcca);
1101         td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
1102         ohci->hcca->done_head = 0;
1103         flush_dcache_hcca(ohci->hcca);
1104
1105         while (td_list_hc) {
1106                 td_list = (td_t *)td_list_hc;
1107                 invalidate_dcache_td(td_list);
1108                 check_status(td_list);
1109                 td_list->next_dl_td = td_rev;
1110                 td_rev = td_list;
1111                 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
1112         }
1113         return td_list;
1114 }
1115
1116 /*-------------------------------------------------------------------------*/
1117 /*-------------------------------------------------------------------------*/
1118
1119 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
1120 {
1121         if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
1122                 urb->finished = 1;
1123         else
1124                 dbg("finish_urb: strange.., ED state %x, \n", status);
1125 }
1126
1127 /*
1128  * Used to take back a TD from the host controller. This would normally be
1129  * called from within dl_done_list, however it may be called directly if the
1130  * HC no longer sees the TD and it has not appeared on the donelist (after
1131  * two frames).  This bug has been observed on ZF Micro systems.
1132  */
1133 static int takeback_td(ohci_t *ohci, td_t *td_list)
1134 {
1135         ed_t *ed;
1136         int cc;
1137         int stat = 0;
1138         /* urb_t *urb; */
1139         urb_priv_t *lurb_priv;
1140         __u32 tdINFO, edHeadP, edTailP;
1141
1142         invalidate_dcache_td(td_list);
1143         tdINFO = m32_swap(td_list->hwINFO);
1144
1145         ed = td_list->ed;
1146         lurb_priv = ed->purb;
1147
1148         dl_transfer_length(td_list);
1149
1150         lurb_priv->td_cnt++;
1151
1152         /* error code of transfer */
1153         cc = TD_CC_GET(tdINFO);
1154         if (cc) {
1155                 err("USB-error: %s (%x)", cc_to_string[cc], cc);
1156                 stat = cc_to_error[cc];
1157         }
1158
1159         /* see if this done list makes for all TD's of current URB,
1160         * and mark the URB finished if so */
1161         if (lurb_priv->td_cnt == lurb_priv->length)
1162                 finish_urb(ohci, lurb_priv, ed->state);
1163
1164         dbg("dl_done_list: processing TD %x, len %x\n",
1165                 lurb_priv->td_cnt, lurb_priv->length);
1166
1167         if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
1168                 invalidate_dcache_ed(ed);
1169                 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
1170                 edTailP = m32_swap(ed->hwTailP);
1171
1172                 /* unlink eds if they are not busy */
1173                 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1174                         ep_unlink(ohci, ed);
1175         }
1176         return stat;
1177 }
1178
1179 static int dl_done_list(ohci_t *ohci)
1180 {
1181         int stat = 0;
1182         td_t    *td_list = dl_reverse_done_list(ohci);
1183
1184         while (td_list) {
1185                 td_t    *td_next = td_list->next_dl_td;
1186                 stat = takeback_td(ohci, td_list);
1187                 td_list = td_next;
1188         }
1189         return stat;
1190 }
1191
1192 /*-------------------------------------------------------------------------*
1193  * Virtual Root Hub
1194  *-------------------------------------------------------------------------*/
1195
1196 #include <usbroothubdes.h>
1197
1198 /* Hub class-specific descriptor is constructed dynamically */
1199
1200 /*-------------------------------------------------------------------------*/
1201
1202 #define OK(x)                   len = (x); break
1203 #ifdef DEBUG
1204 #define WR_RH_STAT(x)           {info("WR:status %#8x", (x)); ohci_writel((x), \
1205                                                 &ohci->regs->roothub.status); }
1206 #define WR_RH_PORTSTAT(x)       {info("WR:portstatus[%d] %#8x", wIndex-1, \
1207         (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); }
1208 #else
1209 #define WR_RH_STAT(x)           ohci_writel((x), &ohci->regs->roothub.status)
1210 #define WR_RH_PORTSTAT(x)       ohci_writel((x), \
1211                                     &ohci->regs->roothub.portstatus[wIndex-1])
1212 #endif
1213 #define RD_RH_STAT              roothub_status(ohci)
1214 #define RD_RH_PORTSTAT          roothub_portstatus(ohci, wIndex-1)
1215
1216 /* request to virtual root hub */
1217
1218 int rh_check_port_status(ohci_t *controller)
1219 {
1220         __u32 temp, ndp, i;
1221         int res;
1222
1223         res = -1;
1224         temp = roothub_a(controller);
1225         ndp = (temp & RH_A_NDP);
1226 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1227         ndp = (ndp == 2) ? 1:0;
1228 #endif
1229         for (i = 0; i < ndp; i++) {
1230                 temp = roothub_portstatus(controller, i);
1231                 /* check for a device disconnect */
1232                 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1233                         (RH_PS_PESC | RH_PS_CSC)) &&
1234                         ((temp & RH_PS_CCS) == 0)) {
1235                         res = i;
1236                         break;
1237                 }
1238         }
1239         return res;
1240 }
1241
1242 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev,
1243         unsigned long pipe, void *buffer, int transfer_len,
1244         struct devrequest *cmd)
1245 {
1246         void *data = buffer;
1247         int leni = transfer_len;
1248         int len = 0;
1249         int stat = 0;
1250         __u16 bmRType_bReq;
1251         __u16 wValue;
1252         __u16 wIndex;
1253         __u16 wLength;
1254         ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
1255
1256 #ifdef DEBUG
1257 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1258           cmd, "SUB(rh)", usb_pipein(pipe));
1259 #else
1260         mdelay(1);
1261 #endif
1262         if (usb_pipeint(pipe)) {
1263                 info("Root-Hub submit IRQ: NOT implemented");
1264                 return 0;
1265         }
1266
1267         bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
1268         wValue        = le16_to_cpu(cmd->value);
1269         wIndex        = le16_to_cpu(cmd->index);
1270         wLength       = le16_to_cpu(cmd->length);
1271
1272         info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1273                 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1274
1275         switch (bmRType_bReq) {
1276         /* Request Destination:
1277            without flags: Device,
1278            RH_INTERFACE: interface,
1279            RH_ENDPOINT: endpoint,
1280            RH_CLASS means HUB here,
1281            RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
1282         */
1283
1284         case RH_GET_STATUS:
1285                 *(u16 *)databuf = cpu_to_le16(1);
1286                 OK(2);
1287         case RH_GET_STATUS | RH_INTERFACE:
1288                 *(u16 *)databuf = cpu_to_le16(0);
1289                 OK(2);
1290         case RH_GET_STATUS | RH_ENDPOINT:
1291                 *(u16 *)databuf = cpu_to_le16(0);
1292                 OK(2);
1293         case RH_GET_STATUS | RH_CLASS:
1294                 *(u32 *)databuf = cpu_to_le32(
1295                                 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1296                 OK(4);
1297         case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1298                 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
1299                 OK(4);
1300
1301         case RH_CLEAR_FEATURE | RH_ENDPOINT:
1302                 switch (wValue) {
1303                 case (RH_ENDPOINT_STALL):
1304                         OK(0);
1305                 }
1306                 break;
1307
1308         case RH_CLEAR_FEATURE | RH_CLASS:
1309                 switch (wValue) {
1310                 case RH_C_HUB_LOCAL_POWER:
1311                         OK(0);
1312                 case (RH_C_HUB_OVER_CURRENT):
1313                         WR_RH_STAT(RH_HS_OCIC);
1314                         OK(0);
1315                 }
1316                 break;
1317
1318         case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1319                 switch (wValue) {
1320                 case (RH_PORT_ENABLE):        WR_RH_PORTSTAT(RH_PS_CCS);  OK(0);
1321                 case (RH_PORT_SUSPEND):       WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
1322                 case (RH_PORT_POWER):         WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
1323                 case (RH_C_PORT_CONNECTION):  WR_RH_PORTSTAT(RH_PS_CSC);  OK(0);
1324                 case (RH_C_PORT_ENABLE):      WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
1325                 case (RH_C_PORT_SUSPEND):     WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
1326                 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
1327                 case (RH_C_PORT_RESET):       WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
1328                 }
1329                 break;
1330
1331         case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1332                 switch (wValue) {
1333                 case (RH_PORT_SUSPEND):
1334                         WR_RH_PORTSTAT(RH_PS_PSS);  OK(0);
1335                 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1336                         if (RD_RH_PORTSTAT & RH_PS_CCS)
1337                                 WR_RH_PORTSTAT(RH_PS_PRS);
1338                         OK(0);
1339                 case (RH_PORT_POWER):
1340                         WR_RH_PORTSTAT(RH_PS_PPS);
1341                         mdelay(100);
1342                         OK(0);
1343                 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1344                         if (RD_RH_PORTSTAT & RH_PS_CCS)
1345                                 WR_RH_PORTSTAT(RH_PS_PES);
1346                         OK(0);
1347                 }
1348                 break;
1349
1350         case RH_SET_ADDRESS:
1351                 ohci->rh.devnum = wValue;
1352                 OK(0);
1353
1354         case RH_GET_DESCRIPTOR:
1355                 switch ((wValue & 0xff00) >> 8) {
1356                 case (0x01): /* device descriptor */
1357                         len = min_t(unsigned int,
1358                                         leni,
1359                                         min_t(unsigned int,
1360                                         sizeof(root_hub_dev_des),
1361                                         wLength));
1362                         databuf = root_hub_dev_des; OK(len);
1363                 case (0x02): /* configuration descriptor */
1364                         len = min_t(unsigned int,
1365                                         leni,
1366                                         min_t(unsigned int,
1367                                         sizeof(root_hub_config_des),
1368                                         wLength));
1369                         databuf = root_hub_config_des; OK(len);
1370                 case (0x03): /* string descriptors */
1371                         if (wValue == 0x0300) {
1372                                 len = min_t(unsigned int,
1373                                                 leni,
1374                                                 min_t(unsigned int,
1375                                                 sizeof(root_hub_str_index0),
1376                                                 wLength));
1377                                 databuf = root_hub_str_index0;
1378                                 OK(len);
1379                         }
1380                         if (wValue == 0x0301) {
1381                                 len = min_t(unsigned int,
1382                                                 leni,
1383                                                 min_t(unsigned int,
1384                                                 sizeof(root_hub_str_index1),
1385                                                 wLength));
1386                                 databuf = root_hub_str_index1;
1387                                 OK(len);
1388                 }
1389                 default:
1390                         stat = USB_ST_STALLED;
1391                 }
1392                 break;
1393
1394         case RH_GET_DESCRIPTOR | RH_CLASS:
1395         {
1396                 __u32 temp = roothub_a(ohci);
1397
1398                 databuf[0] = 9;         /* min length; */
1399                 databuf[1] = 0x29;
1400                 databuf[2] = temp & RH_A_NDP;
1401 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1402                 databuf[2] = (databuf[2] == 2) ? 1 : 0;
1403 #endif
1404                 databuf[3] = 0;
1405                 if (temp & RH_A_PSM)    /* per-port power switching? */
1406                         databuf[3] |= 0x1;
1407                 if (temp & RH_A_NOCP)   /* no overcurrent reporting? */
1408                         databuf[3] |= 0x10;
1409                 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
1410                         databuf[3] |= 0x8;
1411
1412                 databuf[4] = 0;
1413                 databuf[5] = (temp & RH_A_POTPGT) >> 24;
1414                 databuf[6] = 0;
1415                 temp = roothub_b(ohci);
1416                 databuf[7] = temp & RH_B_DR;
1417                 if (databuf[2] < 7) {
1418                         databuf[8] = 0xff;
1419                 } else {
1420                         databuf[0] += 2;
1421                         databuf[8] = (temp & RH_B_DR) >> 8;
1422                         databuf[10] = databuf[9] = 0xff;
1423                 }
1424
1425                 len = min_t(unsigned int, leni,
1426                             min_t(unsigned int, databuf[0], wLength));
1427                 OK(len);
1428         }
1429
1430         case RH_GET_CONFIGURATION:
1431                 databuf[0] = 0x01;
1432                 OK(1);
1433
1434         case RH_SET_CONFIGURATION:
1435                 WR_RH_STAT(0x10000);
1436                 OK(0);
1437
1438         default:
1439                 dbg("unsupported root hub command");
1440                 stat = USB_ST_STALLED;
1441         }
1442
1443 #ifdef  DEBUG
1444         ohci_dump_roothub(ohci, 1);
1445 #else
1446         mdelay(1);
1447 #endif
1448
1449         len = min_t(int, len, leni);
1450         if (data != databuf)
1451                 memcpy(data, databuf, len);
1452         dev->act_len = len;
1453         dev->status = stat;
1454
1455 #ifdef DEBUG
1456         pkt_print(ohci, NULL, dev, pipe, buffer,
1457                   transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1458 #else
1459         mdelay(1);
1460 #endif
1461
1462         return stat;
1463 }
1464
1465 /*-------------------------------------------------------------------------*/
1466
1467 /* common code for handling submit messages - used for all but root hub */
1468 /* accesses. */
1469 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev,
1470                 unsigned long pipe, void *buffer, int transfer_len,
1471                 struct devrequest *setup, int interval)
1472 {
1473         int stat = 0;
1474         int maxsize = usb_maxpacket(dev, pipe);
1475         int timeout;
1476         urb_priv_t *urb;
1477
1478         urb = malloc(sizeof(urb_priv_t));
1479         memset(urb, 0, sizeof(urb_priv_t));
1480
1481         urb->dev = dev;
1482         urb->pipe = pipe;
1483         urb->transfer_buffer = buffer;
1484         urb->transfer_buffer_length = transfer_len;
1485         urb->interval = interval;
1486
1487 #ifdef DEBUG
1488         urb->actual_length = 0;
1489         pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1490                   setup, "SUB", usb_pipein(pipe));
1491 #else
1492         mdelay(1);
1493 #endif
1494         if (!maxsize) {
1495                 err("submit_common_message: pipesize for pipe %lx is zero",
1496                         pipe);
1497                 return -1;
1498         }
1499
1500         if (sohci_submit_job(ohci, &ohci->ohci_dev, urb, setup) < 0) {
1501                 err("sohci_submit_job failed");
1502                 return -1;
1503         }
1504
1505 #if 0
1506         mdelay(10);
1507         /* ohci_dump_status(ohci); */
1508 #endif
1509
1510         timeout = USB_TIMEOUT_MS(pipe);
1511
1512         /* wait for it to complete */
1513         for (;;) {
1514                 /* check whether the controller is done */
1515                 stat = hc_interrupt(ohci);
1516                 if (stat < 0) {
1517                         stat = USB_ST_CRC_ERR;
1518                         break;
1519                 }
1520
1521                 /* NOTE: since we are not interrupt driven in U-Boot and always
1522                  * handle only one URB at a time, we cannot assume the
1523                  * transaction finished on the first successful return from
1524                  * hc_interrupt().. unless the flag for current URB is set,
1525                  * meaning that all TD's to/from device got actually
1526                  * transferred and processed. If the current URB is not
1527                  * finished we need to re-iterate this loop so as
1528                  * hc_interrupt() gets called again as there needs to be some
1529                  * more TD's to process still */
1530                 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1531                         /* 0xff is returned for an SF-interrupt */
1532                         break;
1533                 }
1534
1535                 if (--timeout) {
1536                         mdelay(1);
1537                         if (!urb->finished)
1538                                 dbg("*");
1539
1540                 } else {
1541                         if (!usb_pipeint(pipe))
1542                                 err("CTL:TIMEOUT ");
1543                         dbg("submit_common_msg: TO status %x\n", stat);
1544                         urb->finished = 1;
1545                         stat = USB_ST_CRC_ERR;
1546                         break;
1547                 }
1548         }
1549
1550         dev->status = stat;
1551         dev->act_len = urb->actual_length;
1552
1553         if (usb_pipein(pipe) && dev->status == 0 && dev->act_len)
1554                 invalidate_dcache_buffer(buffer, dev->act_len);
1555
1556 #ifdef DEBUG
1557         pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1558                   setup, "RET(ctlr)", usb_pipein(pipe));
1559 #else
1560         mdelay(1);
1561 #endif
1562         urb_free_priv(urb);
1563         return 0;
1564 }
1565
1566 /* submit routines called from usb.c */
1567 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1568                 int transfer_len)
1569 {
1570         info("submit_bulk_msg");
1571         return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len,
1572                                  NULL, 0);
1573 }
1574
1575 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1576                 int transfer_len, int interval)
1577 {
1578         info("submit_int_msg");
1579         return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
1580                         interval);
1581 }
1582
1583 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev,
1584         unsigned long pipe, void *buffer, int transfer_len,
1585         struct devrequest *setup)
1586 {
1587         int maxsize = usb_maxpacket(dev, pipe);
1588
1589         info("submit_control_msg");
1590 #ifdef DEBUG
1591         pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1592                   setup, "SUB", usb_pipein(pipe));
1593 #else
1594         mdelay(1);
1595 #endif
1596         if (!maxsize) {
1597                 err("submit_control_message: pipesize for pipe %lx is zero",
1598                         pipe);
1599                 return -1;
1600         }
1601         if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) {
1602                 ohci->rh.dev = dev;
1603                 /* root hub - redirect */
1604                 return ohci_submit_rh_msg(ohci, dev, pipe, buffer,
1605                                           transfer_len, setup);
1606         }
1607
1608         return submit_common_msg(ohci, dev, pipe, buffer, transfer_len,
1609                                  setup, 0);
1610 }
1611
1612 /*-------------------------------------------------------------------------*
1613  * HC functions
1614  *-------------------------------------------------------------------------*/
1615
1616 /* reset the HC and BUS */
1617
1618 static int hc_reset(ohci_t *ohci)
1619 {
1620 #ifdef CONFIG_PCI_EHCI_DEVNO
1621         pci_dev_t pdev;
1622 #endif
1623         int timeout = 30;
1624         int smm_timeout = 50; /* 0,5 sec */
1625
1626         dbg("%s\n", __FUNCTION__);
1627
1628 #ifdef CONFIG_PCI_EHCI_DEVNO
1629         /*
1630          *  Some multi-function controllers (e.g. ISP1562) allow root hub
1631          * resetting via EHCI registers only.
1632          */
1633         pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
1634         if (pdev != -1) {
1635                 u32 base;
1636                 int timeout = 1000;
1637
1638                 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1639                 base += EHCI_USBCMD_OFF;
1640                 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
1641
1642                 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
1643                         if (timeout-- <= 0) {
1644                                 printf("USB RootHub reset timed out!");
1645                                 break;
1646                         }
1647                         udelay(1);
1648                 }
1649         } else
1650                 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
1651 #endif
1652         if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1653                 /* SMM owns the HC, request ownership */
1654                 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
1655                 info("USB HC TakeOver from SMM");
1656                 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1657                         mdelay(10);
1658                         if (--smm_timeout == 0) {
1659                                 err("USB HC TakeOver failed!");
1660                                 return -1;
1661                         }
1662                 }
1663         }
1664
1665         /* Disable HC interrupts */
1666         ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
1667
1668         dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1669                 ohci->slot_name,
1670                 ohci_readl(&ohci->regs->control));
1671
1672         /* Reset USB (needed by some controllers) */
1673         ohci->hc_control = 0;
1674         ohci_writel(ohci->hc_control, &ohci->regs->control);
1675
1676         /* HC Reset requires max 10 us delay */
1677         ohci_writel(OHCI_HCR,  &ohci->regs->cmdstatus);
1678         while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1679                 if (--timeout == 0) {
1680                         err("USB HC reset timed out!");
1681                         return -1;
1682                 }
1683                 udelay(1);
1684         }
1685         return 0;
1686 }
1687
1688 /*-------------------------------------------------------------------------*/
1689
1690 /* Start an OHCI controller, set the BUS operational
1691  * enable interrupts
1692  * connect the virtual root hub */
1693
1694 static int hc_start(ohci_t *ohci)
1695 {
1696         __u32 mask;
1697         unsigned int fminterval;
1698
1699         ohci->disabled = 1;
1700
1701         /* Tell the controller where the control and bulk lists are
1702          * The lists are empty now. */
1703
1704         ohci_writel(0, &ohci->regs->ed_controlhead);
1705         ohci_writel(0, &ohci->regs->ed_bulkhead);
1706
1707         ohci_writel((__u32)ohci->hcca,
1708                     &ohci->regs->hcca); /* reset clears this */
1709
1710         fminterval = 0x2edf;
1711         ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
1712         fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1713         ohci_writel(fminterval, &ohci->regs->fminterval);
1714         ohci_writel(0x628, &ohci->regs->lsthresh);
1715
1716         /* start controller operations */
1717         ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1718         ohci->disabled = 0;
1719         ohci_writel(ohci->hc_control, &ohci->regs->control);
1720
1721         /* disable all interrupts */
1722         mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1723                         OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1724                         OHCI_INTR_OC | OHCI_INTR_MIE);
1725         ohci_writel(mask, &ohci->regs->intrdisable);
1726         /* clear all interrupts */
1727         mask &= ~OHCI_INTR_MIE;
1728         ohci_writel(mask, &ohci->regs->intrstatus);
1729         /* Choose the interrupts we care about now  - but w/o MIE */
1730         mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1731         ohci_writel(mask, &ohci->regs->intrenable);
1732
1733 #ifdef  OHCI_USE_NPS
1734         /* required for AMD-756 and some Mac platforms */
1735         ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
1736                 &ohci->regs->roothub.a);
1737         ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
1738 #endif  /* OHCI_USE_NPS */
1739
1740         /* POTPGT delay is bits 24-31, in 2 ms units. */
1741         mdelay((roothub_a(ohci) >> 23) & 0x1fe);
1742
1743         /* connect the virtual root hub */
1744         ohci->rh.devnum = 0;
1745
1746         return 0;
1747 }
1748
1749 /*-------------------------------------------------------------------------*/
1750
1751 /* an interrupt happens */
1752
1753 static int hc_interrupt(ohci_t *ohci)
1754 {
1755         struct ohci_regs *regs = ohci->regs;
1756         int ints;
1757         int stat = -1;
1758
1759         invalidate_dcache_hcca(ohci->hcca);
1760
1761         if ((ohci->hcca->done_head != 0) &&
1762                                 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
1763                 ints =  OHCI_INTR_WDH;
1764         } else {
1765                 ints = ohci_readl(&regs->intrstatus);
1766                 if (ints == ~(u32)0) {
1767                         ohci->disabled++;
1768                         err("%s device removed!", ohci->slot_name);
1769                         return -1;
1770                 } else {
1771                         ints &= ohci_readl(&regs->intrenable);
1772                         if (ints == 0) {
1773                                 dbg("hc_interrupt: returning..\n");
1774                                 return 0xff;
1775                         }
1776                 }
1777         }
1778
1779         /* dbg("Interrupt: %x frame: %x", ints,
1780                                         le16_to_cpu(ohci->hcca->frame_no)); */
1781
1782         if (ints & OHCI_INTR_RHSC)
1783                 stat = 0xff;
1784
1785         if (ints & OHCI_INTR_UE) {
1786                 ohci->disabled++;
1787                 err("OHCI Unrecoverable Error, controller usb-%s disabled",
1788                         ohci->slot_name);
1789                 /* e.g. due to PCI Master/Target Abort */
1790
1791 #ifdef  DEBUG
1792                 ohci_dump(ohci, 1);
1793 #else
1794                 mdelay(1);
1795 #endif
1796                 /* FIXME: be optimistic, hope that bug won't repeat often. */
1797                 /* Make some non-interrupt context restart the controller. */
1798                 /* Count and limit the retries though; either hardware or */
1799                 /* software errors can go forever... */
1800                 hc_reset(ohci);
1801                 return -1;
1802         }
1803
1804         if (ints & OHCI_INTR_WDH) {
1805                 mdelay(1);
1806                 ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
1807                 (void)ohci_readl(&regs->intrdisable); /* flush */
1808                 stat = dl_done_list(ohci);
1809                 ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
1810                 (void)ohci_readl(&regs->intrdisable); /* flush */
1811         }
1812
1813         if (ints & OHCI_INTR_SO) {
1814                 dbg("USB Schedule overrun\n");
1815                 ohci_writel(OHCI_INTR_SO, &regs->intrenable);
1816                 stat = -1;
1817         }
1818
1819         /* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
1820         if (ints & OHCI_INTR_SF) {
1821                 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
1822                 mdelay(1);
1823                 ohci_writel(OHCI_INTR_SF, &regs->intrdisable);
1824                 if (ohci->ed_rm_list[frame] != NULL)
1825                         ohci_writel(OHCI_INTR_SF, &regs->intrenable);
1826                 stat = 0xff;
1827         }
1828
1829         ohci_writel(ints, &regs->intrstatus);
1830         return stat;
1831 }
1832
1833 /*-------------------------------------------------------------------------*/
1834
1835 /*-------------------------------------------------------------------------*/
1836
1837 /* De-allocate all resources.. */
1838
1839 static void hc_release_ohci(ohci_t *ohci)
1840 {
1841         dbg("USB HC release ohci usb-%s", ohci->slot_name);
1842
1843         if (!ohci->disabled)
1844                 hc_reset(ohci);
1845 }
1846
1847 /*-------------------------------------------------------------------------*/
1848
1849 /*
1850  * low level initalisation routine, called from usb.c
1851  */
1852 static char ohci_inited = 0;
1853
1854 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1855 {
1856 #ifdef CONFIG_PCI_OHCI
1857         pci_dev_t pdev;
1858 #endif
1859
1860 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
1861         /* cpu dependant init */
1862         if (usb_cpu_init())
1863                 return -1;
1864 #endif
1865
1866 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1867         /*  board dependant init */
1868         if (board_usb_init(index, USB_INIT_HOST))
1869                 return -1;
1870 #endif
1871         memset(&gohci, 0, sizeof(ohci_t));
1872
1873         /* align the storage */
1874         if ((__u32)&ghcca[0] & 0xff) {
1875                 err("HCCA not aligned!!");
1876                 return -1;
1877         }
1878         gohci.hcca = &ghcca[0];
1879         info("aligned ghcca %p", gohci.hcca);
1880         memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
1881
1882         gohci.disabled = 1;
1883         gohci.sleeping = 0;
1884         gohci.irq = -1;
1885 #ifdef CONFIG_PCI_OHCI
1886         pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
1887
1888         if (pdev != -1) {
1889                 u16 vid, did;
1890                 u32 base;
1891                 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
1892                 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
1893                 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1894                                 vid, did, (pdev >> 16) & 0xff,
1895                                 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
1896                 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1897                 printf("OHCI regs address 0x%08x\n", base);
1898                 gohci.regs = (struct ohci_regs *)base;
1899         } else
1900                 return -1;
1901 #else
1902         gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
1903 #endif
1904
1905         gohci.flags = 0;
1906         gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
1907
1908         if (hc_reset (&gohci) < 0) {
1909                 hc_release_ohci (&gohci);
1910                 err ("can't reset usb-%s", gohci.slot_name);
1911 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1912                 /* board dependant cleanup */
1913                 board_usb_cleanup(index, USB_INIT_HOST);
1914 #endif
1915
1916 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
1917                 /* cpu dependant cleanup */
1918                 usb_cpu_init_fail();
1919 #endif
1920                 return -1;
1921         }
1922
1923         if (hc_start(&gohci) < 0) {
1924                 err("can't start usb-%s", gohci.slot_name);
1925                 hc_release_ohci(&gohci);
1926                 /* Initialization failed */
1927 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1928                 /* board dependant cleanup */
1929                 usb_board_stop();
1930 #endif
1931
1932 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
1933                 /* cpu dependant cleanup */
1934                 usb_cpu_stop();
1935 #endif
1936                 return -1;
1937         }
1938
1939 #ifdef  DEBUG
1940         ohci_dump(&gohci, 1);
1941 #else
1942         mdelay(1);
1943 #endif
1944         ohci_inited = 1;
1945         return 0;
1946 }
1947
1948 int usb_lowlevel_stop(int index)
1949 {
1950         /* this gets called really early - before the controller has */
1951         /* even been initialized! */
1952         if (!ohci_inited)
1953                 return 0;
1954         /* TODO release any interrupts, etc. */
1955         /* call hc_release_ohci() here ? */
1956         hc_reset(&gohci);
1957
1958 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
1959         /* board dependant cleanup */
1960         if (usb_board_stop())
1961                 return -1;
1962 #endif
1963
1964 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
1965         /* cpu dependant cleanup */
1966         if (usb_cpu_stop())
1967                 return -1;
1968 #endif
1969         /* This driver is no longer initialised. It needs a new low-level
1970          * init (board/cpu) before it can be used again. */
1971         ohci_inited = 0;
1972         return 0;
1973 }
1974
1975 int submit_control_msg(struct usb_device *dev, unsigned long pipe,
1976         void *buffer, int transfer_len, struct devrequest *setup)
1977 {
1978         return _ohci_submit_control_msg(&gohci, dev, pipe, buffer,
1979                                         transfer_len, setup);
1980 }