drivers/video/exynos_fimd.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * Author: InKi Dae <inki.dae@samsung.com>
   5  * Author: Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <config.h>
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <lcd.h>
  27 #include <div64.h>
  28 #include <asm/arch/clk.h>
  29 #include <asm/arch/clock.h>
  30 #include <asm/arch/cpu.h>
  31 #include "exynos_fb.h"
  32
  33 static unsigned long *lcd_base_addr;
  34 static vidinfo_t *pvid;
  35
  36 void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
  37                 u_long palette_size)
  38 {
  39         lcd_base_addr = (unsigned long *)screen_base;
  40 }
  41
  42 static void exynos_fimd_set_dualrgb(unsigned int enabled)
  43 {
  44         struct exynos_fb *fimd_ctrl =
  45                 (struct exynos_fb *)samsung_get_base_fimd();
  46         unsigned int cfg = 0;
  47
  48         if (enabled) {
  49                 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
  50                         EXYNOS_DUALRGB_VDEN_EN_ENABLE;
  51
  52                 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
  53                 cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
  54                         EXYNOS_DUALRGB_MAIN_CNT(0);
  55         }
  56
  57         writel(cfg, &fimd_ctrl->dualrgb);
  58 }
  59
  60 static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
  61 {
  62
  63         struct exynos_fb *fimd_ctrl =
  64                 (struct exynos_fb *)samsung_get_base_fimd();
  65         unsigned int cfg = 0;
  66
  67         if (enabled)
  68                 cfg = EXYNOS_DP_CLK_ENABLE;
  69
  70         writel(cfg, &fimd_ctrl->dp_mie_clkcon);
  71 }
  72
  73 static void exynos_fimd_set_par(unsigned int win_id)
  74 {
  75         unsigned int cfg = 0;
  76         struct exynos_fb *fimd_ctrl =
  77                 (struct exynos_fb *)samsung_get_base_fimd();
  78
  79         /* set window control */
  80         cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
  81                         EXYNOS_WINCON(win_id));
  82
  83         cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
  84                 EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
  85                 EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
  86                 EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
  87
  88         /* DATAPATH is DMA */
  89         cfg |= EXYNOS_WINCON_DATAPATH_DMA;
  90
  91         /* bpp is 32 */
  92         cfg |= EXYNOS_WINCON_WSWP_ENABLE;
  93
  94         /* dma burst is 16 */
  95         cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
  96
  97         /* pixel format is unpacked RGB888 */
  98         cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
  99
 100         writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 101                         EXYNOS_WINCON(win_id));
 102
 103         /* set window position to x=0, y=0*/
 104         cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
 105         writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
 106                         EXYNOS_VIDOSD(win_id));
 107
 108         cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
 109                 EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
 110                 EXYNOS_VIDOSD_RIGHT_X_E(1) |
 111                 EXYNOS_VIDOSD_BOTTOM_Y_E(0);
 112
 113         writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
 114                         EXYNOS_VIDOSD(win_id));
 115
 116         /* set window size for window0*/
 117         cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
 118         writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
 119                         EXYNOS_VIDOSD(win_id));
 120 }
 121
 122 static void exynos_fimd_set_buffer_address(unsigned int win_id)
 123 {
 124         unsigned long start_addr, end_addr;
 125         struct exynos_fb *fimd_ctrl =
 126                 (struct exynos_fb *)samsung_get_base_fimd();
 127
 128         start_addr = (unsigned long)lcd_base_addr;
 129         end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
 130                                 pvid->vl_row);
 131
 132         writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
 133                         EXYNOS_BUFFER_OFFSET(win_id));
 134         writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
 135                         EXYNOS_BUFFER_OFFSET(win_id));
 136 }
 137
 138 static void exynos_fimd_set_clock(vidinfo_t *pvid)
 139 {
 140         unsigned int cfg = 0, div = 0, remainder, remainder_div;
 141         unsigned long pixel_clock;
 142         unsigned long long src_clock;
 143         struct exynos_fb *fimd_ctrl =
 144                 (struct exynos_fb *)samsung_get_base_fimd();
 145
 146         if (pvid->dual_lcd_enabled) {
 147                 pixel_clock = pvid->vl_freq *
 148                                 (pvid->vl_hspw + pvid->vl_hfpd +
 149                                  pvid->vl_hbpd + pvid->vl_col / 2) *
 150                                 (pvid->vl_vspw + pvid->vl_vfpd +
 151                                  pvid->vl_vbpd + pvid->vl_row);
 152         } else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
 153                 pixel_clock = pvid->vl_freq *
 154                                 pvid->vl_width * pvid->vl_height *
 155                                 (pvid->cs_setup + pvid->wr_setup +
 156                                  pvid->wr_act + pvid->wr_hold + 1);
 157         } else {
 158                 pixel_clock = pvid->vl_freq *
 159                                 (pvid->vl_hspw + pvid->vl_hfpd +
 160                                  pvid->vl_hbpd + pvid->vl_col) *
 161                                 (pvid->vl_vspw + pvid->vl_vfpd +
 162                                  pvid->vl_vbpd + pvid->vl_row);
 163         }
 164
 165         cfg = readl(&fimd_ctrl->vidcon0);
 166         cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
 167                 EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
 168                 EXYNOS_VIDCON0_CLKDIR_MASK);
 169         cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
 170                 EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
 171
 172         src_clock = (unsigned long long) get_lcd_clk();
 173
 174         /* get quotient and remainder. */
 175         remainder = do_div(src_clock, pixel_clock);
 176         div = src_clock;
 177
 178         remainder *= 10;
 179         remainder_div = remainder / pixel_clock;
 180
 181         /* round about one places of decimals. */
 182         if (remainder_div >= 5)
 183                 div++;
 184
 185         /* in case of dual lcd mode. */
 186         if (pvid->dual_lcd_enabled)
 187                 div--;
 188
 189         cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
 190         writel(cfg, &fimd_ctrl->vidcon0);
 191 }
 192
 193 void exynos_set_trigger(void)
 194 {
 195         unsigned int cfg = 0;
 196         struct exynos_fb *fimd_ctrl =
 197                 (struct exynos_fb *)samsung_get_base_fimd();
 198
 199         cfg = readl(&fimd_ctrl->trigcon);
 200
 201         cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
 202
 203         writel(cfg, &fimd_ctrl->trigcon);
 204 }
 205
 206 int exynos_is_i80_frame_done(void)
 207 {
 208         unsigned int cfg = 0;
 209         int status;
 210         struct exynos_fb *fimd_ctrl =
 211                 (struct exynos_fb *)samsung_get_base_fimd();
 212
 213         cfg = readl(&fimd_ctrl->trigcon);
 214
 215         /* frame done func is valid only when TRIMODE[0] is set to 1. */
 216         status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
 217                         EXYNOS_I80STATUS_TRIG_DONE;
 218
 219         return status;
 220 }
 221
 222 static void exynos_fimd_lcd_on(void)
 223 {
 224         unsigned int cfg = 0;
 225         struct exynos_fb *fimd_ctrl =
 226                 (struct exynos_fb *)samsung_get_base_fimd();
 227
 228         /* display on */
 229         cfg = readl(&fimd_ctrl->vidcon0);
 230         cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
 231         writel(cfg, &fimd_ctrl->vidcon0);
 232 }
 233
 234 static void exynos_fimd_window_on(unsigned int win_id)
 235 {
 236         unsigned int cfg = 0;
 237         struct exynos_fb *fimd_ctrl =
 238                 (struct exynos_fb *)samsung_get_base_fimd();
 239
 240         /* enable window */
 241         cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
 242                         EXYNOS_WINCON(win_id));
 243         cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
 244         writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 245                         EXYNOS_WINCON(win_id));
 246
 247         cfg = readl(&fimd_ctrl->winshmap);
 248         cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
 249         writel(cfg, &fimd_ctrl->winshmap);
 250 }
 251
 252 void exynos_fimd_lcd_off(void)
 253 {
 254         unsigned int cfg = 0;
 255         struct exynos_fb *fimd_ctrl =
 256                 (struct exynos_fb *)samsung_get_base_fimd();
 257
 258         cfg = readl(&fimd_ctrl->vidcon0);
 259         cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
 260         writel(cfg, &fimd_ctrl->vidcon0);
 261 }
 262
 263 void exynos_fimd_window_off(unsigned int win_id)
 264 {
 265         unsigned int cfg = 0;
 266         struct exynos_fb *fimd_ctrl =
 267                 (struct exynos_fb *)samsung_get_base_fimd();
 268
 269         cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
 270                         EXYNOS_WINCON(win_id));
 271         cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
 272         writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 273                         EXYNOS_WINCON(win_id));
 274
 275         cfg = readl(&fimd_ctrl->winshmap);
 276         cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
 277         writel(cfg, &fimd_ctrl->winshmap);
 278 }
 279
 280
 281 void exynos_fimd_lcd_init(vidinfo_t *vid)
 282 {
 283         unsigned int cfg = 0, rgb_mode;
 284         unsigned int offset;
 285         struct exynos_fb *fimd_ctrl =
 286                 (struct exynos_fb *)samsung_get_base_fimd();
 287
 288         offset = exynos_fimd_get_base_offset();
 289
 290         /* store panel info to global variable */
 291         pvid = vid;
 292
 293         rgb_mode = vid->rgb_mode;
 294
 295         if (vid->interface_mode == FIMD_RGB_INTERFACE) {
 296                 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
 297                 writel(cfg, &fimd_ctrl->vidcon0);
 298
 299                 cfg = readl(&fimd_ctrl->vidcon2);
 300                 cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
 301                         EXYNOS_VIDCON2_TVFORMATSEL_MASK |
 302                         EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
 303                 cfg |= EXYNOS_VIDCON2_WB_DISABLE;
 304                 writel(cfg, &fimd_ctrl->vidcon2);
 305
 306                 /* set polarity */
 307                 cfg = 0;
 308                 if (!pvid->vl_clkp)
 309                         cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
 310                 if (!pvid->vl_hsp)
 311                         cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
 312                 if (!pvid->vl_vsp)
 313                         cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
 314                 if (!pvid->vl_dp)
 315                         cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
 316
 317                 writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
 318
 319                 /* set timing */
 320                 cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
 321                 cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
 322                 cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
 323                 writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
 324
 325                 cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
 326                 cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
 327                 cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
 328
 329                 writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
 330
 331                 /* set lcd size */
 332                 cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
 333                         EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
 334                         EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
 335                         EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
 336
 337                 writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
 338         }
 339
 340         /* set display mode */
 341         cfg = readl(&fimd_ctrl->vidcon0);
 342         cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
 343         cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
 344         writel(cfg, &fimd_ctrl->vidcon0);
 345
 346         /* set par */
 347         exynos_fimd_set_par(pvid->win_id);
 348
 349         /* set memory address */
 350         exynos_fimd_set_buffer_address(pvid->win_id);
 351
 352         /* set buffer size */
 353         cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
 354                 EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
 355                 EXYNOS_VIDADDR_OFFSIZE(0) |
 356                 EXYNOS_VIDADDR_OFFSIZE_E(0);
 357
 358         writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
 359                                         EXYNOS_BUFFER_SIZE(pvid->win_id));
 360
 361         /* set clock */
 362         exynos_fimd_set_clock(pvid);
 363
 364         /* set rgb mode to dual lcd. */
 365         exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
 366
 367         /* display on */
 368         exynos_fimd_lcd_on();
 369
 370         /* window on */
 371         exynos_fimd_window_on(pvid->win_id);
 372
 373         exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
 374 }
 375
 376 unsigned long exynos_fimd_calc_fbsize(void)
 377 {
 378         return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
 379 }