5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
9 * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <linux/types.h>
35 #include <asm/errno.h>
37 #include <asm/arch/imx-regs.h>
50 struct dp_csc_param_t {
57 /* DC display ID assignments */
58 #define DC_DISP_ID_SYNC(di) (di)
59 #define DC_DISP_ID_SERIAL 2
60 #define DC_DISP_ID_ASYNC 3
62 static int dmfc_type_setup;
63 static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
64 static int g_di1_tvout;
67 extern struct clk *g_ipu_clk;
68 extern struct clk *g_di_clk[2];
69 extern struct clk *g_pixel_clk[2];
71 extern unsigned char g_ipu_clk_enabled;
72 extern unsigned char g_dc_di_assignment[];
75 void ipu_dmfc_init(int dmfc_type, int first)
77 u32 dmfc_wr_chan, dmfc_dp_chan;
80 if (dmfc_type_setup > dmfc_type)
81 dmfc_type = dmfc_type_setup;
83 dmfc_type_setup = dmfc_type;
85 /* disable DMFC-IC channel*/
86 __raw_writel(0x2, DMFC_IC_CTRL);
87 } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
88 printf("DMFC high resolution has set, will not change\n");
91 dmfc_type_setup = dmfc_type;
93 if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
97 * 1C, 2C and 6B, 6F unused;
99 debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
100 dmfc_wr_chan = 0x00000088;
101 dmfc_dp_chan = 0x00009694;
102 dmfc_size_28 = 256 * 4;
105 dmfc_size_27 = 128 * 4;
106 dmfc_size_23 = 128 * 4;
107 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
111 * 1C, 2C and 6B, 6F unused;
113 debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
114 dmfc_wr_chan = 0x00000090;
115 dmfc_dp_chan = 0x0000968a;
116 dmfc_size_28 = 128 * 4;
119 dmfc_size_27 = 128 * 4;
120 dmfc_size_23 = 256 * 4;
121 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
122 /* 5B - segement 0~3;
124 * 1, 1C, 2C and 6B, 6F unused;
126 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
127 dmfc_wr_chan = 0x00000000;
128 dmfc_dp_chan = 0x00008c88;
132 dmfc_size_27 = 256 * 4;
133 dmfc_size_23 = 256 * 4;
136 * 5B - segement 4, 5;
137 * 5F - segement 6, 7;
138 * 1C, 2C and 6B, 6F unused;
140 debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
141 dmfc_wr_chan = 0x00000090;
142 dmfc_dp_chan = 0x00009694;
143 dmfc_size_28 = 128 * 4;
146 dmfc_size_27 = 128 * 4;
147 dmfc_size_23 = 128 * 4;
149 __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
150 __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
151 __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
152 /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
153 __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
156 void ipu_dmfc_set_wait4eot(int dma_chan, int width)
158 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
160 if (width >= HIGH_RESOLUTION_WIDTH) {
162 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
163 else if (dma_chan == 28)
164 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
167 if (dma_chan == 23) { /*5B*/
168 if (dmfc_size_23 / width > 3)
169 dmfc_gen1 |= 1UL << 20;
171 dmfc_gen1 &= ~(1UL << 20);
172 } else if (dma_chan == 24) { /*6B*/
173 if (dmfc_size_24 / width > 1)
174 dmfc_gen1 |= 1UL << 22;
176 dmfc_gen1 &= ~(1UL << 22);
177 } else if (dma_chan == 27) { /*5F*/
178 if (dmfc_size_27 / width > 2)
179 dmfc_gen1 |= 1UL << 21;
181 dmfc_gen1 &= ~(1UL << 21);
182 } else if (dma_chan == 28) { /*1*/
183 if (dmfc_size_28 / width > 2)
184 dmfc_gen1 |= 1UL << 16;
186 dmfc_gen1 &= ~(1UL << 16);
187 } else if (dma_chan == 29) { /*6F*/
188 if (dmfc_size_29 / width > 1)
189 dmfc_gen1 |= 1UL << 23;
191 dmfc_gen1 &= ~(1UL << 23);
194 __raw_writel(dmfc_gen1, DMFC_GENERAL1);
197 static void ipu_di_data_wave_config(int di,
199 int access_size, int component_size)
202 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
203 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
204 __raw_writel(reg, DI_DW_GEN(di, wave_gen));
207 static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
212 reg = __raw_readl(DI_DW_GEN(di, wave_gen));
213 reg &= ~(0x3 << (di_pin * 2));
214 reg |= set << (di_pin * 2);
215 __raw_writel(reg, DI_DW_GEN(di, wave_gen));
217 __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
220 static void ipu_di_sync_config(int di, int wave_gen,
221 int run_count, int run_src,
222 int offset_count, int offset_src,
223 int repeat_count, int cnt_clr_src,
224 int cnt_polarity_gen_en,
225 int cnt_polarity_clr_src,
226 int cnt_polarity_trigger_src,
227 int cnt_up, int cnt_down)
231 if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
232 (repeat_count >= 0x1000) ||
233 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
234 printf("DI%d counters out of range.\n", di);
238 reg = (run_count << 19) | (++run_src << 16) |
239 (offset_count << 3) | ++offset_src;
240 __raw_writel(reg, DI_SW_GEN0(di, wave_gen));
241 reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
242 (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
243 reg |= (cnt_down << 16) | cnt_up;
244 if (repeat_count == 0) {
245 /* Enable auto reload */
248 __raw_writel(reg, DI_SW_GEN1(di, wave_gen));
249 reg = __raw_readl(DI_STP_REP(di, wave_gen));
250 reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
251 reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
252 __raw_writel(reg, DI_STP_REP(di, wave_gen));
255 static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
257 int ptr = map * 3 + byte_num;
260 reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
261 reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
262 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
263 __raw_writel(reg, DC_MAP_CONF_VAL(ptr));
265 reg = __raw_readl(DC_MAP_CONF_PTR(map));
266 reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
267 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
268 __raw_writel(reg, DC_MAP_CONF_PTR(map));
271 static void ipu_dc_map_clear(int map)
273 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
274 __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
275 DC_MAP_CONF_PTR(map));
278 static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
279 int wave, int glue, int sync)
286 reg |= (++wave << 11);
287 reg |= (++map << 15);
288 reg |= (operand << 20) & 0xFFF00000;
289 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
291 reg = (operand >> 12);
294 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
297 static void ipu_dc_link_event(int chan, int event, int addr, int priority)
301 reg = __raw_readl(DC_RL_CH(chan, event));
302 reg &= ~(0xFFFF << (16 * (event & 0x1)));
303 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
304 __raw_writel(reg, DC_RL_CH(chan, event));
307 /* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
308 * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
309 * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;
311 static const int rgb2ycbcr_coeff[5][3] = {
313 {0x3D5, 0x3AB, 0x80},
314 {0x80, 0x395, 0x3EB},
315 {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
316 {0x2, 0x2, 0x2}, /* S0, S1, S2 */
319 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
320 * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
321 * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
323 static const int ycbcr2rgb_coeff[5][3] = {
324 {0x095, 0x000, 0x0CC},
325 {0x095, 0x3CE, 0x398},
326 {0x095, 0x0FF, 0x000},
327 {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
328 {0x1, 0x1, 0x1}, /*S0,S1,S2 */
331 #define mask_a(a) ((u32)(a) & 0x3FF)
332 #define mask_b(b) ((u32)(b) & 0x3FFF)
334 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
335 static int rgb_to_yuv(int n, int red, int green, int blue)
338 c = red * rgb2ycbcr_coeff[n][0];
339 c += green * rgb2ycbcr_coeff[n][1];
340 c += blue * rgb2ycbcr_coeff[n][2];
342 c += rgb2ycbcr_coeff[3][n] * 4;
353 * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
354 * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
356 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
358 {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
361 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
362 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
366 {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
367 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
369 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
373 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
379 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
386 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
387 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
394 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
395 static int color_key_4rgb = 1;
397 void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
398 unsigned char srm_mode_update)
401 const int (*coeff)[5][3];
403 if (dp_csc_param.mode >= 0) {
404 reg = __raw_readl(DP_COM_CONF());
405 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
406 reg |= dp_csc_param.mode;
407 __raw_writel(reg, DP_COM_CONF());
410 coeff = dp_csc_param.coeff;
413 __raw_writel(mask_a((*coeff)[0][0]) |
414 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
415 __raw_writel(mask_a((*coeff)[0][2]) |
416 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
417 __raw_writel(mask_a((*coeff)[1][1]) |
418 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
419 __raw_writel(mask_a((*coeff)[2][0]) |
420 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
421 __raw_writel(mask_a((*coeff)[2][2]) |
422 (mask_b((*coeff)[3][0]) << 16) |
423 ((*coeff)[4][0] << 30), DP_CSC_0());
424 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
425 (mask_b((*coeff)[3][2]) << 16) |
426 ((*coeff)[4][2] << 30), DP_CSC_1());
429 if (srm_mode_update) {
430 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
431 __raw_writel(reg, IPU_SRM_PRI2);
435 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
436 uint32_t out_pixel_fmt)
443 if (channel == MEM_FG_SYNC) {
446 } else if (channel == MEM_BG_SYNC) {
449 } else if (channel == MEM_BG_ASYNC0) {
456 in_fmt = format_to_colorspace(in_pixel_fmt);
457 out_fmt = format_to_colorspace(out_pixel_fmt);
462 fg_csc_type = RGB2RGB;
464 fg_csc_type = RGB2YUV;
467 fg_csc_type = YUV2RGB;
469 fg_csc_type = YUV2YUV;
474 bg_csc_type = RGB2RGB;
476 bg_csc_type = RGB2YUV;
479 bg_csc_type = YUV2RGB;
481 bg_csc_type = YUV2YUV;
485 /* Transform color key from rgb to yuv if CSC is enabled */
486 reg = __raw_readl(DP_COM_CONF());
487 if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
488 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
489 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
490 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
491 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
492 int red, green, blue;
494 uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
497 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
500 red = (color_key >> 16) & 0xFF;
501 green = (color_key >> 8) & 0xFF;
502 blue = color_key & 0xFF;
504 y = rgb_to_yuv(0, red, green, blue);
505 u = rgb_to_yuv(1, red, green, blue);
506 v = rgb_to_yuv(2, red, green, blue);
507 color_key = (y << 16) | (u << 8) | v;
509 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
510 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
513 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
517 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
522 void ipu_dp_uninit(ipu_channel_t channel)
527 if (channel == MEM_FG_SYNC) {
530 } else if (channel == MEM_BG_SYNC) {
533 } else if (channel == MEM_BG_ASYNC0) {
541 fg_csc_type = CSC_NONE;
543 bg_csc_type = CSC_NONE;
545 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
548 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
552 if ((dc_chan == 1) || (dc_chan == 5)) {
554 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
555 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
556 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
559 ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
560 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
561 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
564 ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
565 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
566 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
570 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
571 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
572 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
573 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
574 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
575 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
578 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
581 reg |= DC_WR_CH_CONF_FIELD_MODE;
582 } else if ((dc_chan == 8) || (dc_chan == 9)) {
584 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
585 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
588 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
590 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
592 __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
594 __raw_writel(0x00000084, DC_GEN);
597 void ipu_dc_uninit(int dc_chan)
599 if ((dc_chan == 1) || (dc_chan == 5)) {
600 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
601 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
602 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
603 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
604 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
605 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
606 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
607 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
608 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
609 } else if ((dc_chan == 8) || (dc_chan == 9)) {
610 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
611 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
612 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
613 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
614 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
615 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
616 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
617 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
618 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
619 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
620 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
621 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
625 int ipu_chan_is_interlaced(ipu_channel_t channel)
627 if (channel == MEM_DC_SYNC)
628 return !!(__raw_readl(DC_WR_CH_CONF_1) &
629 DC_WR_CH_CONF_FIELD_MODE);
630 else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
631 return !!(__raw_readl(DC_WR_CH_CONF_5) &
632 DC_WR_CH_CONF_FIELD_MODE);
636 void ipu_dp_dc_enable(ipu_channel_t channel)
642 if (channel == MEM_FG_SYNC)
644 if (channel == MEM_DC_SYNC)
646 else if (channel == MEM_BG_SYNC)
651 if (channel == MEM_FG_SYNC) {
652 /* Enable FG channel */
653 reg = __raw_readl(DP_COM_CONF());
654 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
656 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
657 __raw_writel(reg, IPU_SRM_PRI2);
661 di = g_dc_di_assignment[dc_chan];
663 /* Make sure other DC sync channel is not assigned same DI */
664 reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
665 if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
666 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
667 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
668 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
671 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
672 reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
673 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
675 clk_enable(g_pixel_clk[di]);
678 static unsigned char dc_swap;
680 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
684 uint32_t dc_chan = 0;
689 if (channel == MEM_DC_SYNC) {
691 } else if (channel == MEM_BG_SYNC) {
693 } else if (channel == MEM_FG_SYNC) {
694 /* Disable FG channel */
697 reg = __raw_readl(DP_COM_CONF());
698 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
699 if (csc == DP_COM_CONF_CSC_DEF_FG)
700 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
702 reg &= ~DP_COM_CONF_FG_EN;
703 __raw_writel(reg, DP_COM_CONF());
705 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
706 __raw_writel(reg, IPU_SRM_PRI2);
711 * Wait for DC triple buffer to empty,
712 * this check is useful for tv overlay.
714 if (g_dc_di_assignment[dc_chan] == 0)
715 while ((__raw_readl(DC_STAT) & 0x00000002)
722 else if (g_dc_di_assignment[dc_chan] == 1)
723 while ((__raw_readl(DC_STAT) & 0x00000020)
736 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
737 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
738 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
739 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
740 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
741 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
745 /* Wait for DC triple buffer to empty */
746 if (g_dc_di_assignment[dc_chan] == 0)
747 while ((__raw_readl(DC_STAT) & 0x00000002)
754 else if (g_dc_di_assignment[dc_chan] == 1)
755 while ((__raw_readl(DC_STAT) & 0x00000020)
763 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
764 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
765 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
767 reg = __raw_readl(IPU_DISP_GEN);
768 if (g_dc_di_assignment[dc_chan])
769 reg &= ~DI1_COUNTER_RELEASE;
771 reg &= ~DI0_COUNTER_RELEASE;
772 __raw_writel(reg, IPU_DISP_GEN);
774 /* Clock is already off because it must be done quickly, but
775 we need to fix the ref count */
776 clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
780 void ipu_init_dc_mappings(void)
782 /* IPU_PIX_FMT_RGB24 */
784 ipu_dc_map_config(0, 0, 7, 0xFF);
785 ipu_dc_map_config(0, 1, 15, 0xFF);
786 ipu_dc_map_config(0, 2, 23, 0xFF);
788 /* IPU_PIX_FMT_RGB666 */
790 ipu_dc_map_config(1, 0, 5, 0xFC);
791 ipu_dc_map_config(1, 1, 11, 0xFC);
792 ipu_dc_map_config(1, 2, 17, 0xFC);
794 /* IPU_PIX_FMT_YUV444 */
796 ipu_dc_map_config(2, 0, 15, 0xFF);
797 ipu_dc_map_config(2, 1, 23, 0xFF);
798 ipu_dc_map_config(2, 2, 7, 0xFF);
800 /* IPU_PIX_FMT_RGB565 */
802 ipu_dc_map_config(3, 0, 4, 0xF8);
803 ipu_dc_map_config(3, 1, 10, 0xFC);
804 ipu_dc_map_config(3, 2, 15, 0xF8);
806 /* IPU_PIX_FMT_LVDS666 */
808 ipu_dc_map_config(4, 0, 5, 0xFC);
809 ipu_dc_map_config(4, 1, 11, 0xFC);
810 ipu_dc_map_config(4, 2, 17, 0xFC);
813 int ipu_pixfmt_to_map(uint32_t fmt)
816 case IPU_PIX_FMT_GENERIC:
817 case IPU_PIX_FMT_RGB24:
818 case IPU_PIX_FMT_LVDS888:
820 case IPU_PIX_FMT_RGB666:
822 case IPU_PIX_FMT_YUV444:
824 case IPU_PIX_FMT_RGB565:
826 case IPU_PIX_FMT_LVDS666:
834 * This function is called to adapt synchronous LCD panel to IPU restriction.
836 void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
837 uint16_t width, uint16_t height,
838 uint16_t h_start_width,
839 uint16_t h_end_width,
840 uint16_t v_start_width,
841 uint16_t *v_end_width)
843 if (*v_end_width < 2) {
844 uint16_t total_width = width + h_start_width + h_end_width;
845 uint16_t total_height_old = height + v_start_width +
847 uint16_t total_height_new = height + v_start_width + 2;
849 *pixel_clk = (*pixel_clk) * total_width * total_height_new /
850 (total_width * total_height_old);
851 printf("WARNING: adapt panel end blank lines\n");
856 * This function is called to initialize a synchronous LCD panel.
858 * @param disp The DI the panel is attached to.
860 * @param pixel_clk Desired pixel clock frequency in Hz.
862 * @param pixel_fmt Input parameter for pixel format of buffer.
863 * Pixel format is a FOURCC ASCII code.
865 * @param width The width of panel in pixels.
867 * @param height The height of panel in pixels.
869 * @param hStartWidth The number of pixel clocks between the HSYNC
870 * signal pulse and the start of valid data.
872 * @param hSyncWidth The width of the HSYNC signal in units of pixel
875 * @param hEndWidth The number of pixel clocks between the end of
876 * valid data and the HSYNC signal for next line.
878 * @param vStartWidth The number of lines between the VSYNC
879 * signal pulse and the start of valid data.
881 * @param vSyncWidth The width of the VSYNC signal in units of lines
883 * @param vEndWidth The number of lines between the end of valid
884 * data and the VSYNC signal for next frame.
886 * @param sig Bitfield of signal polarities for LCD interface.
888 * @return This function returns 0 on success or negative error code on
892 int ipu_init_sync_panel(int disp, uint32_t pixel_clk,
893 uint16_t width, uint16_t height,
895 uint16_t h_start_width, uint16_t h_sync_width,
896 uint16_t h_end_width, uint16_t v_start_width,
897 uint16_t v_sync_width, uint16_t v_end_width,
898 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
901 uint32_t di_gen, vsync_cnt;
902 uint32_t div, rounded_pixel_clk;
903 uint32_t h_total, v_total;
905 struct clk *di_parent;
907 debug("panel size = %d x %d\n", width, height);
909 if ((v_sync_width == 0) || (h_sync_width == 0))
912 adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
913 h_start_width, h_end_width,
914 v_start_width, &v_end_width);
915 h_total = width + h_sync_width + h_start_width + h_end_width;
916 v_total = height + v_sync_width + v_start_width + v_end_width;
919 debug("pixel clk = %d\n", pixel_clk);
922 if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */
924 * Set the PLL to be an even multiple
925 * of the pixel clock.
927 if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
928 (clk_get_usecount(g_pixel_clk[1]) == 0)) {
929 di_parent = clk_get_parent(g_di_clk[disp]);
931 clk_round_rate(g_pixel_clk[disp],
933 if (di_parent != NULL) {
934 div = clk_get_rate(di_parent) /
938 if (clk_get_rate(di_parent) != div *
940 clk_set_rate(di_parent,
941 div * rounded_pixel_clk);
943 clk_set_rate(g_di_clk[disp],
944 2 * rounded_pixel_clk);
949 clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
951 if (clk_get_usecount(g_pixel_clk[disp]) != 0)
952 clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
954 rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
955 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
957 /* Get integer portion of divider */
958 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
961 /* Enable for a divide by 2 clock change. */
962 reg = __raw_readl(IPU_PM);
965 reg &= ~(0x7f << 23);
967 __raw_writel(reg, IPU_PM);
971 if (pixel_fmt != IPU_PIX_FMT_LVDS666 &&
972 pixel_fmt != IPU_PIX_FMT_LVDS888) {
973 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
975 /* Get integer portion of divider */
976 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
978 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
980 clk_set_rate(g_pixel_clk[disp], clk_get_rate(g_ipu_clk));
982 ipu_di_data_wave_config(disp, SYNC_WAVE, 0, 0);
984 di_gen |= DI_GEN_DI_CLK_EXT;
986 ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
988 map = ipu_pixfmt_to_map(pixel_fmt);
990 debug("IPU_DISP: No MAP\n");
994 if (sig.interlaced) {
995 /* Setup internal HSYNC waveform */
999 h_total / 2 - 1,/* run count */
1000 DI_SYNC_CLK, /* run_resolution */
1002 DI_SYNC_NONE, /* offset resolution */
1003 0, /* repeat count */
1004 DI_SYNC_NONE, /* CNT_CLR_SEL */
1005 0, /* CNT_POLARITY_GEN_EN */
1006 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1007 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1012 /* Field 1 VSYNC waveform */
1016 h_total - 1, /* run count */
1017 DI_SYNC_CLK, /* run_resolution */
1019 DI_SYNC_NONE, /* offset resolution */
1020 0, /* repeat count */
1021 DI_SYNC_NONE, /* CNT_CLR_SEL */
1022 0, /* CNT_POLARITY_GEN_EN */
1023 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1024 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1029 /* Setup internal HSYNC waveform */
1033 v_total * 2 - 1,/* run count */
1034 DI_SYNC_INT_HSYNC, /* run_resolution */
1036 DI_SYNC_INT_HSYNC, /* offset resolution */
1037 0, /* repeat count */
1038 DI_SYNC_NONE, /* CNT_CLR_SEL */
1039 0, /* CNT_POLARITY_GEN_EN */
1040 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1041 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1046 /* Active Field ? */
1050 v_total / 2 - 1,/* run count */
1051 DI_SYNC_HSYNC, /* run_resolution */
1052 v_start_width, /* offset */
1053 DI_SYNC_HSYNC, /* offset resolution */
1054 2, /* repeat count */
1055 DI_SYNC_VSYNC, /* CNT_CLR_SEL */
1056 0, /* CNT_POLARITY_GEN_EN */
1057 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1058 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1068 DI_SYNC_HSYNC, /* run_resolution */
1070 DI_SYNC_NONE, /* offset resolution */
1071 height / 2, /* repeat count */
1072 4, /* CNT_CLR_SEL */
1073 0, /* CNT_POLARITY_GEN_EN */
1074 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1075 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1080 /* Field 0 VSYNC waveform */
1084 v_total - 1, /* run count */
1085 DI_SYNC_HSYNC, /* run_resolution */
1087 DI_SYNC_NONE, /* offset resolution */
1088 0, /* repeat count */
1089 DI_SYNC_NONE, /* CNT_CLR_SEL */
1090 0, /* CNT_POLARITY_GEN_EN */
1091 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1092 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1097 /* DC VSYNC waveform */
1102 v_total / 2 - 1,/* run count */
1103 DI_SYNC_HSYNC, /* run_resolution */
1105 DI_SYNC_HSYNC, /* offset resolution */
1106 2, /* repeat count */
1107 DI_SYNC_VSYNC, /* CNT_CLR_SEL */
1108 0, /* CNT_POLARITY_GEN_EN */
1109 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1110 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1115 /* active pixel waveform */
1120 DI_SYNC_CLK, /* run_resolution */
1121 h_start_width, /* offset */
1122 DI_SYNC_CLK, /* offset resolution */
1123 width, /* repeat count */
1124 5, /* CNT_CLR_SEL */
1125 0, /* CNT_POLARITY_GEN_EN */
1126 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1127 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1135 v_total - 1, /* run count */
1136 DI_SYNC_INT_HSYNC,/* run_resolution */
1137 v_total / 2, /* offset */
1138 DI_SYNC_INT_HSYNC,/* offset resolution */
1139 0, /* repeat count */
1140 DI_SYNC_HSYNC, /* CNT_CLR_SEL */
1141 0, /* CNT_POLARITY_GEN_EN */
1142 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1143 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1148 /* set gentime select and tag sel */
1149 reg = __raw_readl(DI_SW_GEN1(disp, 9));
1151 reg |= ((3 - 1) << 29) | 0x00008000;
1152 __raw_writel(reg, DI_SW_GEN1(disp, 9));
1154 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
1157 di_gen |= 0x10000000;
1158 di_gen |= DI_GEN_POLARITY_5;
1159 di_gen |= DI_GEN_POLARITY_8;
1161 /* Setup internal HSYNC waveform */
1162 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
1163 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1165 DI_SYNC_NONE, 0, 0);
1167 /* Setup external (delayed) HSYNC waveform */
1168 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
1169 DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1170 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1171 DI_SYNC_CLK, 0, h_sync_width * 2);
1172 /* Setup VSYNC waveform */
1173 vsync_cnt = DI_SYNC_VSYNC;
1174 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
1175 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1176 DI_SYNC_NONE, 1, DI_SYNC_NONE,
1177 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1178 __raw_writel(v_total - 1, DI_SCR_CONF(disp));
1180 /* Setup active data waveform to sync with DC */
1181 ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
1182 v_sync_width + v_start_width, DI_SYNC_HSYNC,
1184 DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1185 DI_SYNC_NONE, 0, 0);
1186 ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
1187 h_sync_width + h_start_width, DI_SYNC_CLK,
1188 width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1191 /* reset all unused counters */
1192 __raw_writel(0, DI_SW_GEN0(disp, 6));
1193 __raw_writel(0, DI_SW_GEN1(disp, 6));
1194 __raw_writel(0, DI_SW_GEN0(disp, 7));
1195 __raw_writel(0, DI_SW_GEN1(disp, 7));
1196 __raw_writel(0, DI_SW_GEN0(disp, 8));
1197 __raw_writel(0, DI_SW_GEN1(disp, 8));
1198 __raw_writel(0, DI_SW_GEN0(disp, 9));
1199 __raw_writel(0, DI_SW_GEN1(disp, 9));
1201 reg = __raw_readl(DI_STP_REP(disp, 6));
1203 __raw_writel(reg, DI_STP_REP(disp, 6));
1204 __raw_writel(0, DI_STP_REP(disp, 7));
1205 __raw_writel(0, DI_STP_REP(disp, 9));
1207 h_total = ((width + h_start_width + h_sync_width) / 2) - 2;
1208 ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total,
1209 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE,
1210 DI_SYNC_NONE, 0, 0);
1212 /* Init template microcode */
1214 ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1215 ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1216 ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1218 ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1219 ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1220 ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1224 di_gen |= DI_GEN_POLARITY_2;
1226 di_gen |= DI_GEN_POLARITY_3;
1229 di_gen |= DI_GEN_POL_CLK;
1231 /* Set the clock to stop at counter 6. */
1232 di_gen |= 0x6000000;
1235 __raw_writel(di_gen, DI_GENERAL(disp));
1238 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1239 0x00000002, DI_SYNC_AS_GEN(disp));
1241 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET),
1242 DI_SYNC_AS_GEN(disp));
1244 reg = __raw_readl(DI_POL(disp));
1245 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1247 reg |= DI_POL_DRDY_POLARITY_15;
1249 reg |= DI_POL_DRDY_DATA_POLARITY;
1250 __raw_writel(reg, DI_POL(disp));
1252 __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1258 * This function sets the foreground and background plane global alpha blending
1259 * modes. This function also sets the DP graphic plane according to the
1260 * parameter of IPUv3 DP channel.
1262 * @param channel IPUv3 DP channel
1264 * @param enable Boolean to enable or disable global alpha
1265 * blending. If disabled, local blending is used.
1267 * @param alpha Global alpha value.
1269 * @return Returns 0 on success or negative error code on fail
1271 int ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
1277 unsigned char bg_chan;
1279 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1280 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1281 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1284 if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1285 channel == MEM_BG_ASYNC1)
1290 ret = clk_enable(g_ipu_clk);
1295 reg = __raw_readl(DP_COM_CONF());
1296 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
1298 reg = __raw_readl(DP_COM_CONF());
1299 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
1303 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
1304 __raw_writel(reg | ((uint32_t) alpha << 24),
1305 DP_GRAPH_WIND_CTRL());
1307 reg = __raw_readl(DP_COM_CONF());
1308 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
1310 reg = __raw_readl(DP_COM_CONF());
1311 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
1314 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1315 __raw_writel(reg, IPU_SRM_PRI2);
1317 clk_disable(g_ipu_clk);
1323 * This function sets the transparent color key for SDC graphic plane.
1325 * @param channel Input parameter for the logical channel ID.
1327 * @param enable Boolean to enable or disable color key
1329 * @param colorKey 24-bit RGB color for transparent color key.
1331 * @return Returns 0 on success or negative error code on fail
1333 int ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
1339 int red, green, blue;
1341 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1342 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1343 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1346 ret = clk_enable(g_ipu_clk);
1351 /* Transform color key from rgb to yuv if CSC is enabled */
1352 if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
1353 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
1354 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
1355 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
1357 debug("color key 0x%x need change to yuv fmt\n", color_key);
1359 red = (color_key >> 16) & 0xFF;
1360 green = (color_key >> 8) & 0xFF;
1361 blue = color_key & 0xFF;
1363 y = rgb_to_yuv(0, red, green, blue);
1364 u = rgb_to_yuv(1, red, green, blue);
1365 v = rgb_to_yuv(2, red, green, blue);
1366 color_key = (y << 16) | (u << 8) | v;
1370 debug("color key change to yuv fmt 0x%x\n", color_key);
1374 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
1375 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
1377 reg = __raw_readl(DP_COM_CONF());
1378 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
1380 reg = __raw_readl(DP_COM_CONF());
1381 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
1384 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1385 __raw_writel(reg, IPU_SRM_PRI2);
1387 clk_disable(g_ipu_clk);