drivers/video/mpc8xx_lcd.c

   1 /*
   2  * (C) Copyright 2001-2002
   3  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************/
   9 /* ** HEADER FILES                                                      */
  10 /************************************************************************/
  11
  12 /* #define DEBUG */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <command.h>
  17 #include <watchdog.h>
  18 #include <version.h>
  19 #include <stdarg.h>
  20 #include <lcdvideo.h>
  21 #include <linux/types.h>
  22 #include <stdio_dev.h>
  23 #if defined(CONFIG_POST)
  24 #include <post.h>
  25 #endif
  26 #include <lcd.h>
  27
  28 #ifdef CONFIG_LCD
  29
  30 /************************************************************************/
  31 /* ** CONFIG STUFF -- should be moved to board config file              */
  32 /************************************************************************/
  33 #ifndef CONFIG_LCD_INFO
  34 #define CONFIG_LCD_INFO         /* Display Logo, (C) and system info    */
  35 #endif
  36
  37 /*----------------------------------------------------------------------*/
  38 #ifdef CONFIG_KYOCERA_KCS057QV1AJ
  39 /*
  40  *  Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
  41  */
  42 #define LCD_BPP LCD_COLOR4
  43
  44 vidinfo_t panel_info = {
  45     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  46     LCD_BPP, 1, 0, 1, 0,  5, 0, 0, 0
  47                 /* wbl, vpw, lcdac, wbf */
  48 };
  49 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
  50 /*----------------------------------------------------------------------*/
  51
  52 /*----------------------------------------------------------------------*/
  53 #ifdef CONFIG_HITACHI_SP19X001_Z1A
  54 /*
  55  *  Hitachi SP19X001-. Active, color, single scan.
  56  */
  57 vidinfo_t panel_info = {
  58     640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
  59     LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
  60                 /* wbl, vpw, lcdac, wbf */
  61 };
  62 #endif /* CONFIG_HITACHI_SP19X001_Z1A */
  63 /*----------------------------------------------------------------------*/
  64
  65 /*----------------------------------------------------------------------*/
  66 #ifdef CONFIG_NEC_NL6448AC33
  67 /*
  68  *  NEC NL6448AC33-18. Active, color, single scan.
  69  */
  70 vidinfo_t panel_info = {
  71     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
  72     3, 0, 0, 1, 1, 144, 2, 0, 33
  73                 /* wbl, vpw, lcdac, wbf */
  74 };
  75 #endif /* CONFIG_NEC_NL6448AC33 */
  76 /*----------------------------------------------------------------------*/
  77
  78 #ifdef CONFIG_NEC_NL6448BC20
  79 /*
  80  *  NEC NL6448BC20-08.  6.5", 640x480. Active, color, single scan.
  81  */
  82 vidinfo_t panel_info = {
  83     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
  84     3, 0, 0, 1, 1, 144, 2, 0, 33
  85                 /* wbl, vpw, lcdac, wbf */
  86 };
  87 #endif /* CONFIG_NEC_NL6448BC20 */
  88 /*----------------------------------------------------------------------*/
  89
  90 #ifdef CONFIG_NEC_NL6448BC33_54
  91 /*
  92  *  NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
  93  */
  94 vidinfo_t panel_info = {
  95     640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
  96     3, 0, 0, 1, 1, 144, 2, 0, 33
  97                 /* wbl, vpw, lcdac, wbf */
  98 };
  99 #endif /* CONFIG_NEC_NL6448BC33_54 */
 100 /*----------------------------------------------------------------------*/
 101
 102 #ifdef CONFIG_SHARP_LQ104V7DS01
 103 /*
 104  *  SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
 105  */
 106 vidinfo_t panel_info = {
 107     640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 108     3, 0, 0, 1, 1, 25, 1, 0, 33
 109                 /* wbl, vpw, lcdac, wbf */
 110 };
 111 #endif /* CONFIG_SHARP_LQ104V7DS01 */
 112 /*----------------------------------------------------------------------*/
 113
 114 #ifdef CONFIG_SHARP_16x9
 115 /*
 116  * Sharp 320x240. Active, color, single scan.  It isn't 16x9, and I am
 117  * not sure what it is.......
 118  */
 119 vidinfo_t panel_info = {
 120     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 121     3, 0, 0, 1, 1, 15, 4, 0, 3
 122 };
 123 #endif /* CONFIG_SHARP_16x9 */
 124 /*----------------------------------------------------------------------*/
 125
 126 #ifdef CONFIG_SHARP_LQ057Q3DC02
 127 /*
 128  * Sharp LQ057Q3DC02 display. Active, color, single scan.
 129  */
 130 #undef LCD_DF
 131 #define LCD_DF 12
 132
 133 vidinfo_t panel_info = {
 134     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 135     3, 0, 0, 1, 1, 15, 4, 0, 3
 136                 /* wbl, vpw, lcdac, wbf */
 137 };
 138 #define CONFIG_LCD_INFO_BELOW_LOGO
 139 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
 140 /*----------------------------------------------------------------------*/
 141
 142 #ifdef CONFIG_SHARP_LQ64D341
 143 /*
 144  * Sharp LQ64D341 display, 640x480. Active, color, single scan.
 145  */
 146 vidinfo_t panel_info = {
 147     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 148     3, 0, 0, 1, 1, 128, 16, 0, 32
 149                 /* wbl, vpw, lcdac, wbf */
 150 };
 151 #endif /* CONFIG_SHARP_LQ64D341 */
 152
 153 #ifdef CONFIG_SHARP_LQ065T9DR51U
 154 /*
 155  * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
 156  */
 157 vidinfo_t panel_info = {
 158     400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
 159     3, 0, 0, 1, 1, 248, 4, 0, 35
 160                 /* wbl, vpw, lcdac, wbf */
 161 };
 162 #define CONFIG_LCD_INFO_BELOW_LOGO
 163 #endif /* CONFIG_SHARP_LQ065T9DR51U */
 164
 165 #ifdef CONFIG_SHARP_LQ084V1DG21
 166 /*
 167  * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
 168  */
 169 vidinfo_t panel_info = {
 170     640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
 171     3, 0, 0, 1, 1, 160, 3, 0, 48
 172                 /* wbl, vpw, lcdac, wbf */
 173 };
 174 #endif /* CONFIG_SHARP_LQ084V1DG21 */
 175
 176 /*----------------------------------------------------------------------*/
 177
 178 #ifdef CONFIG_HLD1045
 179 /*
 180  * HLD1045 display, 640x480. Active, color, single scan.
 181  */
 182 vidinfo_t panel_info = {
 183     640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 184     3, 0, 0, 1, 1, 160, 3, 0, 48
 185                 /* wbl, vpw, lcdac, wbf */
 186 };
 187 #endif /* CONFIG_HLD1045 */
 188 /*----------------------------------------------------------------------*/
 189
 190 #ifdef CONFIG_PRIMEVIEW_V16C6448AC
 191 /*
 192  * Prime View V16C6448AC
 193  */
 194 vidinfo_t panel_info = {
 195     640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
 196     3, 0, 0, 1, 1, 144, 2, 0, 35
 197                 /* wbl, vpw, lcdac, wbf */
 198 };
 199 #endif /* CONFIG_PRIMEVIEW_V16C6448AC */
 200
 201 /*----------------------------------------------------------------------*/
 202
 203 #ifdef CONFIG_OPTREX_BW
 204 /*
 205  * Optrex   CBL50840-2 NF-FW 99 22 M5
 206  * or
 207  * Hitachi  LMG6912RPFC-00T
 208  * or
 209  * Hitachi  SP14Q002
 210  *
 211  * 320x240. Black & white.
 212  */
 213 #define OPTREX_BPP      0       /* 0 - monochrome,     1 bpp */
 214                                 /* 1 -  4 grey levels, 2 bpp */
 215                                 /* 2 - 16 grey levels, 4 bpp */
 216 vidinfo_t panel_info = {
 217     320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
 218     OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
 219 };
 220 #endif /* CONFIG_OPTREX_BW */
 221
 222 /************************************************************************/
 223 /* ----------------- chipset specific functions ----------------------- */
 224 /************************************************************************/
 225
 226 /*
 227  * Calculate fb size for VIDEOLFB_ATAG.
 228  */
 229 ulong calc_fbsize (void)
 230 {
 231         ulong size;
 232         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 233
 234         size = line_length * panel_info.vl_row;
 235
 236         return size;
 237 }
 238
 239 void lcd_ctrl_init (void *lcdbase)
 240 {
 241         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 242         volatile lcd823_t *lcdp = &immr->im_lcd;
 243
 244         uint lccrtmp;
 245         uint lchcr_hpc_tmp;
 246
 247         /* Initialize the LCD control register according to the LCD
 248          * parameters defined.  We do everything here but enable
 249          * the controller.
 250          */
 251
 252         lccrtmp  = LCDBIT (LCCR_BNUM_BIT,
 253                    (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
 254
 255         lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp)   |
 256                    LCDBIT (LCCR_OEP_BIT,  panel_info.vl_oep)    |
 257                    LCDBIT (LCCR_HSP_BIT,  panel_info.vl_hsp)    |
 258                    LCDBIT (LCCR_VSP_BIT,  panel_info.vl_vsp)    |
 259                    LCDBIT (LCCR_DP_BIT,   panel_info.vl_dp)     |
 260                    LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix)   |
 261                    LCDBIT (LCCR_LBW_BIT,  panel_info.vl_lbw)    |
 262                    LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt)   |
 263                    LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor)   |
 264                    LCDBIT (LCCR_TFT_BIT,  panel_info.vl_tft);
 265
 266 #if 0
 267         lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
 268         lccrtmp |= LCCR_EIEN;
 269 #endif
 270
 271         lcdp->lcd_lccr = lccrtmp;
 272         lcdp->lcd_lcsr = 0xFF;          /* Clear pending interrupts */
 273
 274         /* Initialize LCD controller bus priorities.
 275          */
 276         immr->im_siu_conf.sc_sdcr &= ~0x0f;     /* RAID = LAID = 0 */
 277
 278         /* set SHFT/CLOCK division factor 4
 279          * This needs to be set based upon display type and processor
 280          * speed.  The TFT displays run about 20 to 30 MHz.
 281          * I was running 64 MHz processor speed.
 282          * The value for this divider must be chosen so the result is
 283          * an integer of the processor speed (i.e., divide by 3 with
 284          * 64 MHz would be bad).
 285          */
 286         immr->im_clkrst.car_sccr &= ~0x1F;
 287         immr->im_clkrst.car_sccr |= LCD_DF;     /* was 8 */
 288
 289         /* Enable LCD on port D.
 290          */
 291         immr->im_ioport.iop_pdpar |= 0x1FFF;
 292         immr->im_ioport.iop_pddir |= 0x1FFF;
 293
 294         /* Enable LCD_A/B/C on port B.
 295          */
 296         immr->im_cpm.cp_pbpar |= 0x00005001;
 297         immr->im_cpm.cp_pbdir |= 0x00005001;
 298
 299         /* Load the physical address of the linear frame buffer
 300          * into the LCD controller.
 301          * BIG NOTE:  This has to be modified to load A and B depending
 302          * upon the split mode of the LCD.
 303          */
 304         lcdp->lcd_lcfaa = (ulong)lcdbase;
 305         lcdp->lcd_lcfba = (ulong)lcdbase;
 306
 307         /* MORE HACKS...This must be updated according to 823 manual
 308          * for different panels.
 309          * Udi Finkelstein - done - see below:
 310          * Note: You better not try unsupported combinations such as
 311          * 4-bit wide passive dual scan LCD at 4/8 Bit color.
 312          */
 313         lchcr_hpc_tmp =
 314                 (panel_info.vl_col *
 315                  (panel_info.vl_tft ? 8 :
 316                         (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
 317                          /* use << to mult by: single scan = 1, dual scan = 2 */
 318                           panel_info.vl_splt) *
 319                          (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
 320
 321         lcdp->lcd_lchcr = LCHCR_BO |
 322                           LCDBIT (LCHCR_AT_BIT, 4) |
 323                           LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
 324                           panel_info.vl_wbl;
 325
 326         lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
 327                           LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
 328                           LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
 329                           panel_info.vl_wbf;
 330
 331 }
 332
 333 /*----------------------------------------------------------------------*/
 334
 335 #if LCD_BPP == LCD_COLOR8
 336 void
 337 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 338 {
 339         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 340         volatile cpm8xx_t *cp = &(immr->im_cpm);
 341         unsigned short colreg, *cmap_ptr;
 342
 343         cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
 344
 345         colreg = ((red   & 0x0F) << 8) |
 346                  ((green & 0x0F) << 4) |
 347                   (blue  & 0x0F) ;
 348
 349         *cmap_ptr = colreg;
 350
 351         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
 352                 regno, &(cp->lcd_cmap[regno * 2]),
 353                 red, green, blue,
 354                 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
 355 }
 356 #endif  /* LCD_COLOR8 */
 357
 358 /*----------------------------------------------------------------------*/
 359
 360 ushort *configuration_get_cmap(void)
 361 {
 362         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 363         cpm8xx_t *cp = &(immr->im_cpm);
 364         return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
 365 }
 366
 367 #if defined(CONFIG_MPC823)
 368 void fb_put_byte(uchar **fb, uchar **from)
 369 {
 370         *(*fb)++ = (255 - *(*from)++);
 371 }
 372 #endif
 373
 374 void lcd_enable (void)
 375 {
 376         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 377         volatile lcd823_t *lcdp = &immr->im_lcd;
 378
 379         /* Enable the LCD panel */
 380         immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));          /* LAM = 1 */
 381         lcdp->lcd_lccr |= LCCR_PON;
 382 }
 383
 384 /************************************************************************/
 385
 386 #endif /* CONFIG_LCD */