2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* Stuff on L3 Interconnect */
30 #define SMX_APE_BASE 0x68000000
33 #define OMAP34XX_GPMC_BASE 0x6E000000
36 #define OMAP34XX_SMS_BASE 0x6C000000
39 #define OMAP34XX_SDRC_BASE 0x6D000000
42 * L4 Peripherals - L4 Wakeup and L4 Core now
44 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
45 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
46 #define OMAP34XX_L4_PER 0x49000000
47 #define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
50 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
53 #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
54 #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
55 #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
57 /* General Purpose Timers */
58 #define OMAP34XX_GPT1 0x48318000
59 #define OMAP34XX_GPT2 0x49032000
60 #define OMAP34XX_GPT3 0x49034000
61 #define OMAP34XX_GPT4 0x49036000
62 #define OMAP34XX_GPT5 0x49038000
63 #define OMAP34XX_GPT6 0x4903A000
64 #define OMAP34XX_GPT7 0x4903C000
65 #define OMAP34XX_GPT8 0x4903E000
66 #define OMAP34XX_GPT9 0x49040000
67 #define OMAP34XX_GPT10 0x48086000
68 #define OMAP34XX_GPT11 0x48088000
69 #define OMAP34XX_GPT12 0x48304000
71 /* WatchDog Timers (1 secure, 3 GP) */
72 #define WD1_BASE 0x4830C000
73 #define WD2_BASE 0x48314000
74 #define WD3_BASE 0x49030000
77 #define SYNC_32KTIMER_BASE 0x48320000
81 typedef struct s32ktimer {
82 unsigned char res[0x10];
83 unsigned int s32k_cr; /* 0x10 */
86 #endif /* __ASSEMBLY__ */
88 /* OMAP3 GPIO registers */
89 #define OMAP34XX_GPIO1_BASE 0x48310000
90 #define OMAP34XX_GPIO2_BASE 0x49050000
91 #define OMAP34XX_GPIO3_BASE 0x49052000
92 #define OMAP34XX_GPIO4_BASE 0x49054000
93 #define OMAP34XX_GPIO5_BASE 0x49056000
94 #define OMAP34XX_GPIO6_BASE 0x49058000
98 unsigned char res1[0x34];
99 unsigned int oe; /* 0x34 */
100 unsigned int datain; /* 0x38 */
101 unsigned char res2[0x54];
102 unsigned int cleardataout; /* 0x90 */
103 unsigned int setdataout; /* 0x94 */
105 #endif /* __ASSEMBLY__ */
107 #define GPIO0 (0x1 << 0)
108 #define GPIO1 (0x1 << 1)
109 #define GPIO2 (0x1 << 2)
110 #define GPIO3 (0x1 << 3)
111 #define GPIO4 (0x1 << 4)
112 #define GPIO5 (0x1 << 5)
113 #define GPIO6 (0x1 << 6)
114 #define GPIO7 (0x1 << 7)
115 #define GPIO8 (0x1 << 8)
116 #define GPIO9 (0x1 << 9)
117 #define GPIO10 (0x1 << 10)
118 #define GPIO11 (0x1 << 11)
119 #define GPIO12 (0x1 << 12)
120 #define GPIO13 (0x1 << 13)
121 #define GPIO14 (0x1 << 14)
122 #define GPIO15 (0x1 << 15)
123 #define GPIO16 (0x1 << 16)
124 #define GPIO17 (0x1 << 17)
125 #define GPIO18 (0x1 << 18)
126 #define GPIO19 (0x1 << 19)
127 #define GPIO20 (0x1 << 20)
128 #define GPIO21 (0x1 << 21)
129 #define GPIO22 (0x1 << 22)
130 #define GPIO23 (0x1 << 23)
131 #define GPIO24 (0x1 << 24)
132 #define GPIO25 (0x1 << 25)
133 #define GPIO26 (0x1 << 26)
134 #define GPIO27 (0x1 << 27)
135 #define GPIO28 (0x1 << 28)
136 #define GPIO29 (0x1 << 29)
137 #define GPIO30 (0x1 << 30)
138 #define GPIO31 (0x1 << 31)
140 /* base address for indirect vectors (internal boot mode) */
141 #define SRAM_OFFSET0 0x40000000
142 #define SRAM_OFFSET1 0x00200000
143 #define SRAM_OFFSET2 0x0000F800
144 #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
147 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC
149 #define DEBUG_LED1 149 /* gpio */
150 #define DEBUG_LED2 150 /* gpio */
152 #define XDR_POP 5 /* package on package part */
153 #define SDR_DISCRETE 4 /* 128M memory SDR module */
154 #define DDR_STACKED 3 /* stacked part on 2422 */
155 #define DDR_COMBO 2 /* combo part on cpu daughter card */
156 #define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
158 #define DDR_100 100 /* type found on most mem d-boards */
159 #define DDR_111 111 /* some combo parts */
160 #define DDR_133 133 /* most combo, some mem d-boards */
161 #define DDR_165 165 /* future parts */
163 #define CPU_3430 0x3430
166 * 343x real hardware:
173 #define CPU_3430_ES1 1
174 #define CPU_3430_ES2 2
176 #define WIDTH_8BIT 0x0000
177 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
179 /* SDP definitions according to FPGA Rev. Is this OK?? */
180 #define SDP_3430_V1 0x1
181 #define SDP_3430_V2 0x2
183 /* EVM definitions */
184 #define OMAP3EVM_V1 0x1
185 #define OMAP3EVM_V2 0x2
187 /* I2C power management companion definitions */
188 #define PWRMGT_ADDR_ID1 0x48
189 #define PWRMGT_ADDR_ID2 0x49
190 #define PWRMGT_ADDR_ID3 0x4A
191 #define PWRMGT_ADDR_ID4 0x4B
193 /* I2C ID3 (slave3) register */
196 #define LEDAON (0x1 << 0)
197 #define LEDBON (0x1 << 1)
198 #define LEDAPWM (0x1 << 4)
199 #define LEDBPWM (0x1 << 5)
201 /* I2C ID4 (slave4) register */
202 #define VAUX2_DEV_GRP 0x76
203 #define VAUX2_DEDICATED 0x79
204 #define VAUX3_DEV_GRP 0x7A
205 #define VAUX3_DEDICATED 0x7D
206 #define VMMC1_DEV_GRP 0x82
207 #define VMMC1_DEDICATED 0x85
208 #define VPLL2_DEV_GRP 0x8E
209 #define VPLL2_DEDICATED 0x91
210 #define VDAC_DEV_GRP 0x96
211 #define VDAC_DEDICATED 0x99
213 #define DEV_GRP_P1 0x20
214 #define DEV_GRP_ALL 0xE0
216 #define VAUX2_VSEL_28 0x09
217 #define VAUX3_VSEL_28 0x03
218 #define VPLL2_VSEL_18 0x05
219 #define VDAC_VSEL_18 0x03
220 #define VMMC1_VSEL_30 0x02