include/asm-ppc/e300.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor, Inc.
   3  * Liberty Eran (liberty@freescale.com)
   4  */
   5
   6 #ifndef __E300_H__
   7 #define __E300_H__
   8
   9 /*
  10  * e300 Processor Version & Revision Numbers
  11  */
  12 #define PVR_83xx 0x80830000
  13 #define PVR_8349_REV10 (PVR_83xx | 0x0010)
  14 #define PVR_8349_REV11 (PVR_83xx | 0x0011)
  15 #define PVR_8360_REV10 (PVR_83xx | 0x0020)
  16 #define PVR_8360_REV11 (PVR_83xx | 0x0020)
  17
  18 #if defined(CONFIG_MPC832X)
  19 #undef PVR_83xx
  20 #define PVR_83xx 0x80840000
  21 #endif
  22
  23 /*
  24  * Hardware Implementation-Dependent Register 0 (HID0)
  25  */
  26
  27 /* #define HID0 1008 already defined in processor.h */
  28 #define HID0_MASK_MACHINE_CHECK              0x00000000
  29 #define HID0_ENABLE_MACHINE_CHECK            0x80000000
  30
  31 #define HID0_DISABLE_CACHE_PARITY            0x00000000
  32 #define HID0_ENABLE_CACHE_PARITY             0x40000000
  33
  34 #define HID0_DISABLE_ADDRESS_PARITY          0x00000000 /* on mpc8349ads must be disabled */
  35 #define HID0_ENABLE_ADDRESS_PARITY           0x20000000
  36
  37 #define HID0_DISABLE_DATA_PARITY             0x00000000 /* on mpc8349ads must be disabled */
  38 #define HID0_ENABLE_DATE_PARITY              0x10000000
  39
  40 #define HID0_CORE_CLK_OUT                    0x00000000
  41 #define HID0_CORE_CLK_OUT_DIV_2              0x08000000
  42
  43 #define HID0_ENABLE_ARTRY_OUT_PRECHARGE      0x00000000 /* on mpc8349ads must be enabled */
  44 #define HID0_DISABLE_ARTRY_OUT_PRECHARGE     0x01000000
  45
  46 #define HID0_DISABLE_DOSE_MODE               0x00000000
  47 #define HID0_ENABLE_DOSE_MODE                0x00800000
  48
  49 #define HID0_DISABLE_NAP_MODE                0x00000000
  50 #define HID0_ENABLE_NAP_MODE                 0x00400000
  51
  52 #define HID0_DISABLE_SLEEP_MODE              0x00000000
  53 #define HID0_ENABLE_SLEEP_MODE               0x00200000
  54
  55 #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
  56 #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT  0x00100000
  57
  58 #define HID0_SOFT_RESET                      0x00010000
  59
  60 #define HID0_DISABLE_INSTRUCTION_CACHE       0x00000000
  61 #define HID0_ENABLE_INSTRUCTION_CACHE        0x00008000
  62
  63 #define HID0_DISABLE_DATA_CACHE              0x00000000
  64 #define HID0_ENABLE_DATA_CACHE               0x00004000
  65
  66 #define HID0_LOCK_INSTRUCTION_CACHE          0x00002000
  67
  68 #define HID0_LOCK_DATA_CACHE                 0x00001000
  69
  70 #define HID0_INVALIDATE_INSTRUCTION_CACHE    0x00000800
  71
  72 #define HID0_INVALIDATE_DATA_CACHE           0x00000400
  73
  74 #define HID0_DISABLE_M_BIT                   0x00000000
  75 #define HID0_ENABLE_M_BIT                    0x00000080
  76
  77 #define HID0_FBIOB                           0x00000010
  78
  79 #define HID0_DISABLE_ADDRESS_BROADCAST       0x00000000
  80 #define HID0_ENABLE_ADDRESS_BROADCAST        0x00000008
  81
  82 #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION  0x00000000
  83 #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
  84
  85 /*
  86  * Hardware Implementation-Dependent Register 2 (HID2)
  87  */
  88 #define HID2            1011
  89
  90 #define HID2_LET       0x08000000
  91 #define HID2_HBE       0x00040000
  92 #define HID2_IWLCK_000 0x00000000 /* no ways locked */
  93 #define HID2_IWLCK_001 0x00002000 /* way 0 locked */
  94 #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
  95 #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
  96 #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
  97 #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
  98 #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
  99
 100
 101 /* BAT (block address translation */
 102 #define BATU_BEPI_MSK       0xfffe0000
 103 #define BATU_BL_MSK         0x00001ffc
 104
 105 #define BATU_BL_128K        0x00000000
 106 #define BATU_BL_256K        0x00000004
 107 #define BATU_BL_512K        0x0000000c
 108 #define BATU_BL_1M          0x0000001c
 109 #define BATU_BL_2M          0x0000003c
 110 #define BATU_BL_4M          0x0000007c
 111 #define BATU_BL_8M          0x000000fc
 112 #define BATU_BL_16M         0x000001fc
 113 #define BATU_BL_32M         0x000003fc
 114 #define BATU_BL_64M         0x000007fc
 115 #define BATU_BL_128M        0x00000ffc
 116 #define BATU_BL_256M        0x00001ffc
 117
 118 #define BATU_VS             0x00000002
 119 #define BATU_VP             0x00000001
 120
 121 #define BATL_BRPN_MSK       0xfffe0000
 122 #define BATL_WIMG_MSK       0x00000078
 123
 124 #define BATL_WRITETHROUGH   0x00000040
 125 #define BATL_CACHEINHIBIT   0x00000020
 126 #define BATL_MEMCOHERENCE   0x00000010
 127 #define BATL_GUARDEDSTORAGE 0x00000008
 128
 129 #define BATL_PP_MSK         0x00000003
 130 #define BATL_PP_00          0x00000000 /* No access */
 131 #define BATL_PP_01          0x00000001 /* Read-only */
 132 #define BATL_PP_10          0x00000002 /* Read-write */
 133 #define BATL_PP_11              0x00000003
 134
 135 #endif  /* __E300_H__ */