2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 #define GTREGREAD(x) 0xffffffff /* needed for debug */
18 * High Level Configuration Options
22 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
24 /* these hardware addresses are pretty bogus, please change them to
28 #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
30 #define CONFIG_IPADDR 192.168.0.105
31 #define CONFIG_SERVERIP 192.168.0.100
33 #define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
35 #define CONFIG_BAUDRATE 9600 /* console baudrate */
37 #undef CONFIG_WATCHDOG
39 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
41 #define CONFIG_ZERO_BOOTDELAY_CHECK
43 #undef CONFIG_BOOTARGS
44 #define CONFIG_BOOTCOMMAND \
46 "setenv bootargs root=ramfs console=ttyS00,9600 " \
47 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
48 "${netmask}:${hostname}:eth0:none; " \
51 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
52 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
57 #define CONFIG_BOOTP_SUBNETMASK
58 #define CONFIG_BOOTP_GATEWAY
59 #define CONFIG_BOOTP_HOSTNAME
60 #define CONFIG_BOOTP_BOOTPATH
62 #define CONFIG_BOOTP_BOOTFILESIZE
66 * Command line configuration.
68 #include <config_cmd_default.h>
70 #define CONFIG_CMD_PCI
71 #define CONFIG_CMD_JFFS2
75 * Miscellaneous configurable options
77 #define CONFIG_SYS_LONGHELP /* undef to save memory */
80 * choose between COM1 and COM2 as serial console
82 #define CONFIG_CONS_INDEX 1
84 #if defined(CONFIG_CMD_KGDB)
85 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
87 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
89 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
90 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
91 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
93 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
94 #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
96 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
98 #define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */
100 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
103 * Low Level Configuration Settings
104 * (address mappings, register initial values, etc.)
105 * You should know what you are doing if you make changes here.
107 #define CONFIG_SYS_BOARD_ASM_INIT
108 #define CONFIG_MISC_INIT_R
111 * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
113 #undef CONFIG_SYS_ADDRESS_MAP_A
115 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
116 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
117 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
119 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
120 #define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
121 #define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
123 #define CONFIG_SYS_ISA_MEM_BUS 0x00000000
124 #define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
125 #define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
127 #define CONFIG_SYS_PCI_IO_BUS 0x00800000
128 #define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
129 #define CONFIG_SYS_PCI_IO_SIZE 0x00400000
131 #define CONFIG_SYS_ISA_IO_BUS 0x00000000
132 #define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
133 #define CONFIG_SYS_ISA_IO_SIZE 0x00800000
135 /* driver defines FDC,IDE,... */
136 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
137 #define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
138 #define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
141 * Start addresses for the final memory configuration
142 * (Set up by the startup code)
143 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
145 #define CONFIG_SYS_SDRAM_BASE 0x00000000
147 #define CONFIG_SYS_USR_LED_BASE 0x78000000
148 #define CONFIG_SYS_NVRAM_BASE 0xff000000
149 #define CONFIG_SYS_UART_BASE 0xff400000
150 #define CONFIG_SYS_FLASH_BASE 0xfff00000
152 #define MPC107_EUMB_ADDR 0xfce00000
153 #define MPC107_EUMB_PI 0xfce41090
154 #define MPC107_EUMB_GCR 0xfce41020
155 #define MPC107_EUMB_IACKR 0xfce600a0
156 #define MPC107_I2C_ADDR 0xfce03000
159 * Definitions for initial stack pointer and data area
161 #define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
162 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
163 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
167 * Flash mapping/organization on the MPC10x.
169 #define FLASH_BASE0_PRELIM 0xff800000
170 #define FLASH_BASE1_PRELIM 0xffc00000
172 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
173 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
175 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
182 /* No command line, one static partition, whole device */
183 #undef CONFIG_CMD_MTDPARTS
184 #define CONFIG_JFFS2_DEV "nor0"
185 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
186 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
188 /* mtdparts command line support */
189 /* Note: fake mtd_id used, no linux mtd map file */
191 #define CONFIG_CMD_MTDPARTS
192 #define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
193 #define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
196 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
197 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
198 #define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
199 #undef CONFIG_SYS_MEMTEST
202 * Environment settings
204 #define CONFIG_ENV_OVERWRITE
205 #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
206 #define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
207 #define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
208 #define CONFIG_ENV_ADDR 0x0
209 #define CONFIG_ENV_MAP_ADRS 0xff000000
210 #define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
211 #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
212 #define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
217 #define CONFIG_SYS_NS16550
218 #define CONFIG_SYS_NS16550_SERIAL
219 #define CONFIG_SYS_NS16550_REG_SIZE 1
220 #define CONFIG_SYS_NS16550_CLK 24000000
221 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0)
222 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8)
227 #define CONFIG_PCI /* include pci support */
228 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
229 #define CONFIG_PCI_PNP /* pci plug-and-play */
230 #define CONFIG_PCI_HOST PCI_HOST_AUTO
231 #undef CONFIG_PCI_SCAN_SHOW
234 * Optional Video console (graphic: SMI LynxEM)
237 #define CONFIG_CFB_CONSOLE
238 #define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
239 #define VIDEO_TSTC_FCT serial_tstc
240 #define VIDEO_GETC_FCT serial_getc
242 #define CONFIG_VIDEO_SMI_LYNXEM
243 #define CONFIG_VIDEO_LOGO
244 #define CONFIG_CONSOLE_EXTRA_INFO
251 #define CONFIG_SYS_IBAT0L 0
252 #define CONFIG_SYS_IBAT0U 0
253 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
254 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
256 #define CONFIG_SYS_IBAT1L 0
257 #define CONFIG_SYS_IBAT1U 0
258 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
259 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
261 #define CONFIG_SYS_IBAT2L 0
262 #define CONFIG_SYS_IBAT2U 0
263 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
264 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
266 #define CONFIG_SYS_IBAT3L 0
267 #define CONFIG_SYS_IBAT3U 0
268 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
269 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
274 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
275 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
276 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
277 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
279 /* address range for flashes */
280 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
281 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
282 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
283 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
286 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
287 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
288 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
289 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
291 /* ISA memory space */
292 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
293 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
294 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
295 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
300 * Speed settings are board specific
302 #define CONFIG_SYS_BUS_CLK 100000000
303 #define CONFIG_SYS_CPU_CLK 400000000
306 * For booting Linux, the board info and command line data
307 * have to be in the first 8 MB of memory, since this is
308 * the maximum mapped by the Linux kernel during initialization.
310 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
313 * Cache Configuration
315 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
316 #if defined(CONFIG_CMD_KGDB)
317 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
321 * L2CR setup -- make sure this is right for your board!
322 * look in include/74xx_7xx.h for the defines used here
325 #define CONFIG_SYS_L2
328 #define L2_INIT 0 /* cpu 750 CXe*/
330 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
331 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
333 #define L2_ENABLE (L2_INIT | L2CR_L2E)
335 #define CONFIG_EEPRO100
336 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
337 #define CONFIG_EEPRO100_SROM_WRITE
339 #endif /* __CONFIG_H */