include/configs/MPC8315ERDB.h

   1 /*
   2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #ifdef CONFIG_NAND
  29 #define CONFIG_NAND_U_BOOT              1
  30 #define CONFIG_SYS_TEXT_BASE    0x00100000
  31 #endif
  32
  33 #ifndef CONFIG_SYS_TEXT_BASE
  34 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  35 #endif
  36
  37 /*
  38  * High Level Configuration Options
  39  */
  40 #define CONFIG_E300             1 /* E300 family */
  41 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  42 #define CONFIG_MPC831x          1 /* MPC831x CPU family */
  43 #define CONFIG_MPC8315          1 /* MPC8315 CPU specific */
  44 #define CONFIG_MPC8315ERDB      1 /* MPC8315ERDB board specific */
  45
  46 /*
  47  * System Clock Setup
  48  */
  49 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  50 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  51
  52 /*
  53  * Hardware Reset Configuration Word
  54  * if CLKIN is 66.66MHz, then
  55  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  56  */
  57 #define CONFIG_SYS_HRCW_LOW (\
  58         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  59         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  60         HRCWL_SVCOD_DIV_2 |\
  61         HRCWL_CSB_TO_CLKIN_2X1 |\
  62         HRCWL_CORE_TO_CSB_3X1)
  63 #define CONFIG_SYS_HRCW_HIGH_BASE (\
  64         HRCWH_PCI_HOST |\
  65         HRCWH_PCI1_ARBITER_ENABLE |\
  66         HRCWH_CORE_ENABLE |\
  67         HRCWH_BOOTSEQ_DISABLE |\
  68         HRCWH_SW_WATCHDOG_DISABLE |\
  69         HRCWH_TSEC1M_IN_RGMII |\
  70         HRCWH_TSEC2M_IN_RGMII |\
  71         HRCWH_BIG_ENDIAN |\
  72         HRCWH_LALE_NORMAL)
  73
  74 #ifdef CONFIG_NAND_SPL
  75 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  76                        HRCWH_FROM_0XFFF00100 |\
  77                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
  78                        HRCWH_RL_EXT_NAND)
  79 #else
  80 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  81                        HRCWH_FROM_0X00000100 |\
  82                        HRCWH_ROM_LOC_LOCAL_16BIT |\
  83                        HRCWH_RL_EXT_LEGACY)
  84 #endif
  85
  86 /*
  87  * System IO Config
  88  */
  89 #define CONFIG_SYS_SICRH                0x00000000
  90 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  91
  92 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  93 #define CONFIG_HWCONFIG
  94
  95 /*
  96  * IMMR new address
  97  */
  98 #define CONFIG_SYS_IMMR         0xE0000000
  99
 100 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 101 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
 102 #endif
 103
 104 /*
 105  * Arbiter Setup
 106  */
 107 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 108 #define CONFIG_SYS_ACR_RPTCNT           3 /* Arbiter repeat count is 4 */
 109 #define CONFIG_SYS_SPCR_TSECEP          3 /* eTSEC emergency priority is highest */
 110
 111 /*
 112  * DDR Setup
 113  */
 114 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 115 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 116 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 117 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 118 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
 119                                 | DDRCDR_PZ_LOZ \
 120                                 | DDRCDR_NZ_LOZ \
 121                                 | DDRCDR_ODT \
 122                                 | DDRCDR_Q_DRN )
 123                                 /* 0x7b880001 */
 124 /*
 125  * Manually set up DDR parameters
 126  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 127  */
 128 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 129 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 130 #define CONFIG_SYS_DDR_CS0_CONFIG       ( CSCONFIG_EN \
 131                                 | 0x00010000  /* ODT_WR to CSn */ \
 132                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 133                                 /* 0x80010102 */
 134 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 135 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 136                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 137                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 138                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 139                                 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 140                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 141                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 142                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 143                                 /* 0x00220802 */
 144 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
 145                                 | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 146                                 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
 147                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 148                                 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
 149                                 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
 150                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 151                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 152                                 /* 0x27256222 */
 153 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 154                                 | ( 4 << TIMING_CFG2_CPO_SHIFT ) \
 155                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 156                                 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 157                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 158                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 159                                 | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 160                                 /* 0x121048c5 */
 161 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 162                                 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 163                                 /* 0x03600100 */
 164 #define CONFIG_SYS_DDR_SDRAM_CFG        ( SDRAM_CFG_SREN \
 165                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 166                                 | SDRAM_CFG_32_BE )
 167                                 /* 0x43080000 */
 168 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 169 #define CONFIG_SYS_DDR_MODE             ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
 170                                 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
 171                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 172 #define CONFIG_SYS_DDR_MODE2            0x00000000
 173
 174 /*
 175  * Memory test
 176  */
 177 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 178 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 179 #define CONFIG_SYS_MEMTEST_END          0x00140000
 180
 181 /*
 182  * The reserved memory
 183  */
 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 185
 186 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 187 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024) /* Reserved for malloc */
 188
 189 /*
 190  * Initial RAM Base Address Setup
 191  */
 192 #define CONFIG_SYS_INIT_RAM_LOCK        1
 193 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 194 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 195 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 196 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 197
 198 /*
 199  * Local Bus Configuration & Clock Setup
 200  */
 201 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 202 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 203 #define CONFIG_SYS_LBC_LBCR             0x00040000
 204 #define CONFIG_FSL_ELBC         1
 205
 206 /*
 207  * FLASH on the Local Bus
 208  */
 209 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 210 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 211 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 212
 213 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 214 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 215 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 216
 217 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 218 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016 /* 8MB window size */
 219
 220 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 221                                 | (2 << BR_PS_SHIFT)    /* 16 bit port size */ \
 222                                 | BR_V )                /* valid */
 223 #define CONFIG_SYS_NOR_OR_PRELIM        ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 224                                 | OR_UPM_XAM \
 225                                 | OR_GPCM_CSNT \
 226                                 | OR_GPCM_ACS_DIV2 \
 227                                 | OR_GPCM_XACS \
 228                                 | OR_GPCM_SCY_15 \
 229                                 | OR_GPCM_TRLX \
 230                                 | OR_GPCM_EHTR \
 231                                 | OR_GPCM_EAD )
 232
 233 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 234 #define CONFIG_SYS_MAX_FLASH_SECT       135 /* 127 64KB sectors and 8 8KB top sectors per device */
 235
 236 #undef CONFIG_SYS_FLASH_CHECKSUM
 237 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 238 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 239
 240 /*
 241  * NAND Flash on the Local Bus
 242  */
 243
 244 #ifdef CONFIG_NAND_SPL
 245 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 246 #else
 247 #define CONFIG_SYS_NAND_BASE            0xE0600000
 248 #endif
 249
 250 #define CONFIG_MTD_DEVICE
 251 #define CONFIG_MTD_PARTITION
 252 #define CONFIG_CMD_MTDPARTS
 253 #define MTDIDS_DEFAULT                  "nand0=e0600000.flash"
 254 #define MTDPARTS_DEFAULT                \
 255         "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
 256
 257 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 258 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 259 #define CONFIG_CMD_NAND                 1
 260 #define CONFIG_NAND_FSL_ELBC            1
 261 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 262
 263 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 264 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 265 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 266 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 267 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 268
 269 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 270                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 271                                 | BR_PS_8               /* Port Size = 8 bit */ \
 272                                 | BR_MS_FCM             /* MSEL = FCM */ \
 273                                 | BR_V )                /* valid */
 274 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFF8000     /* length 32K */ \
 275                                 | OR_FCM_CSCT \
 276                                 | OR_FCM_CST \
 277                                 | OR_FCM_CHT \
 278                                 | OR_FCM_SCY_1 \
 279                                 | OR_FCM_TRLX \
 280                                 | OR_FCM_EHTR )
 281                                 /* 0xFFFF8396 */
 282
 283 #ifdef CONFIG_NAND_U_BOOT
 284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 286 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 287 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 288 #else
 289 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 290 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 291 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 292 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 293 #endif
 294
 295 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 296 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E      /* 32KB  */
 297
 298 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 299 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 300
 301 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 302         !defined(CONFIG_NAND_SPL)
 303 #define CONFIG_SYS_RAMBOOT
 304 #else
 305 #undef CONFIG_SYS_RAMBOOT
 306 #endif
 307
 308 /*
 309  * Serial Port
 310  */
 311 #define CONFIG_CONS_INDEX       1
 312 #define CONFIG_SYS_NS16550
 313 #define CONFIG_SYS_NS16550_SERIAL
 314 #define CONFIG_SYS_NS16550_REG_SIZE     1
 315 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 316
 317 #define CONFIG_SYS_BAUDRATE_TABLE  \
 318         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 319
 320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 322
 323 /* Use the HUSH parser */
 324 #define CONFIG_SYS_HUSH_PARSER
 325 #ifdef CONFIG_SYS_HUSH_PARSER
 326 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 327 #endif
 328
 329 /* Pass open firmware flat tree */
 330 #define CONFIG_OF_LIBFDT        1
 331 #define CONFIG_OF_BOARD_SETUP   1
 332 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 333
 334 /* I2C */
 335 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 336 #define CONFIG_FSL_I2C
 337 #define CONFIG_SYS_I2C_SPEED            400000 /* I2C speed and slave address */
 338 #define CONFIG_SYS_I2C_SLAVE            0x7F
 339 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
 340 #define CONFIG_SYS_I2C_OFFSET           0x3000
 341 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 342
 343 /*
 344  * Board info - revision and where boot from
 345  */
 346 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 347
 348 /*
 349  * Config on-board RTC
 350  */
 351 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 352 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 353
 354 /*
 355  * General PCI
 356  * Addresses are mapped 1-1.
 357  */
 358 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
 359 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 360 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
 361 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 362 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 363 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 364 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 365 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 366 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 367
 368 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 369 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 370 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 371
 372 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 373 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 374 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 375 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 376 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 377 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 378 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 379 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 380 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 381
 382 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 383 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 384 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 385 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 386 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 387 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 388 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 389 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 390 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 391
 392 #define CONFIG_PCI
 393 #define CONFIG_PCIE
 394
 395 #define CONFIG_NET_MULTI
 396 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 397
 398 #define CONFIG_EEPRO100
 399 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 400 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 401
 402 #ifndef CONFIG_NET_MULTI
 403 #define CONFIG_NET_MULTI        1
 404 #endif
 405
 406 #define CONFIG_HAS_FSL_DR_USB
 407 #define CONFIG_SYS_SCCR_USBDRCM         3
 408
 409 #define CONFIG_CMD_USB
 410 #define CONFIG_USB_STORAGE
 411 #define CONFIG_USB_EHCI
 412 #define CONFIG_USB_EHCI_FSL
 413 #define CONFIG_USB_PHY_TYPE     "utmi"
 414 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 415
 416 /*
 417  * TSEC
 418  */
 419 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 420 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 421 #define CONFIG_SYS_TSEC1                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 422 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 423 #define CONFIG_SYS_TSEC2                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 424
 425 /*
 426  * TSEC ethernet configuration
 427  */
 428 #define CONFIG_MII              1 /* MII PHY management */
 429 #define CONFIG_TSEC1            1
 430 #define CONFIG_TSEC1_NAME       "eTSEC0"
 431 #define CONFIG_TSEC2            1
 432 #define CONFIG_TSEC2_NAME       "eTSEC1"
 433 #define TSEC1_PHY_ADDR          0
 434 #define TSEC2_PHY_ADDR          1
 435 #define TSEC1_PHYIDX            0
 436 #define TSEC2_PHYIDX            0
 437 #define TSEC1_FLAGS             TSEC_GIGABIT
 438 #define TSEC2_FLAGS             TSEC_GIGABIT
 439
 440 /* Options are: eTSEC[0-1] */
 441 #define CONFIG_ETHPRIME         "eTSEC1"
 442
 443 /*
 444  * SATA
 445  */
 446 #define CONFIG_LIBATA
 447 #define CONFIG_FSL_SATA
 448
 449 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 450 #define CONFIG_SATA1
 451 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 452 #define CONFIG_SYS_SATA1                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 453 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 454 #define CONFIG_SATA2
 455 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 456 #define CONFIG_SYS_SATA2                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 457 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 458
 459 #ifdef CONFIG_FSL_SATA
 460 #define CONFIG_LBA48
 461 #define CONFIG_CMD_SATA
 462 #define CONFIG_DOS_PARTITION
 463 #define CONFIG_CMD_EXT2
 464 #endif
 465
 466 /*
 467  * Environment
 468  */
 469 #if defined(CONFIG_NAND_U_BOOT)
 470         #define CONFIG_ENV_IS_IN_NAND   1
 471         #define CONFIG_ENV_OFFSET               (512 * 1024)
 472         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 473         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 474         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 475         #define CONFIG_ENV_RANGE        (CONFIG_ENV_SECT_SIZE * 4)
 476         #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 477                                                  CONFIG_ENV_RANGE)
 478 #elif !defined(CONFIG_SYS_RAMBOOT)
 479         #define CONFIG_ENV_IS_IN_FLASH  1
 480         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 481         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 482         #define CONFIG_ENV_SIZE         0x2000
 483 #else
 484         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 485         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 486         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 487         #define CONFIG_ENV_SIZE         0x2000
 488 #endif
 489
 490 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 491 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 492
 493 /*
 494  * BOOTP options
 495  */
 496 #define CONFIG_BOOTP_BOOTFILESIZE
 497 #define CONFIG_BOOTP_BOOTPATH
 498 #define CONFIG_BOOTP_GATEWAY
 499 #define CONFIG_BOOTP_HOSTNAME
 500
 501 /*
 502  * Command line configuration.
 503  */
 504 #include <config_cmd_default.h>
 505
 506 #define CONFIG_CMD_PING
 507 #define CONFIG_CMD_I2C
 508 #define CONFIG_CMD_MII
 509 #define CONFIG_CMD_DATE
 510 #define CONFIG_CMD_PCI
 511
 512 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 513     #undef CONFIG_CMD_SAVEENV
 514     #undef CONFIG_CMD_LOADS
 515 #endif
 516
 517 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 518 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 519
 520 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 521
 522 /*
 523  * Miscellaneous configurable options
 524  */
 525 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 526 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 527 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 528
 529 #if defined(CONFIG_CMD_KGDB)
 530         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 531 #else
 532         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 533 #endif
 534
 535 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 536 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 537 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 538 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 539
 540 /*
 541  * For booting Linux, the board info and command line data
 542  * have to be in the first 256 MB of memory, since this is
 543  * the maximum mapped by the Linux kernel during initialization.
 544  */
 545 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20) /* Initial Memory map for Linux */
 546
 547 /*
 548  * Core HID Setup
 549  */
 550 #define CONFIG_SYS_HID0_INIT    0x000000000
 551 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 552                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 553                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 554 #define CONFIG_SYS_HID2         HID2_HBE
 555
 556 /*
 557  * MMU Setup
 558  */
 559 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 560
 561 /* DDR: cache cacheable */
 562 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 563 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 564 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 565 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 566
 567 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 568 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 569                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 570 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
 571 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 572 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 573
 574 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 575 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 576 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
 577                                  BATU_VS | BATU_VP)
 578 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 579                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 580 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 581
 582 /* Stack in dcache: cacheable, no memory coherence */
 583 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 584 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 585 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 586 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 587
 588 /* PCI MEM space: cacheable */
 589 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 590 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 591 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 592 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 593
 594 /* PCI MMIO space: cache-inhibit and guarded */
 595 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 596                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 597 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 598 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 599 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 600
 601 #define CONFIG_SYS_IBAT6L       0
 602 #define CONFIG_SYS_IBAT6U       0
 603 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 604 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 605
 606 #define CONFIG_SYS_IBAT7L       0
 607 #define CONFIG_SYS_IBAT7U       0
 608 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 609 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 610
 611 #if defined(CONFIG_CMD_KGDB)
 612 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 613 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 614 #endif
 615
 616 /*
 617  * Environment Configuration
 618  */
 619
 620 #define CONFIG_ENV_OVERWRITE
 621
 622 #if defined(CONFIG_TSEC_ENET)
 623 #define CONFIG_HAS_ETH0
 624 #define CONFIG_HAS_ETH1
 625 #endif
 626
 627 #define CONFIG_BAUDRATE 115200
 628
 629 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 630
 631 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 632 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 633
 634 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 635    "netdev=eth0\0"                                                      \
 636    "consoledev=ttyS0\0"                                                 \
 637    "ramdiskaddr=1000000\0"                                              \
 638    "ramdiskfile=ramfs.83xx\0"                                           \
 639    "fdtaddr=780000\0"                                                   \
 640    "fdtfile=mpc8315erdb.dtb\0"                                          \
 641    "usb_phy_type=utmi\0"                                                \
 642    ""
 643
 644 #define CONFIG_NFSBOOTCOMMAND                                           \
 645    "setenv bootargs root=/dev/nfs rw "                                  \
 646       "nfsroot=$serverip:$rootpath "                                    \
 647       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 648       "console=$consoledev,$baudrate $othbootargs;"                     \
 649    "tftp $loadaddr $bootfile;"                                          \
 650    "tftp $fdtaddr $fdtfile;"                                            \
 651    "bootm $loadaddr - $fdtaddr"
 652
 653 #define CONFIG_RAMBOOTCOMMAND                                           \
 654    "setenv bootargs root=/dev/ram rw "                                  \
 655       "console=$consoledev,$baudrate $othbootargs;"                     \
 656    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 657    "tftp $loadaddr $bootfile;"                                          \
 658    "tftp $fdtaddr $fdtfile;"                                            \
 659    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 660
 661
 662 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 663
 664 #endif  /* __CONFIG_H */