include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  18 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
  19
  20 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  21
  22 #define CONFIG_PCI              1
  23
  24 /*
  25  * System Clock Setup
  26  */
  27 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  28
  29 #ifndef CONFIG_SYS_CLK_FREQ
  30 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  31 #endif
  32
  33 /*
  34  * Hardware Reset Configuration Word
  35  */
  36 #define CONFIG_SYS_HRCW_LOW (\
  37         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  38         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  39         HRCWL_VCO_1X2 |\
  40         HRCWL_CSB_TO_CLKIN_2X1 |\
  41         HRCWL_CORE_TO_CSB_2_5X1 |\
  42         HRCWL_CE_PLL_VCO_DIV_2 |\
  43         HRCWL_CE_PLL_DIV_1X1 |\
  44         HRCWL_CE_TO_PLL_1X3)
  45
  46 #define CONFIG_SYS_HRCW_HIGH (\
  47         HRCWH_PCI_HOST |\
  48         HRCWH_PCI1_ARBITER_ENABLE |\
  49         HRCWH_CORE_ENABLE |\
  50         HRCWH_FROM_0X00000100 |\
  51         HRCWH_BOOTSEQ_DISABLE |\
  52         HRCWH_SW_WATCHDOG_DISABLE |\
  53         HRCWH_ROM_LOC_LOCAL_16BIT |\
  54         HRCWH_BIG_ENDIAN |\
  55         HRCWH_LALE_NORMAL)
  56
  57 /*
  58  * System IO Config
  59  */
  60 #define CONFIG_SYS_SICRL                0x00000000
  61
  62 /*
  63  * IMMR new address
  64  */
  65 #define CONFIG_SYS_IMMR         0xE0000000
  66
  67 /*
  68  * System performance
  69  */
  70 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  71 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  72 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  73 #define CONFIG_SYS_SPCR_OPT     1
  74
  75 /*
  76  * DDR Setup
  77  */
  78 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  79 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  82
  83 #undef CONFIG_SPD_EEPROM
  84 #if defined(CONFIG_SPD_EEPROM)
  85 /* Determine DDR configuration from I2C interface
  86  */
  87 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  88 #else
  89 /* Manually set up DDR parameters
  90  */
  91 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  92 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  93                                 | CSCONFIG_ODT_WR_ACS \
  94                                 | CSCONFIG_ROW_BIT_13 \
  95                                 | CSCONFIG_COL_BIT_9)
  96                                 /* 0x80010101 */
  97 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  98                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  99                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 100                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 101                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 102                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 103                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 104                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 105                                 /* 0x00220802 */
 106 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 107                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 108                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 109                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 110                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
 111                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 112                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 113                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 114                                 /* 0x26253222 */
 115 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 116                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 117                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 118                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 119                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 120                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 121                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 122                                 /* 0x1f9048c7 */
 123 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 124 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 125                                 /* 0x02000000 */
 126 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 127                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 128                                 /* 0x44480232 */
 129 #define CONFIG_SYS_DDR_MODE2    0x8000c000
 130 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 131                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 132                                 /* 0x03200064 */
 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
 134 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 135                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 136                                 | SDRAM_CFG_32_BE)
 137                                 /* 0x43080000 */
 138 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 139 #endif
 140
 141 /*
 142  * Memory test
 143  */
 144 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 145 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 146 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 147
 148 /*
 149  * The reserved memory
 150  */
 151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 152
 153 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 154 #define CONFIG_SYS_RAMBOOT
 155 #else
 156 #undef  CONFIG_SYS_RAMBOOT
 157 #endif
 158
 159 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 160 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
 161 #define CONFIG_SYS_MALLOC_LEN   (128 * 1024)    /* Reserved for malloc */
 162
 163 /*
 164  * Initial RAM Base Address Setup
 165  */
 166 #define CONFIG_SYS_INIT_RAM_LOCK        1
 167 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 168 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 170                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 171
 172 /*
 173  * Local Bus Configuration & Clock Setup
 174  */
 175 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 176 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 177 #define CONFIG_SYS_LBC_LBCR             0x00000000
 178
 179 /*
 180  * FLASH on the Local Bus
 181  */
 182 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 183 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 184 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 185 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 186 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 187
 188                                         /* Window base at flash base */
 189 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 190 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018      /* 32MB window size */
 191
 192 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 193                                 | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
 194                                 | BR_V)                 /* valid */
 195 #define CONFIG_SYS_OR0_PRELIM   0xfe006ff7              /* 16MB Flash size */
 196
 197 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 199
 200 #undef CONFIG_SYS_FLASH_CHECKSUM
 201
 202 /*
 203  * SDRAM on the Local Bus
 204  */
 205 #undef CONFIG_SYS_LB_SDRAM      /* The board has not SRDAM on local bus */
 206
 207 #ifdef CONFIG_SYS_LB_SDRAM
 208 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base addr */
 209 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 210
 211 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 212 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019      /* 64MB */
 213
 214 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 215 /*
 216  * Base Register 2 and Option Register 2 configure SDRAM.
 217  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 218  *
 219  * For BR2, need:
 220  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 221  *    port size = 32-bits = BR2[19:20] = 11
 222  *    no parity checking = BR2[21:22] = 00
 223  *    SDRAM for MSEL = BR2[24:26] = 011
 224  *    Valid = BR[31] = 1
 225  *
 226  * 0    4    8    12   16   20   24   28
 227  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 228  *
 229  * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 230  * the top 17 bits of BR2.
 231  */
 232
 233                                 /*Port size=32bit, MSEL=SDRAM */
 234 #define CONFIG_SYS_BR2_PRELIM   0xf0001861
 235
 236 /*
 237  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 238  *
 239  * For OR2, need:
 240  *    64MB mask for AM, OR2[0:7] = 1111 1100
 241  *                 XAM, OR2[17:18] = 11
 242  *    9 columns OR2[19-21] = 010
 243  *    13 rows   OR2[23-25] = 100
 244  *    EAD set for extra time OR[31] = 1
 245  *
 246  * 0    4    8    12   16   20   24   28
 247  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 248  */
 249
 250 #define CONFIG_SYS_OR2_PRELIM   0xfc006901
 251
 252                                 /* LB sdram refresh timer, about 6us */
 253 #define CONFIG_SYS_LBC_LSRT     0x32000000
 254                                 /* LB refresh timer prescal, 266MHz/32 */
 255 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 256
 257 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 258
 259 #endif
 260
 261 /*
 262  * Windows to access PIB via local bus
 263  */
 264                                         /* windows base 0xf8008000 */
 265 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xf8008000
 266 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000f      /* windows size 64KB */
 267
 268 /*
 269  * Serial Port
 270  */
 271 #define CONFIG_CONS_INDEX       1
 272 #define CONFIG_SYS_NS16550
 273 #define CONFIG_SYS_NS16550_SERIAL
 274 #define CONFIG_SYS_NS16550_REG_SIZE     1
 275 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 276
 277 #define CONFIG_SYS_BAUDRATE_TABLE  \
 278                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 279
 280 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 281 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 282
 283 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 284 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 285 /* Use the HUSH parser */
 286 #define CONFIG_SYS_HUSH_PARSER
 287 #ifdef CONFIG_SYS_HUSH_PARSER
 288 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 289 #endif
 290
 291 /* pass open firmware flat tree */
 292 #define CONFIG_OF_LIBFDT        1
 293 #define CONFIG_OF_BOARD_SETUP   1
 294 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 295
 296 /* I2C */
 297 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 298 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 299 #define CONFIG_FSL_I2C
 300 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 301 #define CONFIG_SYS_I2C_SLAVE    0x7F
 302 #define CONFIG_SYS_I2C_NOPROBES {0x51}  /* Don't probe these addrs */
 303 #define CONFIG_SYS_I2C_OFFSET   0x3000
 304
 305 /*
 306  * Config on-board EEPROM
 307  */
 308 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 309 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 310 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 311 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 312
 313 /*
 314  * General PCI
 315  * Addresses are mapped 1-1.
 316  */
 317 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 318 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 319 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 320 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 321 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 322 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 323 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 324 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 325 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 326
 327 #ifdef CONFIG_PCI
 328 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 329 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 330
 331 #undef CONFIG_EEPRO100
 332 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 333 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 334
 335 #endif  /* CONFIG_PCI */
 336
 337 /*
 338  * QE UEC ethernet configuration
 339  */
 340 #define CONFIG_UEC_ETH
 341 #define CONFIG_ETHPRIME         "UEC0"
 342
 343 #define CONFIG_UEC_ETH1         /* ETH3 */
 344
 345 #ifdef CONFIG_UEC_ETH1
 346 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 347 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 348 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 349 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 350 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 351 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 352 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 353 #endif
 354
 355 #define CONFIG_UEC_ETH2         /* ETH4 */
 356
 357 #ifdef CONFIG_UEC_ETH2
 358 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 359 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 360 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 361 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 362 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 363 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 364 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 365 #endif
 366
 367 /*
 368  * Environment
 369  */
 370 #ifndef CONFIG_SYS_RAMBOOT
 371         #define CONFIG_ENV_IS_IN_FLASH  1
 372         #define CONFIG_ENV_ADDR         \
 373                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 374         #define CONFIG_ENV_SECT_SIZE    0x20000
 375         #define CONFIG_ENV_SIZE         0x2000
 376 #else
 377         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 378         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 379         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 380         #define CONFIG_ENV_SIZE         0x2000
 381 #endif
 382
 383 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 384 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 385
 386 /*
 387  * BOOTP options
 388  */
 389 #define CONFIG_BOOTP_BOOTFILESIZE
 390 #define CONFIG_BOOTP_BOOTPATH
 391 #define CONFIG_BOOTP_GATEWAY
 392 #define CONFIG_BOOTP_HOSTNAME
 393
 394 /*
 395  * Command line configuration.
 396  */
 397 #include <config_cmd_default.h>
 398
 399 #define CONFIG_CMD_PING
 400 #define CONFIG_CMD_I2C
 401 #define CONFIG_CMD_EEPROM
 402 #define CONFIG_CMD_ASKENV
 403
 404 #if defined(CONFIG_PCI)
 405         #define CONFIG_CMD_PCI
 406 #endif
 407 #if defined(CONFIG_SYS_RAMBOOT)
 408         #undef CONFIG_CMD_SAVEENV
 409         #undef CONFIG_CMD_LOADS
 410 #endif
 411
 412 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 413
 414 /*
 415  * Miscellaneous configurable options
 416  */
 417 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 418 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 419 #define CONFIG_SYS_PROMPT       "=> "   /* Monitor Command Prompt */
 420
 421 #if (CONFIG_CMD_KGDB)
 422         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 423 #else
 424         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 425 #endif
 426
 427                                 /* Print Buffer Size */
 428 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 429 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 430                                 /* Boot Argument Buffer Size */
 431 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 432 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 433
 434 /*
 435  * For booting Linux, the board info and command line data
 436  * have to be in the first 256 MB of memory, since this is
 437  * the maximum mapped by the Linux kernel during initialization.
 438  */
 439                                         /* Initial Memory map for Linux */
 440 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 441
 442 /*
 443  * Core HID Setup
 444  */
 445 #define CONFIG_SYS_HID0_INIT    0x000000000
 446 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 447                                  HID0_ENABLE_INSTRUCTION_CACHE)
 448 #define CONFIG_SYS_HID2         HID2_HBE
 449
 450 /*
 451  * MMU Setup
 452  */
 453 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 454
 455 /* DDR: cache cacheable */
 456 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 457                                 | BATL_PP_10 \
 458                                 | BATL_MEMCOHERENCE)
 459 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 460                                 | BATU_BL_256M \
 461                                 | BATU_VS \
 462                                 | BATU_VP)
 463 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 464 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 465
 466 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 467 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 468                                 | BATL_PP_10 \
 469                                 | BATL_CACHEINHIBIT \
 470                                 | BATL_GUARDEDSTORAGE)
 471 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 472                                 | BATU_BL_4M \
 473                                 | BATU_VS \
 474                                 | BATU_VP)
 475 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 476 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 477
 478 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 479 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 480                                 | BATL_PP_10 \
 481                                 | BATL_MEMCOHERENCE)
 482 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 483                                 | BATU_BL_32M \
 484                                 | BATU_VS \
 485                                 | BATU_VP)
 486 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 487                                 | BATL_PP_10 \
 488                                 | BATL_CACHEINHIBIT \
 489                                 | BATL_GUARDEDSTORAGE)
 490 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 491
 492 #define CONFIG_SYS_IBAT3L       (0)
 493 #define CONFIG_SYS_IBAT3U       (0)
 494 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 495 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 496
 497 /* Stack in dcache: cacheable, no memory coherence */
 498 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 499 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 500                                 | BATU_BL_128K \
 501                                 | BATU_VS \
 502                                 | BATU_VP)
 503 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 504 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 505
 506 #ifdef CONFIG_PCI
 507 /* PCI MEM space: cacheable */
 508 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
 509                                 | BATL_PP_10 \
 510                                 | BATL_MEMCOHERENCE)
 511 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
 512                                 | BATU_BL_256M \
 513                                 | BATU_VS \
 514                                 | BATU_VP)
 515 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 516 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 517 /* PCI MMIO space: cache-inhibit and guarded */
 518 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 519                                 | BATL_PP_10 \
 520                                 | BATL_CACHEINHIBIT \
 521                                 | BATL_GUARDEDSTORAGE)
 522 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 523                                 | BATU_BL_256M \
 524                                 | BATU_VS \
 525                                 | BATU_VP)
 526 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 527 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 528 #else
 529 #define CONFIG_SYS_IBAT5L       (0)
 530 #define CONFIG_SYS_IBAT5U       (0)
 531 #define CONFIG_SYS_IBAT6L       (0)
 532 #define CONFIG_SYS_IBAT6U       (0)
 533 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 534 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 535 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 536 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 537 #endif
 538
 539 /* Nothing in BAT7 */
 540 #define CONFIG_SYS_IBAT7L       (0)
 541 #define CONFIG_SYS_IBAT7U       (0)
 542 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 543 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 544
 545 #if (CONFIG_CMD_KGDB)
 546 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 547 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 548 #endif
 549
 550 /*
 551  * Environment Configuration
 552  */
 553 #define CONFIG_ENV_OVERWRITE
 554
 555 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 556 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 557
 558 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 559  * (see CONFIG_SYS_I2C_EEPROM) */
 560                                         /* MAC address offset in I2C EEPROM */
 561 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 562
 563 #define CONFIG_NETDEV           "eth1"
 564
 565 #define CONFIG_HOSTNAME         mpc8323erdb
 566 #define CONFIG_ROOTPATH         "/nfsroot"
 567 #define CONFIG_BOOTFILE         "uImage"
 568                                 /* U-Boot image on TFTP server */
 569 #define CONFIG_UBOOTPATH        "u-boot.bin"
 570 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 571 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 572
 573                                 /* default location for tftp and bootm */
 574 #define CONFIG_LOADADDR         800000
 575 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 576 #define CONFIG_BAUDRATE         115200
 577
 578 #define XMK_STR(x)      #x
 579 #define MK_STR(x)       XMK_STR(x)
 580
 581 #define CONFIG_EXTRA_ENV_SETTINGS \
 582         "netdev=" CONFIG_NETDEV "\0"                                    \
 583         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 584         "tftpflash=tftp $loadaddr $uboot;"                              \
 585                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
 586                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "   \
 587                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
 588                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
 589                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
 590         "fdtaddr=780000\0"                                              \
 591         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 592         "ramdiskaddr=1000000\0"                                         \
 593         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 594         "console=ttyS0\0"                                               \
 595         "setbootargs=setenv bootargs "                                  \
 596                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 597         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 598                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 599                                                                 "$netdev:off "\
 600                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 601
 602 #define CONFIG_NFSBOOTCOMMAND                                           \
 603         "setenv rootdev /dev/nfs;"                                      \
 604         "run setbootargs;"                                              \
 605         "run setipargs;"                                                \
 606         "tftp $loadaddr $bootfile;"                                     \
 607         "tftp $fdtaddr $fdtfile;"                                       \
 608         "bootm $loadaddr - $fdtaddr"
 609
 610 #define CONFIG_RAMBOOTCOMMAND                                           \
 611         "setenv rootdev /dev/ram;"                                      \
 612         "run setbootargs;"                                              \
 613         "tftp $ramdiskaddr $ramdiskfile;"                               \
 614         "tftp $loadaddr $bootfile;"                                     \
 615         "tftp $fdtaddr $fdtfile;"                                       \
 616         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 617
 618 #undef MK_STR
 619 #undef XMK_STR
 620
 621 #endif  /* __CONFIG_H */