include/configs/MPC8349ITX.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
  25
  26  Memory map:
  27
  28  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  29  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  30  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  31  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  32  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  33  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  34  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  35  0xF001_0000-0xF001_FFFF Local bus expansion slot
  36  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  37  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  38  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  39
  40  I2C address list:
  41                                                 Align.  Board
  42  Bus    Addr    Part No.        Description     Length  Location
  43  ----------------------------------------------------------------
  44  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  45
  46  I2C1   0x20    PCF8574         I2C Expander    0       U8
  47  I2C1   0x21    PCF8574         I2C Expander    0       U10
  48  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  49  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  50  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  51  I2C1   0x68    DS1339          RTC             1       U68
  52
  53  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  54 */
  55
  56 #ifndef __CONFIG_H
  57 #define __CONFIG_H
  58
  59 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  60 #define CONFIG_SYS_LOWBOOT
  61 #endif
  62
  63 /*
  64  * High Level Configuration Options
  65  */
  66 #define CONFIG_MPC83xx          1
  67 #define CONFIG_MPC834x          /* MPC834x family (8343, 8347, 8349) */
  68 #define CONFIG_MPC8349          /* MPC8349 specific */
  69
  70 #ifndef CONFIG_SYS_TEXT_BASE
  71 #define CONFIG_SYS_TEXT_BASE    0xFEF00000
  72 #endif
  73
  74 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  75
  76 #define CONFIG_MISC_INIT_F
  77 #define CONFIG_MISC_INIT_R
  78
  79 /*
  80  * On-board devices
  81  */
  82
  83 #ifdef CONFIG_MPC8349ITX
  84 /* The CF card interface on the back of the board */
  85 #define CONFIG_COMPACT_FLASH
  86 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  87 #define CONFIG_SATA_SIL3114     /* SIL3114 SATA controller */
  88 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  89 #endif
  90
  91 #define CONFIG_PCI
  92 #define CONFIG_RTC_DS1337
  93 #define CONFIG_HARD_I2C
  94 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  95
  96 /*
  97  * Device configurations
  98  */
  99
 100 /* I2C */
 101 #ifdef CONFIG_HARD_I2C
 102
 103 #define CONFIG_FSL_I2C
 104 #define CONFIG_I2C_MULTI_BUS
 105 #define CONFIG_SYS_I2C_OFFSET           0x3000
 106 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 107 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
 108 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
 109
 110 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
 111 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
 112 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
 113 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
 114 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
 115 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
 116 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
 117
 118 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 119 #define CONFIG_SYS_I2C_SLAVE    0x7F
 120
 121 /* Don't probe these addresses: */
 122 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
 123                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
 124                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
 125                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
 126 /* Bit definitions for the 8574[A] I2C expander */
 127                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 128 #define I2C_8574_REVISION       0x03
 129 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
 130 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
 131 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
 132 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 133
 134 #undef CONFIG_SOFT_I2C
 135
 136 #endif
 137
 138 /* Compact Flash */
 139 #ifdef CONFIG_COMPACT_FLASH
 140
 141 #define CONFIG_SYS_IDE_MAXBUS           1
 142 #define CONFIG_SYS_IDE_MAXDEVICE        1
 143
 144 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 145 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 146 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 147 #define CONFIG_SYS_ATA_REG_OFFSET       0
 148 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 149 #define CONFIG_SYS_ATA_STRIDE           2
 150
 151 /* If a CF card is not inserted, time out quickly */
 152 #define ATA_RESET_TIME  1
 153
 154 #endif
 155
 156 /*
 157  * SATA
 158  */
 159 #ifdef CONFIG_SATA_SIL3114
 160
 161 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 162 #define CONFIG_LIBATA
 163 #define CONFIG_LBA48
 164
 165 #endif
 166
 167 #ifdef CONFIG_SYS_USB_HOST
 168 /*
 169  * Support USB
 170  */
 171 #define CONFIG_CMD_USB
 172 #define CONFIG_USB_STORAGE
 173 #define CONFIG_USB_EHCI
 174 #define CONFIG_USB_EHCI_FSL
 175
 176 /* Current USB implementation supports the only USB controller,
 177  * so we have to choose between the MPH or the DR ones */
 178 #if 1
 179 #define CONFIG_HAS_FSL_MPH_USB
 180 #else
 181 #define CONFIG_HAS_FSL_DR_USB
 182 #endif
 183
 184 #endif
 185
 186 /*
 187  * DDR Setup
 188  */
 189 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 190 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 191 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 192 #define CONFIG_SYS_83XX_DDR_USES_CS0
 193 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 194 #define CONFIG_SYS_MEMTEST_END          0x2000
 195
 196 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 197                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 198
 199 #define CONFIG_VERY_BIG_RAM
 200 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 201
 202 #ifdef CONFIG_HARD_I2C
 203 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 204 #endif
 205
 206 /* No SPD? Then manually set up DDR parameters */
 207 #ifndef CONFIG_SPD_EEPROM
 208     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 209     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 210                                         | CSCONFIG_ROW_BIT_13 \
 211                                         | CSCONFIG_COL_BIT_10)
 212
 213     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 214     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 215 #endif
 216
 217 /*
 218  *Flash on the Local Bus
 219  */
 220
 221 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 222 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 223 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 224 #define CONFIG_SYS_FLASH_EMPTY_INFO
 225 /* 127 64KB sectors + 8 8KB sectors per device */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       135
 227 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 228 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 229 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 230
 231 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 232 boards, we say we have two, but don't display a message if we find only one. */
 233 #define CONFIG_SYS_FLASH_QUIET_TEST
 234 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 235 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 236                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 237 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 238 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 239
 240 /* Vitesse 7385 */
 241
 242 #ifdef CONFIG_VSC7385_ENET
 243
 244 #define CONFIG_TSEC2
 245
 246 /* The flash address and size of the VSC7385 firmware image */
 247 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 248 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 249
 250 #endif
 251
 252 /*
 253  * BRx, ORx, LBLAWBARx, and LBLAWARx
 254  */
 255
 256 /* Flash */
 257
 258 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 259                                 | BR_PS_16 \
 260                                 | BR_MS_GPCM \
 261                                 | BR_V)
 262 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 263                                 | OR_UPM_XAM \
 264                                 | OR_GPCM_CSNT \
 265                                 | OR_GPCM_ACS_DIV2 \
 266                                 | OR_GPCM_XACS \
 267                                 | OR_GPCM_SCY_15 \
 268                                 | OR_GPCM_TRLX_SET \
 269                                 | OR_GPCM_EHTR_SET \
 270                                 | OR_GPCM_EAD)
 271 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 272 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 273
 274 /* Vitesse 7385 */
 275
 276 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 277
 278 #ifdef CONFIG_VSC7385_ENET
 279
 280 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 281                                 | BR_PS_8 \
 282                                 | BR_MS_GPCM \
 283                                 | BR_V)
 284 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 285                                 | OR_GPCM_CSNT \
 286                                 | OR_GPCM_XACS \
 287                                 | OR_GPCM_SCY_15 \
 288                                 | OR_GPCM_SETA \
 289                                 | OR_GPCM_TRLX_SET \
 290                                 | OR_GPCM_EHTR_SET \
 291                                 | OR_GPCM_EAD)
 292
 293 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 294 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 295
 296 #endif
 297
 298 /* LED */
 299
 300 #define CONFIG_SYS_LED_BASE     0xF9000000
 301 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 302                                 | BR_PS_8 \
 303                                 | BR_MS_GPCM \
 304                                 | BR_V)
 305 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 306                                 | OR_GPCM_CSNT \
 307                                 | OR_GPCM_ACS_DIV2 \
 308                                 | OR_GPCM_XACS \
 309                                 | OR_GPCM_SCY_9 \
 310                                 | OR_GPCM_TRLX_SET \
 311                                 | OR_GPCM_EHTR_SET \
 312                                 | OR_GPCM_EAD)
 313
 314 /* Compact Flash */
 315
 316 #ifdef CONFIG_COMPACT_FLASH
 317
 318 #define CONFIG_SYS_CF_BASE      0xF0000000
 319
 320 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 321                                 | BR_PS_16 \
 322                                 | BR_MS_UPMA \
 323                                 | BR_V)
 324 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 325
 326 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 327 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 328
 329 #endif
 330
 331 /*
 332  * U-Boot memory configuration
 333  */
 334 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 335
 336 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 337 #define CONFIG_SYS_RAMBOOT
 338 #else
 339 #undef  CONFIG_SYS_RAMBOOT
 340 #endif
 341
 342 #define CONFIG_SYS_INIT_RAM_LOCK
 343 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 344 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 345
 346 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 347                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 348 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 349
 350 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 351 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 352 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 353
 354 /*
 355  * Local Bus LCRR and LBCR regs
 356  *    LCRR:  DLL bypass, Clock divider is 4
 357  * External Local Bus rate is
 358  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 359  */
 360 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 361 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 362 #define CONFIG_SYS_LBC_LBCR     0x00000000
 363
 364                                 /* LB sdram refresh timer, about 6us */
 365 #define CONFIG_SYS_LBC_LSRT     0x32000000
 366                                 /* LB refresh timer prescal, 266MHz/32*/
 367 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 368
 369 /*
 370  * Serial Port
 371  */
 372 #define CONFIG_CONS_INDEX       1
 373 #define CONFIG_SYS_NS16550
 374 #define CONFIG_SYS_NS16550_SERIAL
 375 #define CONFIG_SYS_NS16550_REG_SIZE     1
 376 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 377
 378 #define CONFIG_SYS_BAUDRATE_TABLE  \
 379                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 380
 381 #define CONFIG_CONSOLE          ttyS0
 382 #define CONFIG_BAUDRATE         115200
 383
 384 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 385 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 386
 387 /* pass open firmware flat tree */
 388 #define CONFIG_OF_LIBFDT        1
 389 #define CONFIG_OF_BOARD_SETUP   1
 390 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 391
 392 /*
 393  * PCI
 394  */
 395 #ifdef CONFIG_PCI
 396 #define CONFIG_PCI_INDIRECT_BRIDGE
 397
 398 #define CONFIG_MPC83XX_PCI2
 399
 400 /*
 401  * General PCI
 402  * Addresses are mapped 1-1.
 403  */
 404 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 405 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 406 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 407 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 408                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 409 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 410 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 411 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 412 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 413 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 414
 415 #ifdef CONFIG_MPC83XX_PCI2
 416 #define CONFIG_SYS_PCI2_MEM_BASE        \
 417                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 418 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 419 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 420 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 421                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 422 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 423 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 424 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 425 #define CONFIG_SYS_PCI2_IO_PHYS         \
 426                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 427 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 428 #endif
 429
 430 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 431
 432 #ifndef CONFIG_PCI_PNP
 433     #define PCI_ENET0_IOADDR    0x00000000
 434     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 435     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 436 #endif
 437
 438 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 439
 440 #endif
 441
 442 #define CONFIG_PCI_66M
 443 #ifdef CONFIG_PCI_66M
 444 #define CONFIG_83XX_CLKIN       66666666        /* in Hz */
 445 #else
 446 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
 447 #endif
 448
 449 /* TSEC */
 450
 451 #ifdef CONFIG_TSEC_ENET
 452
 453 #define CONFIG_MII
 454 #define CONFIG_PHY_GIGE         /* In case CONFIG_CMD_MII is specified */
 455
 456 #define CONFIG_TSEC1
 457
 458 #ifdef CONFIG_TSEC1
 459 #define CONFIG_HAS_ETH0
 460 #define CONFIG_TSEC1_NAME  "TSEC0"
 461 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 462 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 463 #define TSEC1_PHYIDX            0
 464 #define TSEC1_FLAGS             TSEC_GIGABIT
 465 #endif
 466
 467 #ifdef CONFIG_TSEC2
 468 #define CONFIG_HAS_ETH1
 469 #define CONFIG_TSEC2_NAME  "TSEC1"
 470 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 471
 472 #define TSEC2_PHY_ADDR          4
 473 #define TSEC2_PHYIDX            0
 474 #define TSEC2_FLAGS             TSEC_GIGABIT
 475 #endif
 476
 477 #define CONFIG_ETHPRIME         "Freescale TSEC"
 478
 479 #endif
 480
 481 /*
 482  * Environment
 483  */
 484 #define CONFIG_ENV_OVERWRITE
 485
 486 #ifndef CONFIG_SYS_RAMBOOT
 487   #define CONFIG_ENV_IS_IN_FLASH
 488   #define CONFIG_ENV_ADDR       \
 489                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 490   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 491   #define CONFIG_ENV_SIZE       0x2000
 492 #else
 493   #define CONFIG_SYS_NO_FLASH   /* Flash is not usable now */
 494   #undef  CONFIG_FLASH_CFI_DRIVER
 495   #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
 496   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 497   #define CONFIG_ENV_SIZE       0x2000
 498 #endif
 499
 500 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 501 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 502
 503 /*
 504  * BOOTP options
 505  */
 506 #define CONFIG_BOOTP_BOOTFILESIZE
 507 #define CONFIG_BOOTP_BOOTPATH
 508 #define CONFIG_BOOTP_GATEWAY
 509 #define CONFIG_BOOTP_HOSTNAME
 510
 511
 512 /*
 513  * Command line configuration.
 514  */
 515 #include <config_cmd_default.h>
 516
 517 #define CONFIG_CMD_CACHE
 518 #define CONFIG_CMD_DATE
 519 #define CONFIG_CMD_IRQ
 520 #define CONFIG_CMD_NET
 521 #define CONFIG_CMD_PING
 522 #define CONFIG_CMD_DHCP
 523 #define CONFIG_CMD_SDRAM
 524
 525 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
 526                                 || defined(CONFIG_USB_STORAGE)
 527         #define CONFIG_DOS_PARTITION
 528         #define CONFIG_CMD_FAT
 529         #define CONFIG_SUPPORT_VFAT
 530 #endif
 531
 532 #ifdef CONFIG_COMPACT_FLASH
 533         #define CONFIG_CMD_IDE
 534 #endif
 535
 536 #ifdef CONFIG_SATA_SIL3114
 537         #define CONFIG_CMD_SATA
 538 #endif
 539
 540 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
 541         #define CONFIG_CMD_EXT2
 542 #endif
 543
 544 #ifdef CONFIG_PCI
 545         #define CONFIG_CMD_PCI
 546 #endif
 547
 548 #ifdef CONFIG_HARD_I2C
 549         #define CONFIG_CMD_I2C
 550 #endif
 551
 552 /* Watchdog */
 553 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 554
 555 /*
 556  * Miscellaneous configurable options
 557  */
 558 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 559 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 560 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 561 #define CONFIG_SYS_HUSH_PARSER          /* Use the HUSH parser */
 562
 563 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 564 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 565
 566 #ifdef CONFIG_MPC8349ITX
 567 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> "     /* Monitor Command Prompt */
 568 #else
 569 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> "  /* Monitor Command Prompt */
 570 #endif
 571
 572 #if defined(CONFIG_CMD_KGDB)
 573         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 574 #else
 575         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 576 #endif
 577
 578                                 /* Print Buffer Size */
 579 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 580 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 581                                 /* Boot Argument Buffer Size */
 582 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 583 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 584
 585 /*
 586  * For booting Linux, the board info and command line data
 587  * have to be in the first 256 MB of memory, since this is
 588  * the maximum mapped by the Linux kernel during initialization.
 589  */
 590                                 /* Initial Memory map for Linux*/
 591 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 592
 593 #define CONFIG_SYS_HRCW_LOW (\
 594         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 595         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 596         HRCWL_CSB_TO_CLKIN_4X1 |\
 597         HRCWL_VCO_1X2 |\
 598         HRCWL_CORE_TO_CSB_2X1)
 599
 600 #ifdef CONFIG_SYS_LOWBOOT
 601 #define CONFIG_SYS_HRCW_HIGH (\
 602         HRCWH_PCI_HOST |\
 603         HRCWH_32_BIT_PCI |\
 604         HRCWH_PCI1_ARBITER_ENABLE |\
 605         HRCWH_PCI2_ARBITER_ENABLE |\
 606         HRCWH_CORE_ENABLE |\
 607         HRCWH_FROM_0X00000100 |\
 608         HRCWH_BOOTSEQ_DISABLE |\
 609         HRCWH_SW_WATCHDOG_DISABLE |\
 610         HRCWH_ROM_LOC_LOCAL_16BIT |\
 611         HRCWH_TSEC1M_IN_GMII |\
 612         HRCWH_TSEC2M_IN_GMII)
 613 #else
 614 #define CONFIG_SYS_HRCW_HIGH (\
 615         HRCWH_PCI_HOST |\
 616         HRCWH_32_BIT_PCI |\
 617         HRCWH_PCI1_ARBITER_ENABLE |\
 618         HRCWH_PCI2_ARBITER_ENABLE |\
 619         HRCWH_CORE_ENABLE |\
 620         HRCWH_FROM_0XFFF00100 |\
 621         HRCWH_BOOTSEQ_DISABLE |\
 622         HRCWH_SW_WATCHDOG_DISABLE |\
 623         HRCWH_ROM_LOC_LOCAL_16BIT |\
 624         HRCWH_TSEC1M_IN_GMII |\
 625         HRCWH_TSEC2M_IN_GMII)
 626 #endif
 627
 628 /*
 629  * System performance
 630  */
 631 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 632 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 633 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 634 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 635 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 636 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 637 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 638 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 639
 640 /*
 641  * System IO Config
 642  */
 643 /* Needed for gigabit to work on TSEC 1 */
 644 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 645                                 /* USB DR as device + USB MPH as host */
 646 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 647
 648 #define CONFIG_SYS_HID0_INIT    0x00000000
 649 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 650
 651 #define CONFIG_SYS_HID2 HID2_HBE
 652 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 653
 654 /* DDR  */
 655 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 656                                 | BATL_PP_RW \
 657                                 | BATL_MEMCOHERENCE)
 658 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 659                                 | BATU_BL_256M \
 660                                 | BATU_VS \
 661                                 | BATU_VP)
 662
 663 /* PCI  */
 664 #ifdef CONFIG_PCI
 665 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 666                                 | BATL_PP_RW \
 667                                 | BATL_MEMCOHERENCE)
 668 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 669                                 | BATU_BL_256M \
 670                                 | BATU_VS \
 671                                 | BATU_VP)
 672 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 673                                 | BATL_PP_RW \
 674                                 | BATL_CACHEINHIBIT \
 675                                 | BATL_GUARDEDSTORAGE)
 676 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 677                                 | BATU_BL_256M \
 678                                 | BATU_VS \
 679                                 | BATU_VP)
 680 #else
 681 #define CONFIG_SYS_IBAT1L       0
 682 #define CONFIG_SYS_IBAT1U       0
 683 #define CONFIG_SYS_IBAT2L       0
 684 #define CONFIG_SYS_IBAT2U       0
 685 #endif
 686
 687 #ifdef CONFIG_MPC83XX_PCI2
 688 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 689                                 | BATL_PP_RW \
 690                                 | BATL_MEMCOHERENCE)
 691 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 692                                 | BATU_BL_256M \
 693                                 | BATU_VS \
 694                                 | BATU_VP)
 695 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 696                                 | BATL_PP_RW \
 697                                 | BATL_CACHEINHIBIT \
 698                                 | BATL_GUARDEDSTORAGE)
 699 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 700                                 | BATU_BL_256M \
 701                                 | BATU_VS \
 702                                 | BATU_VP)
 703 #else
 704 #define CONFIG_SYS_IBAT3L       0
 705 #define CONFIG_SYS_IBAT3U       0
 706 #define CONFIG_SYS_IBAT4L       0
 707 #define CONFIG_SYS_IBAT4U       0
 708 #endif
 709
 710 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 711 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 712                                 | BATL_PP_RW \
 713                                 | BATL_CACHEINHIBIT \
 714                                 | BATL_GUARDEDSTORAGE)
 715 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 716                                 | BATU_BL_256M \
 717                                 | BATU_VS \
 718                                 | BATU_VP)
 719
 720 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 721 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 722                                 | BATL_PP_RW \
 723                                 | BATL_MEMCOHERENCE \
 724                                 | BATL_GUARDEDSTORAGE)
 725 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 726                                 | BATU_BL_256M \
 727                                 | BATU_VS \
 728                                 | BATU_VP)
 729
 730 #define CONFIG_SYS_IBAT7L       0
 731 #define CONFIG_SYS_IBAT7U       0
 732
 733 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 734 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 735 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 736 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 737 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 738 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 739 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 740 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 741 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 742 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 743 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 744 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 745 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 746 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 747 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 748 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 749
 750 #if defined(CONFIG_CMD_KGDB)
 751 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 752 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 753 #endif
 754
 755
 756 /*
 757  * Environment Configuration
 758  */
 759 #define CONFIG_ENV_OVERWRITE
 760
 761 #define CONFIG_NETDEV           "eth0"
 762
 763 #ifdef CONFIG_MPC8349ITX
 764 #define CONFIG_HOSTNAME         "mpc8349emitx"
 765 #else
 766 #define CONFIG_HOSTNAME         "mpc8349emitxgp"
 767 #endif
 768
 769 /* Default path and filenames */
 770 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 771 #define CONFIG_BOOTFILE         "uImage"
 772                                 /* U-Boot image on TFTP server */
 773 #define CONFIG_UBOOTPATH        "u-boot.bin"
 774
 775 #ifdef CONFIG_MPC8349ITX
 776 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 777 #else
 778 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 779 #endif
 780
 781 #define CONFIG_BOOTDELAY        6
 782
 783 #define CONFIG_BOOTARGS \
 784         "root=/dev/nfs rw" \
 785         " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH    \
 786         " ip=" __stringify(CONFIG_IPADDR) ":"           \
 787                 __stringify(CONFIG_SERVERIP) ":"        \
 788                 __stringify(CONFIG_GATEWAYIP) ":"       \
 789                 __stringify(CONFIG_NETMASK) ":"         \
 790                 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off"                \
 791         " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
 792
 793 #define CONFIG_EXTRA_ENV_SETTINGS \
 794         "console=" __stringify(CONFIG_CONSOLE) "\0"                     \
 795         "netdev=" CONFIG_NETDEV "\0"                                    \
 796         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 797         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 798                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 799                         " +$filesize; " \
 800                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 801                         " +$filesize; " \
 802                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 803                         " $filesize; "  \
 804                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 805                         " +$filesize; " \
 806                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 807                         " $filesize\0"  \
 808         "fdtaddr=780000\0"                                              \
 809         "fdtfile=" CONFIG_FDTFILE "\0"
 810
 811 #define CONFIG_NFSBOOTCOMMAND                                           \
 812         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 813         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 814         " console=$console,$baudrate $othbootargs; "                    \
 815         "tftp $loadaddr $bootfile;"                                     \
 816         "tftp $fdtaddr $fdtfile;"                                       \
 817         "bootm $loadaddr - $fdtaddr"
 818
 819 #define CONFIG_RAMBOOTCOMMAND                                           \
 820         "setenv bootargs root=/dev/ram rw"                              \
 821         " console=$console,$baudrate $othbootargs; "                    \
 822         "tftp $ramdiskaddr $ramdiskfile;"                               \
 823         "tftp $loadaddr $bootfile;"                                     \
 824         "tftp $fdtaddr $fdtfile;"                                       \
 825         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 826
 827 #endif