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1 /*
2  * (C) Copyright 2003-2004
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * (C) Copyright 2004-2008
6  * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #include <version.h>
15
16 #define CONFIG_MPC5200  1
17
18 #ifndef CONFIG_SYS_TEXT_BASE
19 #define CONFIG_SYS_TEXT_BASE    0xFF800000
20 #endif
21
22 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000
23
24 #define CONFIG_MISC_INIT_R      1
25
26 #define CONFIG_SYS_CACHELINE_SIZE       32
27 #ifdef CONFIG_CMD_KGDB
28 #define CONFIG_SYS_CACHELINE_SHIFT      5
29 #endif
30
31 #define CONFIG_PSC_CONSOLE      1
32 #define CONFIG_BAUDRATE         115200
33 #define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200, 230400}
34
35 #define CONFIG_PCI              1
36 #define CONFIG_PCI_PNP          1
37 #undef  CONFIG_PCI_SCAN_SHOW
38 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
39
40 #define CONFIG_PCI_MEM_BUS      0x40000000
41 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
42 #define CONFIG_PCI_MEM_SIZE     0x10000000
43
44 #define CONFIG_PCI_IO_BUS       0x50000000
45 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
46 #define CONFIG_PCI_IO_SIZE      0x01000000
47
48 #define CONFIG_SYS_XLB_PIPELINING       1
49 #define CONFIG_HIGH_BATS        1
50
51 #define MV_CI                   mvBlueCOUGAR-P
52 #define MV_VCI                  mvBlueCOUGAR-P
53 #define MV_FPGA_DATA            0xff860000
54 #define MV_FPGA_SIZE            0
55 #define MV_KERNEL_ADDR          0xffd00000
56 #define MV_INITRD_ADDR          0xff900000
57 #define MV_INITRD_LENGTH        0x00400000
58 #define MV_SCRATCH_ADDR         0x00000000
59 #define MV_SCRATCH_LENGTH       MV_INITRD_LENGTH
60 #define MV_SCRIPT_ADDR          0xff840000
61 #define MV_SCRIPT_ADDR2         0xff850000
62 #define MV_DTB_ADDR             0xfffc0000
63
64 #define CONFIG_SHOW_BOOT_PROGRESS 1
65
66 #define MV_KERNEL_ADDR_RAM      0x00100000
67 #define MV_DTB_ADDR_RAM         0x00600000
68 #define MV_INITRD_ADDR_RAM      0x01000000
69
70 /* pass open firmware flat tree */
71 #define CONFIG_OF_LIBFDT        1
72 #define CONFIG_OF_BOARD_SETUP   1
73
74 #define OF_CPU                  "PowerPC,5200@0"
75 #define OF_SOC                  "soc5200@f0000000"
76 #define OF_TBCLK                (bd->bi_busfreq / 4)
77 #define MV_DTB_NAME             mvbc-p.dtb
78 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
79
80 /*
81  * Supported commands
82  */
83 #include <config_cmd_default.h>
84
85 #define CONFIG_CMD_CACHE
86 #define CONFIG_CMD_NET
87 #define CONFIG_CMD_PING
88 #define CONFIG_CMD_DHCP
89 #define CONFIG_CMD_SDRAM
90 #define CONFIG_CMD_PCI
91 #define CONFIG_CMD_FPGA
92 #define CONFIG_CMD_I2C
93
94 #undef CONFIG_WATCHDOG
95
96 #define CONFIG_BOOTP_VENDOREX
97 #define CONFIG_BOOTP_SUBNETMASK
98 #define CONFIG_BOOTP_GATEWAY
99 #define CONFIG_BOOTP_DNS
100 #define CONFIG_BOOTP_DNS2
101 #define CONFIG_BOOTP_HOSTNAME
102 #define CONFIG_BOOTP_BOOTFILESIZE
103 #define CONFIG_BOOTP_BOOTPATH
104 #define CONFIG_BOOTP_NTPSERVER
105 #define CONFIG_BOOTP_RANDOM_DELAY
106 #define CONFIG_BOOTP_SEND_HOSTNAME
107
108 /*
109  * Autoboot
110  */
111 #define CONFIG_BOOTDELAY                2
112 #define CONFIG_AUTOBOOT_KEYED
113 #define CONFIG_AUTOBOOT_STOP_STR        "s"
114 #define CONFIG_ZERO_BOOTDELAY_CHECK
115 #define CONFIG_RESET_TO_RETRY           1000
116
117 #define CONFIG_BOOTCOMMAND      "if imi ${script_addr}; \
118                                         then source ${script_addr};     \
119                                         else source ${script_addr2};    \
120                                 fi;"
121
122 #define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs"
123 #define CONFIG_ENV_OVERWRITE
124
125 #define CONFIG_EXTRA_ENV_SETTINGS                               \
126         "console_nr=0\0"                                        \
127         "console=yes\0"                                         \
128         "stdin=serial\0"                                        \
129         "stdout=serial\0"                                       \
130         "stderr=serial\0"                                       \
131         "fpga=0\0"                                              \
132         "fpgadata=" __stringify(MV_FPGA_DATA) "\0"                      \
133         "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"          \
134         "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"         \
135         "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"               \
136         "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"              \
137         "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"      \
138         "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"              \
139         "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"      \
140         "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"  \
141         "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"                    \
142         "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"            \
143         "dtb_name=" __stringify(MV_DTB_NAME) "\0"                       \
144         "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"            \
145         "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"        \
146         "mv_version=" U_BOOT_VERSION "\0"                       \
147         "dhcp_client_id=" __stringify(MV_CI) "\0"                       \
148         "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"        \
149         "netretry=no\0"                                         \
150         "use_static_ipaddr=no\0"                                \
151         "static_ipaddr=192.168.90.10\0"                         \
152         "static_netmask=255.255.255.0\0"                        \
153         "static_gateway=0.0.0.0\0"                              \
154         "initrd_name=uInitrd.mvbc-p-rfs\0"                      \
155         "zcip=no\0"                                             \
156         "netboot=yes\0"                                         \
157         "mvtest=Ff\0"                                           \
158         "tried_bootfromflash=no\0"                              \
159         "tried_bootfromnet=no\0"                                \
160         "use_dhcp=yes\0"                                        \
161         "gev_start=yes\0"                                       \
162         "mvbcdma_debug=0\0"                                     \
163         "mvbcia_debug=0\0"                                      \
164         "propdev_debug=0\0"                                     \
165         "gevss_debug=0\0"                                       \
166         "watchdog=1\0"                                          \
167         "sensor_cnt=1\0"                                        \
168         ""
169
170 /*
171  * IPB Bus clocking configuration.
172  */
173 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
174 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
175
176 /*
177  * Flash configuration
178  */
179 #undef  CONFIG_FLASH_16BIT
180 #define CONFIG_SYS_FLASH_CFI
181 #define CONFIG_FLASH_CFI_DRIVER
182 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
183 #define CONFIG_SYS_FLASH_EMPTY_INFO
184
185 #define CONFIG_SYS_FLASH_ERASE_TOUT     50000
186 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000
187
188 #define CONFIG_SYS_MAX_FLASH_BANKS      1
189 #define CONFIG_SYS_MAX_FLASH_SECT       256
190
191 #define CONFIG_SYS_LOWBOOT
192 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE
193 #define CONFIG_SYS_FLASH_SIZE           0x00800000
194
195 /*
196  * Environment settings
197  */
198 #define CONFIG_ENV_IS_IN_FLASH
199 #undef  CONFIG_SYS_FLASH_PROTECTION
200
201 #define CONFIG_ENV_ADDR         0xFFFE0000
202 #define CONFIG_ENV_SIZE         0x10000
203 #define CONFIG_ENV_SECT_SIZE    0x10000
204 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
205 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
206
207 /*
208  * Memory map
209  */
210 #define CONFIG_SYS_MBAR         0xF0000000
211 #define CONFIG_SYS_SDRAM_BASE           0x00000000
212 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
213
214 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
215 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
216
217 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
218 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
219
220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
221 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
222 #define CONFIG_SYS_RAMBOOT              1
223 #endif
224
225 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
226 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
227 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
228 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
229
230 /*
231  * I2C configuration
232  */
233 #define CONFIG_HARD_I2C         1
234 #define CONFIG_SYS_I2C_MODULE   1
235 #define CONFIG_SYS_I2C_SPEED    86000
236 #define CONFIG_SYS_I2C_SLAVE    0x7F
237
238 /*
239  * Ethernet configuration
240  */
241 #define CONFIG_NET_RETRY_COUNT 5
242
243 #define CONFIG_E1000
244 #define CONFIG_E1000_FALLBACK_MAC       { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
245 #undef CONFIG_MPC5xxx_FEC
246 #undef CONFIG_PHY_ADDR
247 #define CONFIG_NETDEV           eth0
248
249 /*
250  * Miscellaneous configurable options
251  */
252 #define CONFIG_SYS_HUSH_PARSER
253 #define CONFIG_CMDLINE_EDITING
254 #undef  CONFIG_SYS_LONGHELP
255 #ifdef CONFIG_CMD_KGDB
256 #define CONFIG_SYS_CBSIZE               1024
257 #else
258 #define CONFIG_SYS_CBSIZE               256
259 #endif
260 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
261 #define CONFIG_SYS_MAXARGS              16
262 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
263
264 #define CONFIG_SYS_MEMTEST_START        0x00800000
265 #define CONFIG_SYS_MEMTEST_END          0x02f00000
266
267 /* default load address */
268 #define CONFIG_SYS_LOAD_ADDR            0x02000000
269 /* default location for tftp and bootm */
270 #define CONFIG_LOADADDR         0x00200000
271
272 /*
273  * Various low-level settings
274  */
275 #define CONFIG_SYS_GPS_PORT_CONFIG      0x20000004
276
277 #define CONFIG_SYS_HID0_INIT            (HID0_ICE | HID0_ICFI)
278 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
279
280 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
281 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
282 #define CONFIG_SYS_BOOTCS_CFG           0x00047800
283 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
284 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
285
286 #define CONFIG_SYS_CS_BURST             0x000000f0
287 #define CONFIG_SYS_CS_DEADCYCLE 0x33333303
288
289 #define CONFIG_SYS_RESET_ADDRESS        0x00000100
290
291 #undef FPGA_DEBUG
292 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
293 #define CONFIG_FPGA
294 #define CONFIG_FPGA_ALTERA      1
295 #define CONFIG_FPGA_CYCLON2     1
296 #define CONFIG_FPGA_COUNT       1
297
298 #endif