include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the Free
   8  * Software Foundation; either version 2 of the License, or (at your option)
   9  * any later version.
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 /* High Level Configuration Options */
  18 #define CONFIG_BOOKE                    /* BOOKE */
  19 #define CONFIG_E500                     /* BOOKE e500 family */
  20 #define CONFIG_MPC85xx                  /* MPC8540/60/55/41/48 */
  21 #define CONFIG_P1022
  22 #define CONFIG_P1022DS
  23 #define CONFIG_MP                       /* support multiple processors */
  24
  25 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  26 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  27 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
  28 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
  29 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
  30 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  31 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  32 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  33 #define CONFIG_SYS_HAS_SERDES           /* has SERDES */
  34
  35 #define CONFIG_PHYS_64BIT
  36 #define CONFIG_ENABLE_36BIT_PHYS
  37 #define CONFIG_ADDR_MAP
  38 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  39
  40 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  41
  42 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  43 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  44 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  45
  46 /*
  47  * These can be toggled for performance analysis, otherwise use default.
  48  */
  49 #define CONFIG_L2_CACHE
  50 #define CONFIG_BTB
  51
  52 #define CONFIG_SYS_MEMTEST_START        0x00000000
  53 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
  54
  55 /*
  56  * Base addresses -- Note these are effective addresses where the
  57  * actual resources get mapped (not physical addresses)
  58  */
  59 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  60 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  61 #define CONFIG_SYS_CCSRBAR_PHYS         0xfffe00000ull
  62 #define CONFIG_SYS_IMMR                 CONFIG_SYS_CCSRBAR
  63
  64 /* DDR Setup */
  65 #define CONFIG_DDR_SPD
  66 #define CONFIG_VERY_BIG_RAM
  67 #define CONFIG_FSL_DDR3
  68
  69 #ifdef CONFIG_DDR_ECC
  70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  71 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  72 #endif
  73
  74 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  75 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  76
  77 #define CONFIG_NUM_DDR_CONTROLLERS      1
  78 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  79 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  80
  81 /* I2C addresses of SPD EEPROMs */
  82 #define CONFIG_SYS_SPD_BUS_NUM          1
  83 #define SPD_EEPROM_ADDRESS1             0x51    /* CTLR 0 DIMM 0 */
  84
  85 /*
  86  * Memory map
  87  *
  88  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  89  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
  90  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
  91  *
  92  * Localbus cacheable (TBD)
  93  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
  94  *
  95  * Localbus non-cacheable
  96  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
  97  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
  98  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
  99  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 100  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 101  */
 102
 103 /*
 104  * Local Bus Definitions
 105  */
 106 #define CONFIG_SYS_FLASH_BASE           0xe0000000 /* start of FLASH 128M */
 107 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 108
 109 #define CONFIG_FLASH_BR_PRELIM  \
 110         (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
 111 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 112
 113 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 114 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 115
 116 #define CONFIG_SYS_BR1_PRELIM   \
 117         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 118 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM
 119
 120 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 121         {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 122 #define CONFIG_SYS_FLASH_QUIET_TEST
 123 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 124
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 126 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 127
 128 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE       /* start of monitor */
 129
 130 #define CONFIG_FLASH_CFI_DRIVER
 131 #define CONFIG_SYS_FLASH_CFI
 132 #define CONFIG_SYS_FLASH_EMPTY_INFO
 133
 134 #define CONFIG_BOARD_EARLY_INIT_F
 135 #define CONFIG_BOARD_EARLY_INIT_R
 136 #define CONFIG_MISC_INIT_R
 137 #define CONFIG_HWCONFIG
 138
 139 #define CONFIG_FSL_NGPIXIS
 140 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 141 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 142
 143 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 144 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 145
 146 #define PIXIS_LBMAP_SWITCH      7
 147 #define PIXIS_LBMAP_MASK        0xE0
 148 #define PIXIS_LBMAP_ALTBANK     0x20
 149
 150 #define CONFIG_SYS_INIT_RAM_LOCK
 151 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 152 #define CONFIG_SYS_INIT_RAM_END         0x00004000 /* End of used area in RAM */
 153
 154 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 155 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 156         (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 157 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 158
 159 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 160 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
 161
 162 /*
 163  * Serial Port
 164  */
 165 #define CONFIG_CONS_INDEX               1
 166 #define CONFIG_SYS_NS16550
 167 #define CONFIG_SYS_NS16550_SERIAL
 168 #define CONFIG_SYS_NS16550_REG_SIZE     1
 169 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 170
 171 #define CONFIG_SYS_BAUDRATE_TABLE       \
 172         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 173
 174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 176
 177 /* Use the HUSH parser */
 178 #define CONFIG_SYS_HUSH_PARSER
 179 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 180
 181 /* Video */
 182 #undef CONFIG_FSL_DIU_FB
 183
 184 #ifdef CONFIG_FSL_DIU_FB
 185 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 186 #define CONFIG_VIDEO
 187 #define CONFIG_CMD_BMP
 188 #define CONFIG_CFB_CONSOLE
 189 #define CONFIG_VGA_AS_SINGLE_DEVICE
 190 #define CONFIG_VIDEO_LOGO
 191 #define CONFIG_VIDEO_BMP_LOGO
 192 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 193 /*
 194  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 195  * disable empty flash sector detection, which is I/O-intensive.
 196  */
 197 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 198 #endif
 199
 200 /*
 201  * Pass open firmware flat tree
 202  */
 203 #define CONFIG_OF_LIBFDT
 204 #define CONFIG_OF_BOARD_SETUP
 205 #define CONFIG_OF_STDOUT_VIA_ALIAS
 206
 207 /* new uImage format support */
 208 #define CONFIG_FIT
 209 #define CONFIG_FIT_VERBOSE
 210
 211 /* I2C */
 212 #define CONFIG_FSL_I2C
 213 #define CONFIG_HARD_I2C
 214 #define CONFIG_I2C_MULTI_BUS
 215 #define CONFIG_SYS_I2C_SPEED            400000
 216 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 217 #define CONFIG_SYS_I2C_SLAVE            0x7F
 218 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 219 #define CONFIG_SYS_I2C_OFFSET           0x3000
 220 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 221
 222 /*
 223  * I2C2 EEPROM
 224  */
 225 #define CONFIG_ID_EEPROM
 226 #define CONFIG_SYS_I2C_EEPROM_NXID
 227 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 229 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 230
 231 /*
 232  * General PCI
 233  * Memory space is mapped 1-1, but I/O space must start from 0.
 234  */
 235
 236 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 237 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 238 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 239 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 240 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 241 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 242 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 243 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 244 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 245
 246 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 247 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 248 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 249 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 250 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 251 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 252 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 253 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 254 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 255
 256 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 257 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 258 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 259 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 260 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 261 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 262 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 263 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 264 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 265
 266 #ifdef CONFIG_PCI
 267 #define CONFIG_NET_MULTI
 268 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 269 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 270 #endif
 271
 272 /* SATA */
 273 #define CONFIG_LIBATA
 274 #define CONFIG_FSL_SATA
 275
 276 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 277 #define CONFIG_SATA1
 278 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 279 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 280 #define CONFIG_SATA2
 281 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 282 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 283
 284 #ifdef CONFIG_FSL_SATA
 285 #define CONFIG_LBA48
 286 #define CONFIG_CMD_SATA
 287 #define CONFIG_DOS_PARTITION
 288 #define CONFIG_CMD_EXT2
 289 #endif
 290
 291 #define CONFIG_MMC
 292 #ifdef CONFIG_MMC
 293 #define CONFIG_CMD_MMC
 294 #define CONFIG_FSL_ESDHC
 295 #define CONFIG_GENERIC_MMC
 296 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 297 #endif
 298
 299 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 300 #define CONFIG_CMD_EXT2
 301 #define CONFIG_CMD_FAT
 302 #define CONFIG_DOS_PARTITION
 303 #endif
 304
 305 #define CONFIG_TSEC_ENET
 306 #ifdef CONFIG_TSEC_ENET
 307
 308 #define CONFIG_TSECV2
 309 #define CONFIG_NET_MULTI
 310
 311 #define CONFIG_MII                      /* MII PHY management */
 312 #define CONFIG_TSEC1            1
 313 #define CONFIG_TSEC1_NAME       "eTSEC1"
 314 #define CONFIG_TSEC2            1
 315 #define CONFIG_TSEC2_NAME       "eTSEC2"
 316
 317 #define TSEC1_PHY_ADDR          1
 318 #define TSEC2_PHY_ADDR          2
 319
 320 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 321 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 322
 323 #define TSEC1_PHYIDX            0
 324 #define TSEC2_PHYIDX            0
 325
 326 #define CONFIG_ETHPRIME         "eTSEC1"
 327
 328 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 329 #endif
 330
 331 /*
 332  * Environment
 333  */
 334 #define CONFIG_ENV_IS_IN_FLASH
 335 #define CONFIG_ENV_OVERWRITE
 336 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 337 #define CONFIG_ENV_SIZE         0x2000
 338 #define CONFIG_ENV_SECT_SIZE    0x20000
 339
 340 #define CONFIG_LOADS_ECHO
 341 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 342
 343 /*
 344  * Command line configuration.
 345  */
 346 #include <config_cmd_default.h>
 347
 348 #define CONFIG_CMD_ELF
 349 #define CONFIG_CMD_ERRATA
 350 #define CONFIG_CMD_IRQ
 351 #define CONFIG_CMD_I2C
 352 #define CONFIG_CMD_MII
 353 #define CONFIG_CMD_PING
 354 #define CONFIG_CMD_SETEXPR
 355
 356 #ifdef CONFIG_PCI
 357 #define CONFIG_CMD_PCI
 358 #define CONFIG_CMD_NET
 359 #endif
 360
 361 /*
 362  * USB
 363  */
 364 #define CONFIG_USB_EHCI
 365
 366 #ifdef CONFIG_USB_EHCI
 367 #define CONFIG_CMD_USB
 368 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 369 #define CONFIG_USB_EHCI_FSL
 370 #define CONFIG_USB_STORAGE
 371 #define CONFIG_CMD_FAT
 372 #endif
 373
 374 /*
 375  * Miscellaneous configurable options
 376  */
 377 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 378 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 379 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 380 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 381 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 382 #ifdef CONFIG_CMD_KGDB
 383 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 384 #else
 385 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 386 #endif
 387 /* Print Buffer Size */
 388 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 389 #define CONFIG_SYS_MAXARGS      16
 390 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 391 #define CONFIG_SYS_HZ           1000
 392
 393 /*
 394  * For booting Linux, the board info and command line data
 395  * have to be in the first 16 MB of memory, since this is
 396  * the maximum mapped by the Linux kernel during initialization.
 397  */
 398 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 399
 400 /*
 401  * Internal Definitions
 402  *
 403  * Boot Flags
 404  */
 405 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 406 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 407
 408 #ifdef CONFIG_CMD_KGDB
 409 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 410 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 411 #endif
 412
 413 /*
 414  * Environment Configuration
 415  */
 416
 417 #define CONFIG_HOSTNAME         p1022ds
 418 #define CONFIG_ROOTPATH         /opt/nfsroot
 419 #define CONFIG_BOOTFILE         uImage
 420 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 421
 422 #define CONFIG_LOADADDR         1000000
 423
 424 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 425 #define CONFIG_BOOTARGS
 426
 427 #define CONFIG_BAUDRATE 115200
 428
 429 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 430         "perf_mode=stable\0"                                            \
 431         "memctl_intlv_ctl=2\0"                                          \
 432         "netdev=eth0\0"                                                 \
 433         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 434         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 435                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 436                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 437                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 438                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 439                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 440         "consoledev=ttyS0\0"                                            \
 441         "ramdiskaddr=2000000\0"                                         \
 442         "ramdiskfile=uramdisk\0"                                        \
 443         "fdtaddr=c00000\0"                                              \
 444         "fdtfile=p1022ds.dtb\0"                                         \
 445         "bdev=sda3\0"                                                   \
 446         "diuregs=md e002c000 1d\0"                                      \
 447         "dium=mw e002c01c\0"                                            \
 448         "diuerr=md e002c014 1\0"                                        \
 449         "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
 450         "monitor=0-DVI\0"
 451
 452 #define CONFIG_HDBOOT                                   \
 453         "setenv bootargs root=/dev/$bdev rw "           \
 454         "console=$consoledev,$baudrate $othbootargs;"   \
 455         "tftp $loadaddr $bootfile;"                     \
 456         "tftp $fdtaddr $fdtfile;"                       \
 457         "bootm $loadaddr - $fdtaddr"
 458
 459 #define CONFIG_NFSBOOTCOMMAND                                           \
 460         "setenv bootargs root=/dev/nfs rw "                             \
 461         "nfsroot=$serverip:$rootpath "                                  \
 462         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 463         "console=$consoledev,$baudrate $othbootargs;"                   \
 464         "tftp $loadaddr $bootfile;"                                     \
 465         "tftp $fdtaddr $fdtfile;"                                       \
 466         "bootm $loadaddr - $fdtaddr"
 467
 468 #define CONFIG_RAMBOOTCOMMAND                                           \
 469         "setenv bootargs root=/dev/ram rw "                             \
 470         "console=$consoledev,$baudrate $othbootargs;"                   \
 471         "tftp $ramdiskaddr $ramdiskfile;"                               \
 472         "tftp $loadaddr $bootfile;"                                     \
 473         "tftp $fdtaddr $fdtfile;"                                       \
 474         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 475
 476 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 477
 478 #endif