include/configs/T104xRDB.h

   1 /*
   2 + * Copyright 2014 Freescale Semiconductor, Inc.
   3 + *
   4 + * SPDX-License-Identifier:     GPL-2.0+
   5 + */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * T104x RDB board configuration file
  12  */
  13 #define CONFIG_T104xRDB
  14 #define CONFIG_PHYS_64BIT
  15
  16 #ifdef CONFIG_RAMBOOT_PBL
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #endif
  20
  21 /* High Level Configuration Options */
  22 #define CONFIG_BOOKE
  23 #define CONFIG_E500                     /* BOOKE e500 family */
  24 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  25 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  26 #define CONFIG_MP                       /* support multiple processors */
  27
  28 #ifndef CONFIG_SYS_TEXT_BASE
  29 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  30 #endif
  31
  32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  34 #endif
  35
  36 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  37 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  38 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  39 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  40 #define CONFIG_PCI_INDIRECT_BRIDGE
  41 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  42 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  43 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  44 #define CONFIG_PCIE4                    /* PCIE controler 4 */
  45
  46 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  47 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  48
  49 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  50
  51 #define CONFIG_ENV_OVERWRITE
  52
  53 #ifdef CONFIG_SYS_NO_FLASH
  54 #define CONFIG_ENV_IS_NOWHERE
  55 #else
  56 #define CONFIG_FLASH_CFI_DRIVER
  57 #define CONFIG_SYS_FLASH_CFI
  58 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  59 #endif
  60
  61 #ifndef CONFIG_SYS_NO_FLASH
  62 #if defined(CONFIG_SPIFLASH)
  63 #define CONFIG_SYS_EXTRA_ENV_RELOC
  64 #define CONFIG_ENV_IS_IN_SPI_FLASH
  65 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  66 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  67 #define CONFIG_ENV_SECT_SIZE            0x10000
  68 #elif defined(CONFIG_SDCARD)
  69 #define CONFIG_SYS_EXTRA_ENV_RELOC
  70 #define CONFIG_ENV_IS_IN_MMC
  71 #define CONFIG_SYS_MMC_ENV_DEV          0
  72 #define CONFIG_ENV_SIZE                 0x2000
  73 #define CONFIG_ENV_OFFSET               (512 * 1658)
  74 #elif defined(CONFIG_NAND)
  75 #define CONFIG_SYS_EXTRA_ENV_RELOC
  76 #define CONFIG_ENV_IS_IN_NAND
  77 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  78 #define CONFIG_ENV_OFFSET               (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  79 #else
  80 #define CONFIG_ENV_IS_IN_FLASH
  81 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  82 #define CONFIG_ENV_SIZE         0x2000
  83 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  84 #endif
  85 #else /* CONFIG_SYS_NO_FLASH */
  86 #define CONFIG_ENV_SIZE                0x2000
  87 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
  88 #endif
  89
  90 #define CONFIG_SYS_CLK_FREQ     100000000
  91 #define CONFIG_DDR_CLK_FREQ     66666666
  92
  93 /*
  94  * These can be toggled for performance analysis, otherwise use default.
  95  */
  96 #define CONFIG_SYS_CACHE_STASHING
  97 #define CONFIG_BACKSIDE_L2_CACHE
  98 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  99 #define CONFIG_BTB                      /* toggle branch predition */
 100 #define CONFIG_DDR_ECC
 101 #ifdef CONFIG_DDR_ECC
 102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 103 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 104 #endif
 105
 106 #define CONFIG_ENABLE_36BIT_PHYS
 107
 108 #define CONFIG_ADDR_MAP
 109 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 110
 111 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 112 #define CONFIG_SYS_MEMTEST_END          0x00400000
 113 #define CONFIG_SYS_ALT_MEMTEST
 114 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 115
 116 /*
 117  *  Config the L3 Cache as L3 SRAM
 118  */
 119 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 120
 121 #define CONFIG_SYS_DCSRBAR              0xf0000000
 122 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 123
 124 /*
 125  * DDR Setup
 126  */
 127 #define CONFIG_VERY_BIG_RAM
 128 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 129 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 130
 131 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 132 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 133 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 134
 135 #define CONFIG_DDR_SPD
 136 #define CONFIG_SYS_DDR_RAW_TIMING
 137 #define CONFIG_SYS_FSL_DDR3
 138
 139 #define CONFIG_SYS_SPD_BUS_NUM  0
 140 #define SPD_EEPROM_ADDRESS      0x51
 141
 142 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 143
 144 /*
 145  * IFC Definitions
 146  */
 147 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 148 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 149
 150 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
 151 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
 152                                 CSPR_PORT_SIZE_16 | \
 153                                 CSPR_MSEL_NOR | \
 154                                 CSPR_V)
 155 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 156 /* NOR Flash Timing Params */
 157 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 158 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 159                                 FTIM0_NOR_TEADC(0x5) | \
 160                                 FTIM0_NOR_TEAHC(0x5))
 161 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 162                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 163                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 164 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 165                                 FTIM2_NOR_TCH(0x4) | \
 166                                 FTIM2_NOR_TWPH(0x0E) | \
 167                                 FTIM2_NOR_TWP(0x1c))
 168 #define CONFIG_SYS_NOR_FTIM3    0x0
 169
 170 #define CONFIG_SYS_FLASH_QUIET_TEST
 171 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 172
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 177
 178 #define CONFIG_SYS_FLASH_EMPTY_INFO
 179 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 180
 181 /* CPLD on IFC */
 182 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 183 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 184 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 185 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 186                                 | CSPR_PORT_SIZE_8 \
 187                                 | CSPR_MSEL_GPCM \
 188                                 | CSPR_V)
 189 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 190 #define CONFIG_SYS_CSOR2        0x0
 191 /* CPLD Timing parameters for IFC CS2 */
 192 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 193                                         FTIM0_GPCM_TEADC(0x0e) | \
 194                                         FTIM0_GPCM_TEAHC(0x0e))
 195 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 196                                         FTIM1_GPCM_TRAD(0x1f))
 197 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 198                                         FTIM2_GPCM_TCH(0x0) | \
 199                                         FTIM2_GPCM_TWP(0x1f))
 200 #define CONFIG_SYS_CS2_FTIM3            0x0
 201
 202 /* NAND Flash on IFC */
 203 #define CONFIG_NAND_FSL_IFC
 204 #define CONFIG_SYS_NAND_BASE            0xff800000
 205 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 206
 207 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 209                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 210                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 211                                 | CSPR_V)
 212 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 213
 214 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 215                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 216                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 217                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 218                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 219                                 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
 220                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 221
 222 #define CONFIG_SYS_NAND_ONFI_DETECTION
 223
 224 /* ONFI NAND Flash mode0 Timing Params */
 225 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 226                                         FTIM0_NAND_TWP(0x18)   | \
 227                                         FTIM0_NAND_TWCHT(0x07) | \
 228                                         FTIM0_NAND_TWH(0x0a))
 229 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 230                                         FTIM1_NAND_TWBE(0x39)  | \
 231                                         FTIM1_NAND_TRR(0x0e)   | \
 232                                         FTIM1_NAND_TRP(0x18))
 233 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 234                                         FTIM2_NAND_TREH(0x0a) | \
 235                                         FTIM2_NAND_TWHRE(0x1e))
 236 #define CONFIG_SYS_NAND_FTIM3           0x0
 237
 238 #define CONFIG_SYS_NAND_DDR_LAW         11
 239 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 240 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 241 #define CONFIG_MTD_NAND_VERIFY_WRITE
 242 #define CONFIG_CMD_NAND
 243
 244 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 245
 246 #if defined(CONFIG_NAND)
 247 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 248 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 249 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 250 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 251 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 252 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 253 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 254 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 255 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 256 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 257 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 258 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 259 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 260 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 261 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 262 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 263 #else
 264 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 265 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 266 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 273 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 274 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 275 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 276 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 277 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 278 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 279 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 280 #endif
 281
 282 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 283
 284 #if defined(CONFIG_RAMBOOT_PBL)
 285 #define CONFIG_SYS_RAMBOOT
 286 #endif
 287
 288 #define CONFIG_BOARD_EARLY_INIT_R
 289 #define CONFIG_MISC_INIT_R
 290
 291 #define CONFIG_HWCONFIG
 292
 293 /* define to use L1 as initial stack */
 294 #define CONFIG_L1_INIT_RAM
 295 #define CONFIG_SYS_INIT_RAM_LOCK
 296 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 299 /* The assembler doesn't like typecast */
 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 301         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 302           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 303 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 304
 305 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 306                                         GENERATED_GBL_DATA_SIZE)
 307 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 308
 309 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 310 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 311
 312 /* Serial Port - controlled on board with jumper J8
 313  * open - index 2
 314  * shorted - index 1
 315  */
 316 #define CONFIG_CONS_INDEX       1
 317 #define CONFIG_SYS_NS16550
 318 #define CONFIG_SYS_NS16550_SERIAL
 319 #define CONFIG_SYS_NS16550_REG_SIZE     1
 320 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 321
 322 #define CONFIG_SYS_BAUDRATE_TABLE       \
 323         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 324
 325 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 326 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 327 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 328 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 329 #define CONFIG_SERIAL_MULTI             /* Enable both serial ports */
 330 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 331
 332 /* Use the HUSH parser */
 333 #define CONFIG_SYS_HUSH_PARSER
 334 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 335
 336 /* pass open firmware flat tree */
 337 #define CONFIG_OF_LIBFDT
 338 #define CONFIG_OF_BOARD_SETUP
 339 #define CONFIG_OF_STDOUT_VIA_ALIAS
 340
 341 /* new uImage format support */
 342 #define CONFIG_FIT
 343 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 344
 345 /* I2C */
 346 #define CONFIG_SYS_I2C
 347 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 348 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 349 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 350 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 351 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 352 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 353 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 354
 355 /* I2C bus multiplexer */
 356 #define I2C_MUX_PCA_ADDR                0x70
 357 #ifdef CONFIG_T1040RDB
 358 #define I2C_MUX_CH_DEFAULT      0x8
 359 #endif
 360
 361 #ifdef CONFIG_T1042RDB_PI
 362 /*
 363  * RTC configuration
 364  */
 365 #define RTC
 366 #define CONFIG_RTC_DS1337               1
 367 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 368
 369 /*DVI encoder*/
 370 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
 371 #endif
 372
 373 /*
 374  * eSPI - Enhanced SPI
 375  */
 376 #define CONFIG_FSL_ESPI
 377 #define CONFIG_SPI_FLASH
 378 #define CONFIG_SPI_FLASH_STMICRO
 379 #define CONFIG_CMD_SF
 380 #define CONFIG_SF_DEFAULT_SPEED         10000000
 381 #define CONFIG_SF_DEFAULT_MODE          0
 382 #define CONFIG_ENV_SPI_BUS              0
 383 #define CONFIG_ENV_SPI_CS               0
 384 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 385 #define CONFIG_ENV_SPI_MODE             0
 386
 387 /*
 388  * General PCI
 389  * Memory space is mapped 1-1, but I/O space must start from 0.
 390  */
 391
 392 #ifdef CONFIG_PCI
 393 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 394 #ifdef CONFIG_PCIE1
 395 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 396 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 397 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 398 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 399 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 400 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 401 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 402 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 403 #endif
 404
 405 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 406 #ifdef CONFIG_PCIE2
 407 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 408 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 409 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 410 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 411 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 412 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 413 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 414 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 415 #endif
 416
 417 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 418 #ifdef CONFIG_PCIE3
 419 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 420 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 421 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 422 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 423 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 424 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 425 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 426 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 427 #endif
 428
 429 /* controller 4, Base address 203000 */
 430 #ifdef CONFIG_PCIE4
 431 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 432 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 433 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 434 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 435 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 436 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 437 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 438 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 439 #endif
 440
 441 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 442 #define CONFIG_E1000
 443
 444 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 445 #define CONFIG_DOS_PARTITION
 446 #endif  /* CONFIG_PCI */
 447
 448 /* SATA */
 449 #define CONFIG_FSL_SATA_V2
 450 #ifdef CONFIG_FSL_SATA_V2
 451 #define CONFIG_LIBATA
 452 #define CONFIG_FSL_SATA
 453
 454 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 455 #define CONFIG_SATA1
 456 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 457 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 458
 459 #define CONFIG_LBA48
 460 #define CONFIG_CMD_SATA
 461 #define CONFIG_DOS_PARTITION
 462 #define CONFIG_CMD_EXT2
 463 #endif
 464
 465 /*
 466 * USB
 467 */
 468 #define CONFIG_HAS_FSL_DR_USB
 469
 470 #ifdef CONFIG_HAS_FSL_DR_USB
 471 #define CONFIG_USB_EHCI
 472
 473 #ifdef CONFIG_USB_EHCI
 474 #define CONFIG_CMD_USB
 475 #define CONFIG_USB_STORAGE
 476 #define CONFIG_USB_EHCI_FSL
 477 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 478 #define CONFIG_CMD_EXT2
 479 #endif
 480 #endif
 481
 482 #define CONFIG_MMC
 483
 484 #ifdef CONFIG_MMC
 485 #define CONFIG_FSL_ESDHC
 486 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 487 #define CONFIG_CMD_MMC
 488 #define CONFIG_GENERIC_MMC
 489 #define CONFIG_CMD_EXT2
 490 #define CONFIG_CMD_FAT
 491 #define CONFIG_DOS_PARTITION
 492 #endif
 493
 494 /* Qman/Bman */
 495 #ifndef CONFIG_NOBQFMAN
 496 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 497 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 498 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 499 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 500 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 501 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 502 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 503 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 504 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 505
 506 #define CONFIG_SYS_DPAA_FMAN
 507 #define CONFIG_SYS_DPAA_PME
 508
 509 #define CONFIG_QE
 510 #define CONFIG_U_QE
 511
 512 /* Default address of microcode for the Linux Fman driver */
 513 #if defined(CONFIG_SPIFLASH)
 514 /*
 515  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 516  * env, so we got 0x110000.
 517  */
 518 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 519 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 520 #elif defined(CONFIG_SDCARD)
 521 /*
 522  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 523  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 524  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 525  */
 526 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 527 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 528 #elif defined(CONFIG_NAND)
 529 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 530 #define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 531 #else
 532 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 533 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 534 #define CONFIG_SYS_QE_FW_ADDR           0xEFF10000
 535 #endif
 536 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 537 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 538 #endif /* CONFIG_NOBQFMAN */
 539
 540 #ifdef CONFIG_SYS_DPAA_FMAN
 541 #define CONFIG_FMAN_ENET
 542 #define CONFIG_PHY_VITESSE
 543 #define CONFIG_PHY_REALTEK
 544 #endif
 545
 546 #ifdef CONFIG_FMAN_ENET
 547 #ifdef CONFIG_T1040RDB
 548 #define CONFIG_SYS_SGMII1_PHY_ADDR              0x03
 549 #endif
 550 #define CONFIG_SYS_RGMII1_PHY_ADDR              0x01
 551 #define CONFIG_SYS_RGMII2_PHY_ADDR              0x02
 552
 553 #define CONFIG_MII              /* MII PHY management */
 554 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 555 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 556 #endif
 557
 558 /*
 559  * Environment
 560  */
 561 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 562 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 563
 564 /*
 565  * Command line configuration.
 566  */
 567 #include <config_cmd_default.h>
 568
 569 #ifdef CONFIG_T1042RDB_PI
 570 #define CONFIG_CMD_DATE
 571 #endif
 572 #define CONFIG_CMD_DHCP
 573 #define CONFIG_CMD_ELF
 574 #define CONFIG_CMD_ERRATA
 575 #define CONFIG_CMD_GREPENV
 576 #define CONFIG_CMD_IRQ
 577 #define CONFIG_CMD_I2C
 578 #define CONFIG_CMD_MII
 579 #define CONFIG_CMD_PING
 580 #define CONFIG_CMD_REGINFO
 581 #define CONFIG_CMD_SETEXPR
 582
 583 #ifdef CONFIG_PCI
 584 #define CONFIG_CMD_PCI
 585 #define CONFIG_CMD_NET
 586 #endif
 587
 588 /*
 589  * Miscellaneous configurable options
 590  */
 591 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 592 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 593 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 594 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 595 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 596 #ifdef CONFIG_CMD_KGDB
 597 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 598 #else
 599 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 600 #endif
 601 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 602 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 603 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 604
 605 /*
 606  * For booting Linux, the board info and command line data
 607  * have to be in the first 64 MB of memory, since this is
 608  * the maximum mapped by the Linux kernel during initialization.
 609  */
 610 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 611 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 612
 613 #ifdef CONFIG_CMD_KGDB
 614 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 615 #endif
 616
 617 /*
 618  * Environment Configuration
 619  */
 620 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 621 #define CONFIG_BOOTFILE         "uImage"
 622 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 623
 624 /* default location for tftp and bootm */
 625 #define CONFIG_LOADADDR         1000000
 626
 627 #define CONFIG_BOOTDELAY        10      /*-1 disables auto-boot*/
 628
 629 #define CONFIG_BAUDRATE 115200
 630
 631 #define __USB_PHY_TYPE  utmi
 632
 633 #ifdef CONFIG_T1040RDB
 634 #define FDTFILE         "t1040rdb/t1040rdb.dtb"
 635 #define RAMDISKFILE     "t1040rdb/ramdisk.uboot"
 636 #elif CONFIG_T1042RDB_PI
 637 #define FDTFILE         "t1040rdb_pi/t1040rdb_pi.dtb"
 638 #define RAMDISKFILE     "t1040rdb_pi/ramdisk.uboot"
 639 #endif
 640
 641 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 642         "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"                  \
 643         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 644         "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 645         "netdev=eth0\0"                                         \
 646         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 647         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 648         "tftpflash=tftpboot $loadaddr $uboot && "               \
 649         "protect off $ubootaddr +$filesize && "                 \
 650         "erase $ubootaddr +$filesize && "                       \
 651         "cp.b $loadaddr $ubootaddr $filesize && "               \
 652         "protect on $ubootaddr +$filesize && "                  \
 653         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 654         "consoledev=ttyS0\0"                                    \
 655         "ramdiskaddr=2000000\0"                                 \
 656         "ramdiskfile=" __stringify(RAMDISKFILE) "\0"            \
 657         "fdtaddr=c00000\0"                                      \
 658         "fdtfile=" __stringify(FDTFILE) "\0"                    \
 659         "bdev=sda3\0"                                           \
 660         "c=ffe\0"
 661
 662 #define CONFIG_LINUX                       \
 663         "setenv bootargs root=/dev/ram rw "            \
 664         "console=$consoledev,$baudrate $othbootargs;"  \
 665         "setenv ramdiskaddr 0x02000000;"               \
 666         "setenv fdtaddr 0x00c00000;"                   \
 667         "setenv loadaddr 0x1000000;"                   \
 668         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 669
 670 #define CONFIG_HDBOOT                                   \
 671         "setenv bootargs root=/dev/$bdev rw "           \
 672         "console=$consoledev,$baudrate $othbootargs;"   \
 673         "tftp $loadaddr $bootfile;"                     \
 674         "tftp $fdtaddr $fdtfile;"                       \
 675         "bootm $loadaddr - $fdtaddr"
 676
 677 #define CONFIG_NFSBOOTCOMMAND                   \
 678         "setenv bootargs root=/dev/nfs rw "     \
 679         "nfsroot=$serverip:$rootpath "          \
 680         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 681         "console=$consoledev,$baudrate $othbootargs;"   \
 682         "tftp $loadaddr $bootfile;"             \
 683         "tftp $fdtaddr $fdtfile;"               \
 684         "bootm $loadaddr - $fdtaddr"
 685
 686 #define CONFIG_RAMBOOTCOMMAND                           \
 687         "setenv bootargs root=/dev/ram rw "             \
 688         "console=$consoledev,$baudrate $othbootargs;"   \
 689         "tftp $ramdiskaddr $ramdiskfile;"               \
 690         "tftp $loadaddr $bootfile;"                     \
 691         "tftp $fdtaddr $fdtfile;"                       \
 692         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 693
 694 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 695
 696 #ifdef CONFIG_SECURE_BOOT
 697 #include <asm/fsl_secure_boot.h>
 698 #endif
 699
 700 #endif  /* __CONFIG_H */