include/configs/axs101.h

   1 /*
   2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_AXS101_H_
   8 #define _CONFIG_AXS101_H_
   9
  10 /*
  11  *  CPU configuration
  12  */
  13 #define CONFIG_SYS_TIMER_RATE           CONFIG_SYS_CLK_FREQ
  14
  15 /*
  16  * Board configuration
  17  */
  18 #define CONFIG_SYS_GENERIC_BOARD
  19 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is in RAM already */
  20
  21 #define CONFIG_ARCH_EARLY_INIT_R
  22
  23 #define ARC_FPGA_PERIPHERAL_BASE        0xE0000000
  24 #define ARC_APB_PERIPHERAL_BASE         0xF0000000
  25 #define ARC_DWMMC_BASE                  (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
  26 #define ARC_DWGMAC_BASE                 (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
  27
  28 /*
  29  * Memory configuration
  30  */
  31 #define CONFIG_SYS_TEXT_BASE            0x81000000
  32 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  33
  34 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  35 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  36 #define CONFIG_SYS_SDRAM_SIZE           0x20000000      /* 512 Mb */
  37
  38 #define CONFIG_SYS_INIT_SP_ADDR         \
  39         (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  40
  41 #define CONFIG_SYS_MALLOC_LEN           0x200000        /* 2 MB */
  42 #define CONFIG_SYS_BOOTM_LEN            0x2000000       /* 32 MB */
  43 #define CONFIG_SYS_LOAD_ADDR            0x82000000
  44
  45 /*
  46  * NAND Flash configuration
  47  */
  48 #define CONFIG_SYS_NO_FLASH
  49 #define CONFIG_SYS_NAND_BASE            (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
  50 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  51
  52 /*
  53  * UART configuration
  54  *
  55  * CONFIG_CONS_INDEX = 1 - Debug UART
  56  * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
  57  */
  58 #define CONFIG_CONS_INDEX               4
  59 #define CONFIG_SYS_NS16550
  60 #define CONFIG_SYS_NS16550_SERIAL
  61 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  62 #if (CONFIG_CONS_INDEX == 1)
  63         /* Debug UART */
  64 #       define CONFIG_SYS_NS16550_CLK           33333000
  65 #else
  66         /* FPGA UARTs use different clock */
  67 #       define CONFIG_SYS_NS16550_CLK           33333333
  68 #endif
  69 #define CONFIG_SYS_NS16550_COM1         (ARC_APB_PERIPHERAL_BASE + 0x5000)
  70 #define CONFIG_SYS_NS16550_COM2         (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
  71 #define CONFIG_SYS_NS16550_COM3         (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
  72 #define CONFIG_SYS_NS16550_COM4         (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
  73 #define CONFIG_SYS_NS16550_MEM32
  74
  75 #define CONFIG_BAUDRATE                 115200
  76 /*
  77  * I2C configuration
  78  */
  79 #define CONFIG_SYS_I2C
  80 #define CONFIG_SYS_I2C_DW
  81 #define CONFIG_I2C_ENV_EEPROM_BUS       2
  82 #define CONFIG_SYS_I2C_SPEED            100000
  83 #define CONFIG_SYS_I2C_SPEED1           100000
  84 #define CONFIG_SYS_I2C_SPEED2           100000
  85 #define CONFIG_SYS_I2C_SLAVE            0
  86 #define CONFIG_SYS_I2C_SLAVE1           0
  87 #define CONFIG_SYS_I2C_SLAVE2           0
  88 #define CONFIG_SYS_I2C_BASE             0xE001D000
  89 #define CONFIG_SYS_I2C_BASE1            0xE001E000
  90 #define CONFIG_SYS_I2C_BASE2            0xE001F000
  91 #define CONFIG_SYS_I2C_BUS_MAX          3
  92 #define IC_CLK                          50
  93
  94 /*
  95  * EEPROM configuration
  96  */
  97 #define CONFIG_SYS_I2C_MULTI_EEPROMS
  98 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xA8 >> 1)
  99 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 100 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     1
 101 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 102 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   64
 103
 104 /*
 105  * SD/MMC configuration
 106  */
 107 #define CONFIG_MMC
 108 #define CONFIG_GENERIC_MMC
 109 #define CONFIG_DWMMC
 110 #define CONFIG_DOS_PARTITION
 111
 112 /*
 113  * Ethernet PHY configuration
 114  */
 115 #define CONFIG_PHYLIB
 116 #define CONFIG_MII
 117 #define CONFIG_PHY_GIGE
 118
 119 /*
 120  * Ethernet configuration
 121  */
 122 #define CONFIG_DESIGNWARE_ETH
 123 #define CONFIG_DW_AUTONEG
 124 #define CONFIG_NET_MULTI
 125
 126 /*
 127  * Command line configuration
 128  */
 129 #include <config_cmd_default.h>
 130
 131 #define CONFIG_CMD_DHCP
 132 #define CONFIG_CMD_EEPROM
 133 #define CONFIG_CMD_ELF
 134 #define CONFIG_CMD_FAT
 135 #define CONFIG_CMD_I2C
 136 #define CONFIG_CMD_MMC
 137 #define CONFIG_CMD_NAND
 138 #define CONFIG_CMD_PING
 139 #define CONFIG_CMD_RARP
 140
 141 #define CONFIG_OF_LIBFDT
 142
 143 #define CONFIG_AUTO_COMPLETE
 144 #define CONFIG_SYS_MAXARGS              16
 145
 146 /*
 147  * Environment settings
 148  */
 149 #define CONFIG_ENV_IS_IN_EEPROM
 150 #define CONFIG_ENV_SIZE                 0x00200         /* 512 bytes */
 151 #define CONFIG_ENV_OFFSET               0
 152
 153 /*
 154  * Environment configuration
 155  */
 156 #define CONFIG_BOOTDELAY                3
 157 #define CONFIG_BOOTFILE                 "uImage"
 158 #define CONFIG_BOOTARGS                 "console=ttyS3,115200n8"
 159 #define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
 160
 161 /*
 162  * Console configuration
 163  */
 164 #define CONFIG_SYS_LONGHELP
 165 #define CONFIG_SYS_PROMPT               "AXS# "
 166 #define CONFIG_SYS_CBSIZE               256
 167 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 168 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 169                                                 sizeof(CONFIG_SYS_PROMPT) + 16)
 170
 171 /*
 172  * Misc utility configuration
 173  */
 174 #define CONFIG_BOUNCE_BUFFER
 175
 176 #endif /* _CONFIG_AXS101_H_ */