include/configs/axs101.h

   1 /*
   2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_AXS101_H_
   8 #define _CONFIG_AXS101_H_
   9
  10 /*
  11  *  CPU configuration
  12  */
  13 #define CONFIG_SYS_CACHELINE_SIZE       32
  14 #define CONFIG_SYS_TIMER_RATE           CONFIG_SYS_CLK_FREQ
  15
  16 /* NAND controller DMA doesn't work correctly with D$ enabled */
  17 #define CONFIG_SYS_DCACHE_OFF
  18
  19 /*
  20  * Board configuration
  21  */
  22 #define CONFIG_SYS_GENERIC_BOARD
  23 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is in RAM already */
  24
  25 #define CONFIG_ARCH_EARLY_INIT_R
  26
  27 #define ARC_FPGA_PERIPHERAL_BASE        0xE0000000
  28 #define ARC_APB_PERIPHERAL_BASE         0xF0000000
  29 #define ARC_DWMMC_BASE                  (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
  30 #define ARC_DWGMAC_BASE                 (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
  31
  32 /*
  33  * Memory configuration
  34  */
  35 #define CONFIG_SYS_TEXT_BASE            0x81000000
  36 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  37
  38 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  39 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  40 #define CONFIG_SYS_SDRAM_SIZE           0x20000000      /* 512 Mb */
  41
  42 #define CONFIG_SYS_INIT_SP_ADDR         \
  43         (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  44
  45 #define CONFIG_SYS_MALLOC_LEN           0x200000        /* 2 MB */
  46 #define CONFIG_SYS_BOOTM_LEN            0x2000000       /* 32 MB */
  47 #define CONFIG_SYS_LOAD_ADDR            0x82000000
  48
  49 /*
  50  * NAND Flash configuration
  51  */
  52 #define CONFIG_SYS_NO_FLASH
  53 #define CONFIG_SYS_NAND_BASE            (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
  54 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  55
  56 /*
  57  * UART configuration
  58  *
  59  * CONFIG_CONS_INDEX = 1 - Debug UART
  60  * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
  61  */
  62 #define CONFIG_CONS_INDEX               4
  63 #define CONFIG_SYS_NS16550
  64 #define CONFIG_SYS_NS16550_SERIAL
  65 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  66 #if (CONFIG_CONS_INDEX == 1)
  67         /* Debug UART */
  68 #       define CONFIG_SYS_NS16550_CLK           33333000
  69 #else
  70         /* FPGA UARTs use different clock */
  71 #       define CONFIG_SYS_NS16550_CLK           33333333
  72 #endif
  73 #define CONFIG_SYS_NS16550_COM1         (ARC_APB_PERIPHERAL_BASE + 0x5000)
  74 #define CONFIG_SYS_NS16550_COM2         (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
  75 #define CONFIG_SYS_NS16550_COM3         (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
  76 #define CONFIG_SYS_NS16550_COM4         (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
  77 #define CONFIG_SYS_NS16550_MEM32
  78
  79 #define CONFIG_BAUDRATE                 115200
  80 /*
  81  * I2C configuration
  82  */
  83 #define CONFIG_SYS_I2C
  84 #define CONFIG_SYS_I2C_DW
  85 #define CONFIG_I2C_ENV_EEPROM_BUS       2
  86 #define CONFIG_SYS_I2C_SPEED            100000
  87 #define CONFIG_SYS_I2C_SPEED1           100000
  88 #define CONFIG_SYS_I2C_SPEED2           100000
  89 #define CONFIG_SYS_I2C_SLAVE            0
  90 #define CONFIG_SYS_I2C_SLAVE1           0
  91 #define CONFIG_SYS_I2C_SLAVE2           0
  92 #define CONFIG_SYS_I2C_BASE             0xE001D000
  93 #define CONFIG_SYS_I2C_BASE1            0xE001E000
  94 #define CONFIG_SYS_I2C_BASE2            0xE001F000
  95 #define CONFIG_SYS_I2C_BUS_MAX          3
  96 #define IC_CLK                          50
  97
  98 /*
  99  * EEPROM configuration
 100  */
 101 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 102 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xA8 >> 1)
 103 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 104 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     1
 105 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 106 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   64
 107
 108 /*
 109  * SD/MMC configuration
 110  */
 111 #define CONFIG_MMC
 112 #define CONFIG_GENERIC_MMC
 113 #define CONFIG_DWMMC
 114 #define CONFIG_DOS_PARTITION
 115
 116 /*
 117  * Ethernet PHY configuration
 118  */
 119 #define CONFIG_PHYLIB
 120 #define CONFIG_MII
 121 #define CONFIG_PHY_GIGE
 122
 123 /*
 124  * Ethernet configuration
 125  */
 126 #define CONFIG_DESIGNWARE_ETH
 127 #define CONFIG_DW_AUTONEG
 128 #define CONFIG_NET_MULTI
 129
 130 /*
 131  * Command line configuration
 132  */
 133 #include <config_cmd_default.h>
 134
 135 #define CONFIG_CMD_DHCP
 136 #define CONFIG_CMD_EEPROM
 137 #define CONFIG_CMD_ELF
 138 #define CONFIG_CMD_FAT
 139 #define CONFIG_CMD_I2C
 140 #define CONFIG_CMD_MMC
 141 #define CONFIG_CMD_NAND
 142 #define CONFIG_CMD_PING
 143 #define CONFIG_CMD_RARP
 144
 145 #define CONFIG_OF_LIBFDT
 146
 147 #define CONFIG_AUTO_COMPLETE
 148 #define CONFIG_SYS_MAXARGS              16
 149
 150 /*
 151  * Environment settings
 152  */
 153 #define CONFIG_ENV_IS_IN_EEPROM
 154 #define CONFIG_ENV_SIZE                 0x00200         /* 512 bytes */
 155 #define CONFIG_ENV_OFFSET               0
 156
 157 /*
 158  * Environment configuration
 159  */
 160 #define CONFIG_BOOTDELAY                3
 161 #define CONFIG_BOOTFILE                 "uImage"
 162 #define CONFIG_BOOTARGS                 "console=ttyS3,115200n8"
 163 #define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
 164
 165 /*
 166  * Console configuration
 167  */
 168 #define CONFIG_SYS_LONGHELP
 169 #define CONFIG_SYS_PROMPT               "AXS# "
 170 #define CONFIG_SYS_CBSIZE               256
 171 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 172 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 173                                                 sizeof(CONFIG_SYS_PROMPT) + 16)
 174
 175 /*
 176  * Misc utility configuration
 177  */
 178 #define CONFIG_BOUNCE_BUFFER
 179
 180 #endif /* _CONFIG_AXS101_H_ */