include/configs/cm_t35.h

   1 /*
   2  * (C) Copyright 2011
   3  * CompuLab, Ltd.
   4  * Mike Rapoport <mike@compulab.co.il>
   5  * Igor Grinberg <grinberg@compulab.co.il>
   6  *
   7  * Based on omap3_beagle.h
   8  * (C) Copyright 2006-2008
   9  * Texas Instruments.
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Syed Mohammed Khasim <x0khasim@ti.com>
  12  *
  13  * Configuration settings for the CompuLab CM-T35 board
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc.
  31  */
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39 #define CONFIG_ARMV7            1       /* This is an ARM V7 CPU core */
  40 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  41 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  42 #define CONFIG_OMAP3430         1       /* which is in a 3430 */
  43 #define CONFIG_CM_T35           1       /* working with CM-T35 */
  44
  45 #define CONFIG_SYS_TEXT_BASE    0x80008000
  46
  47 #define CONFIG_SDRC     /* The chip has SDRC controller */
  48
  49 #include <asm/arch/cpu.h>               /* get chip and board defs */
  50 #include <asm/arch/omap3.h>
  51
  52 /*
  53  * Display CPU and Board information
  54  */
  55 #define CONFIG_DISPLAY_CPUINFO          1
  56 #define CONFIG_DISPLAY_BOARDINFO        1
  57
  58 /* Clock Defines */
  59 #define V_OSCK                  26000000        /* Clock output from T2 */
  60 #define V_SCLK                  (V_OSCK >> 1)
  61
  62 #undef CONFIG_USE_IRQ                           /* no support for IRQs */
  63 #define CONFIG_MISC_INIT_R
  64
  65 #define CONFIG_OF_LIBFDT                1
  66 /*
  67  * The early kernel mapping on ARM currently only maps from the base of DRAM
  68  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
  69  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
  70  * so that leaves DRAM base to DRAM base + 0x4000 available.
  71  */
  72 #define CONFIG_SYS_BOOTMAPSZ            0x4000
  73
  74 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  75 #define CONFIG_SETUP_MEMORY_TAGS        1
  76 #define CONFIG_INITRD_TAG               1
  77 #define CONFIG_REVISION_TAG             1
  78
  79 /*
  80  * Size of malloc() pool
  81  */
  82 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  83                                                 /* Sector */
  84 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  85                                                 /* initial data */
  86
  87 /*
  88  * Hardware drivers
  89  */
  90
  91 /*
  92  * NS16550 Configuration
  93  */
  94 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  95
  96 #define CONFIG_SYS_NS16550
  97 #define CONFIG_SYS_NS16550_SERIAL
  98 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  99 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
 100
 101 /*
 102  * select serial console configuration
 103  */
 104 #define CONFIG_CONS_INDEX               3
 105 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
 106 #define CONFIG_SERIAL3                  3       /* UART3 */
 107
 108 /* allow to overwrite serial and ethaddr */
 109 #define CONFIG_ENV_OVERWRITE
 110 #define CONFIG_BAUDRATE                 115200
 111 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
 112                                         115200}
 113 #define CONFIG_MMC                      1
 114 #define CONFIG_OMAP3_MMC                1
 115 #define CONFIG_DOS_PARTITION            1
 116
 117 /* DDR - I use Micron DDR */
 118 #define CONFIG_OMAP3_MICRON_DDR         1
 119
 120 /* USB */
 121 #define CONFIG_MUSB_UDC                 1
 122 #define CONFIG_USB_OMAP3                1
 123 #define CONFIG_TWL4030_USB              1
 124
 125 /* USB device configuration */
 126 #define CONFIG_USB_DEVICE               1
 127 #define CONFIG_USB_TTY                  1
 128 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 129
 130 /* commands to include */
 131 #include <config_cmd_default.h>
 132
 133 #define CONFIG_CMD_CACHE
 134 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 135 #define CONFIG_CMD_FAT          /* FAT support                  */
 136 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 137 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
 138 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 139 #define MTDIDS_DEFAULT                  "nand0=nand"
 140 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
 141                                         "1920k(u-boot),128k(u-boot-env),"\
 142                                         "4m(kernel),-(fs)"
 143
 144 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 145 #define CONFIG_CMD_MMC          /* MMC support                  */
 146 #define CONFIG_CMD_NAND         /* NAND support                 */
 147 #define CONFIG_CMD_DHCP
 148 #define CONFIG_CMD_PING
 149
 150 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 151 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 152 #undef CONFIG_CMD_IMLS          /* List all found images        */
 153
 154 #define CONFIG_SYS_NO_FLASH
 155 #define CONFIG_HARD_I2C                 1
 156 #define CONFIG_SYS_I2C_SPEED            100000
 157 #define CONFIG_SYS_I2C_SLAVE            1
 158 #define CONFIG_SYS_I2C_BUS              0
 159 #define CONFIG_SYS_I2C_BUS_SELECT       1
 160 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 161
 162 /*
 163  * TWL4030
 164  */
 165 #define CONFIG_TWL4030_POWER            1
 166 #define CONFIG_TWL4030_LED              1
 167
 168 /*
 169  * Board NAND Info.
 170  */
 171 #define CONFIG_SYS_NAND_QUIET_TEST      1
 172 #define CONFIG_NAND_OMAP_GPMC
 173 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 174                                                         /* to access nand */
 175 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 176                                                         /* to access nand at */
 177                                                         /* CS0 */
 178 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 179
 180 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 181                                                         /* devices */
 182 #define CONFIG_JFFS2_NAND
 183 /* nand device jffs2 lives on */
 184 #define CONFIG_JFFS2_DEV                "nand0"
 185 /* start of jffs2 partition */
 186 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 187 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 188                                                         /* partition */
 189
 190 /* Environment information */
 191 #define CONFIG_BOOTDELAY                10
 192
 193 #define CONFIG_EXTRA_ENV_SETTINGS \
 194         "loadaddr=0x82000000\0" \
 195         "usbtty=cdc_acm\0" \
 196         "console=ttyS2,115200n8\0" \
 197         "mpurate=500\0" \
 198         "vram=12M\0" \
 199         "dvimode=1024x768MR-16@60\0" \
 200         "defaultdisplay=dvi\0" \
 201         "mmcdev=0\0" \
 202         "mmcroot=/dev/mmcblk0p2 rw\0" \
 203         "mmcrootfstype=ext3 rootwait\0" \
 204         "nandroot=/dev/mtdblock4 rw\0" \
 205         "nandrootfstype=jffs2\0" \
 206         "mmcargs=setenv bootargs console=${console} " \
 207                 "mpurate=${mpurate} " \
 208                 "vram=${vram} " \
 209                 "omapfb.mode=dvi:${dvimode} " \
 210                 "omapfb.debug=y " \
 211                 "omapdss.def_disp=${defaultdisplay} " \
 212                 "root=${mmcroot} " \
 213                 "rootfstype=${mmcrootfstype}\0" \
 214         "nandargs=setenv bootargs console=${console} " \
 215                 "mpurate=${mpurate} " \
 216                 "vram=${vram} " \
 217                 "omapfb.mode=dvi:${dvimode} " \
 218                 "omapfb.debug=y " \
 219                 "omapdss.def_disp=${defaultdisplay} " \
 220                 "root=${nandroot} " \
 221                 "rootfstype=${nandrootfstype}\0" \
 222         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 223         "bootscript=echo Running bootscript from mmc ...; " \
 224                 "source ${loadaddr}\0" \
 225         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 226         "mmcboot=echo Booting from mmc ...; " \
 227                 "run mmcargs; " \
 228                 "bootm ${loadaddr}\0" \
 229         "nandboot=echo Booting from nand ...; " \
 230                 "run nandargs; " \
 231                 "nand read ${loadaddr} 280000 400000; " \
 232                 "bootm ${loadaddr}\0" \
 233
 234 #define CONFIG_BOOTCOMMAND \
 235         "if mmc rescan ${mmcdev}; then " \
 236                 "if run loadbootscript; then " \
 237                         "run bootscript; " \
 238                 "else " \
 239                         "if run loaduimage; then " \
 240                                 "run mmcboot; " \
 241                         "else run nandboot; " \
 242                         "fi; " \
 243                 "fi; " \
 244         "else run nandboot; fi"
 245
 246 /*
 247  * Miscellaneous configurable options
 248  */
 249 #define CONFIG_AUTO_COMPLETE
 250 #define CONFIG_CMDLINE_EDITING
 251 #define CONFIG_TIMESTAMP
 252 #define CONFIG_SYS_AUTOLOAD     "no"
 253 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 254 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 255 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 256 #define CONFIG_SYS_PROMPT               "CM-T35 # "
 257 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 258 /* Print Buffer Size */
 259 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 260                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 261 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 262 /* Boot Argument Buffer Size */
 263 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 264
 265 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 266                                                                 /* works on */
 267 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 268                                         0x01F00000) /* 31MB */
 269
 270 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 271                                                         /* load address */
 272
 273 /*
 274  * OMAP3 has 12 GP timers, they can be driven by the system clock
 275  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 276  * This rate is divided by a local divisor.
 277  */
 278 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 279 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 280 #define CONFIG_SYS_HZ                   1000
 281
 282 /*-----------------------------------------------------------------------
 283  * Stack sizes
 284  *
 285  * The stack sizes are set up in start.S using the settings below
 286  */
 287 #define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
 288 #ifdef CONFIG_USE_IRQ
 289 #define CONFIG_STACKSIZE_IRQ    (4 << 10)       /* IRQ stack 4 KiB */
 290 #define CONFIG_STACKSIZE_FIQ    (4 << 10)       /* FIQ stack 4 KiB */
 291 #endif
 292
 293 /*-----------------------------------------------------------------------
 294  * Physical Memory Map
 295  */
 296 #define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 297 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 298 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 299
 300 /* SDRAM Bank Allocation method */
 301 #define SDRC_R_B_C              1
 302
 303 /*-----------------------------------------------------------------------
 304  * FLASH and environment organization
 305  */
 306
 307 /* **** PISMO SUPPORT *** */
 308
 309 /* Configure the PISMO */
 310 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 311 #define PISMO1_ONEN_SIZE                GPMC_SIZE_128M
 312
 313 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 314
 315 #define CONFIG_SYS_FLASH_BASE           boot_flash_base
 316
 317 /* Monitor at start of flash */
 318 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 319 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 320
 321 #define CONFIG_ENV_IS_IN_NAND           1
 322 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 323 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 324
 325 #define CONFIG_SYS_ENV_SECT_SIZE        boot_flash_sec
 326 #define CONFIG_ENV_OFFSET               boot_flash_off
 327 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 328
 329 #ifndef __ASSEMBLY__
 330 extern unsigned int boot_flash_base;
 331 extern volatile unsigned int boot_flash_env_addr;
 332 extern unsigned int boot_flash_off;
 333 extern unsigned int boot_flash_sec;
 334 extern unsigned int boot_flash_type;
 335 #endif
 336
 337 #if defined(CONFIG_CMD_NET)
 338 #define CONFIG_NET_MULTI
 339 #define CONFIG_SMC911X
 340 #define CONFIG_SMC911X_32_BIT
 341 #define CM_T35_SMC911X_BASE     0x2C000000
 342 #define SB_T35_SMC911X_BASE     (CM_T35_SMC911X_BASE + (16 << 20))
 343 #define CONFIG_SMC911X_BASE     CM_T35_SMC911X_BASE
 344 #endif /* (CONFIG_CMD_NET) */
 345
 346 /* additions for new relocation code, must be added to all boards */
 347 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 348 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 349 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 350 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 351                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 352                                          GENERATED_GBL_DATA_SIZE)
 353
 354 #endif /* __CONFIG_H */