include/configs/corenet_ds.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * Corenet DS style board configuration file
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #include "../board/freescale/common/ics307_clk.h"
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  34 #endif
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_BOOKE
  38 #define CONFIG_E500                     /* BOOKE e500 family */
  39 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  40 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  41 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  42 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  43 #define CONFIG_MP                       /* support multiple processors */
  44
  45 #ifndef CONFIG_SYS_TEXT_BASE
  46 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  47 #endif
  48
  49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  50 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  51 #endif
  52
  53 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  54 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  55 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  56 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  57 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  58 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  59 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  60 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  61
  62 #define CONFIG_SYS_SRIO
  63 #define CONFIG_SRIO1                    /* SRIO port 1 */
  64 #define CONFIG_SRIO2                    /* SRIO port 2 */
  65
  66 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  67
  68 #define CONFIG_ENV_OVERWRITE
  69
  70 #ifdef CONFIG_SYS_NO_FLASH
  71 #define CONFIG_ENV_IS_NOWHERE
  72 #else
  73 #define CONFIG_FLASH_CFI_DRIVER
  74 #define CONFIG_SYS_FLASH_CFI
  75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  76 #endif
  77
  78 #if defined(CONFIG_SPIFLASH)
  79 #define CONFIG_SYS_EXTRA_ENV_RELOC
  80 #define CONFIG_ENV_IS_IN_SPI_FLASH
  81 #define CONFIG_ENV_SPI_BUS              0
  82 #define CONFIG_ENV_SPI_CS               0
  83 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  84 #define CONFIG_ENV_SPI_MODE             0
  85 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  86 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  87 #define CONFIG_ENV_SECT_SIZE            0x10000
  88 #elif defined(CONFIG_SDCARD)
  89 #define CONFIG_SYS_EXTRA_ENV_RELOC
  90 #define CONFIG_ENV_IS_IN_MMC
  91 #define CONFIG_SYS_MMC_ENV_DEV          0
  92 #define CONFIG_ENV_SIZE                 0x2000
  93 #define CONFIG_ENV_OFFSET               (512 * 1097)
  94 #elif defined(CONFIG_NAND)
  95 #define CONFIG_SYS_EXTRA_ENV_RELOC
  96 #define CONFIG_ENV_IS_IN_NAND
  97 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  98 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
  99 #else
 100 #define CONFIG_ENV_IS_IN_FLASH
 101 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 102 #define CONFIG_ENV_SIZE         0x2000
 103 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 104 #endif
 105
 106 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 107
 108 /*
 109  * These can be toggled for performance analysis, otherwise use default.
 110  */
 111 #define CONFIG_SYS_CACHE_STASHING
 112 #define CONFIG_BACKSIDE_L2_CACHE
 113 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 114 #define CONFIG_BTB                      /* toggle branch predition */
 115 #define CONFIG_DDR_ECC
 116 #ifdef CONFIG_DDR_ECC
 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 118 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 119 #endif
 120
 121 #define CONFIG_ENABLE_36BIT_PHYS
 122
 123 #ifdef CONFIG_PHYS_64BIT
 124 #define CONFIG_ADDR_MAP
 125 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 126 #endif
 127
 128 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 129 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 130 #define CONFIG_SYS_MEMTEST_END          0x00400000
 131 #define CONFIG_SYS_ALT_MEMTEST
 132 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 133
 134 /*
 135  *  Config the L3 Cache as L3 SRAM
 136  */
 137 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 138 #ifdef CONFIG_PHYS_64BIT
 139 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 140 #else
 141 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 142 #endif
 143 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 144 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 145
 146 #ifdef CONFIG_PHYS_64BIT
 147 #define CONFIG_SYS_DCSRBAR              0xf0000000
 148 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 149 #endif
 150
 151 /* EEPROM */
 152 #define CONFIG_ID_EEPROM
 153 #define CONFIG_SYS_I2C_EEPROM_NXID
 154 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 155 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 157
 158 /*
 159  * DDR Setup
 160  */
 161 #define CONFIG_VERY_BIG_RAM
 162 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 163 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 164
 165 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 166 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 167
 168 #define CONFIG_DDR_SPD
 169 #define CONFIG_FSL_DDR3
 170
 171 #ifdef CONFIG_P3060QDS
 172 #define CONFIG_SYS_SPD_BUS_NUM  0
 173 #else
 174 #define CONFIG_SYS_SPD_BUS_NUM  1
 175 #endif
 176 #define SPD_EEPROM_ADDRESS1     0x51
 177 #define SPD_EEPROM_ADDRESS2     0x52
 178 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 179 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 180
 181 /*
 182  * Local Bus Definitions
 183  */
 184
 185 /* Set the local bus clock 1/8 of platform clock */
 186 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 187
 188 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 189 #ifdef CONFIG_PHYS_64BIT
 190 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 191 #else
 192 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 193 #endif
 194
 195 #define CONFIG_SYS_FLASH_BR_PRELIM \
 196                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 197                  | BR_PS_16 | BR_V)
 198 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 199                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 200
 201 #define CONFIG_SYS_BR1_PRELIM \
 202         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 203 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 204
 205 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 206 #ifdef CONFIG_PHYS_64BIT
 207 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 208 #else
 209 #define PIXIS_BASE_PHYS         PIXIS_BASE
 210 #endif
 211
 212 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 213 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 214
 215 #define PIXIS_LBMAP_SWITCH      7
 216 #define PIXIS_LBMAP_MASK        0xf0
 217 #define PIXIS_LBMAP_SHIFT       4
 218 #define PIXIS_LBMAP_ALTBANK     0x40
 219
 220 #define CONFIG_SYS_FLASH_QUIET_TEST
 221 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 222
 223 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 224 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 225 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 226 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 227
 228 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 229
 230 #if defined(CONFIG_RAMBOOT_PBL)
 231 #define CONFIG_SYS_RAMBOOT
 232 #endif
 233
 234 /* Nand Flash */
 235 #ifdef CONFIG_NAND_FSL_ELBC
 236 #define CONFIG_SYS_NAND_BASE            0xffa00000
 237 #ifdef CONFIG_PHYS_64BIT
 238 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 239 #else
 240 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 241 #endif
 242
 243 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 244 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 245 #define CONFIG_MTD_NAND_VERIFY_WRITE
 246 #define CONFIG_CMD_NAND
 247 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 248
 249 /* NAND flash config */
 250 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 251                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 252                                | BR_PS_8               /* Port Size = 8 bit */ \
 253                                | BR_MS_FCM             /* MSEL = FCM */ \
 254                                | BR_V)                 /* valid */
 255 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 256                                | OR_FCM_PGS            /* Large Page*/ \
 257                                | OR_FCM_CSCT \
 258                                | OR_FCM_CST \
 259                                | OR_FCM_CHT \
 260                                | OR_FCM_SCY_1 \
 261                                | OR_FCM_TRLX \
 262                                | OR_FCM_EHTR)
 263
 264 #ifdef CONFIG_NAND
 265 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 266 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 267 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 268 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 269 #else
 270 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 271 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 272 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 273 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 274 #endif
 275 #else
 276 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 277 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 278 #endif /* CONFIG_NAND_FSL_ELBC */
 279
 280 #define CONFIG_SYS_FLASH_EMPTY_INFO
 281 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 282 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 283
 284 #define CONFIG_BOARD_EARLY_INIT_F
 285 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 286 #define CONFIG_MISC_INIT_R
 287
 288 #define CONFIG_HWCONFIG
 289
 290 /* define to use L1 as initial stack */
 291 #define CONFIG_L1_INIT_RAM
 292 #define CONFIG_SYS_INIT_RAM_LOCK
 293 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 294 #ifdef CONFIG_PHYS_64BIT
 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 297 /* The assembler doesn't like typecast */
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 299         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 300           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 301 #else
 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 305 #endif
 306 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 307
 308 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 309 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 310
 311 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 312 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 313
 314 /* Serial Port - controlled on board with jumper J8
 315  * open - index 2
 316  * shorted - index 1
 317  */
 318 #define CONFIG_CONS_INDEX       1
 319 #define CONFIG_SYS_NS16550
 320 #define CONFIG_SYS_NS16550_SERIAL
 321 #define CONFIG_SYS_NS16550_REG_SIZE     1
 322 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 323
 324 #define CONFIG_SYS_BAUDRATE_TABLE       \
 325         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 326
 327 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 328 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 329 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 330 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 331
 332 /* Use the HUSH parser */
 333 #define CONFIG_SYS_HUSH_PARSER
 334 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 335
 336 /* pass open firmware flat tree */
 337 #define CONFIG_OF_LIBFDT
 338 #define CONFIG_OF_BOARD_SETUP
 339 #define CONFIG_OF_STDOUT_VIA_ALIAS
 340
 341 /* new uImage format support */
 342 #define CONFIG_FIT
 343 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 344
 345 /* I2C */
 346 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 347 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 348 #define CONFIG_I2C_MULTI_BUS
 349 #define CONFIG_I2C_CMD_TREE
 350 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 351 #define CONFIG_SYS_I2C_SLAVE            0x7F
 352 #define CONFIG_SYS_I2C_OFFSET           0x118000
 353 #define CONFIG_SYS_I2C2_OFFSET          0x118100
 354
 355 /*
 356  * RapidIO
 357  */
 358 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 359 #ifdef CONFIG_PHYS_64BIT
 360 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 361 #else
 362 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 363 #endif
 364 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 365
 366 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 367 #ifdef CONFIG_PHYS_64BIT
 368 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 369 #else
 370 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 371 #endif
 372 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 373
 374 /*
 375  * eSPI - Enhanced SPI
 376  */
 377 #define CONFIG_FSL_ESPI
 378 #define CONFIG_SPI_FLASH
 379 #define CONFIG_SPI_FLASH_SPANSION
 380 #define CONFIG_CMD_SF
 381 #define CONFIG_SF_DEFAULT_SPEED         10000000
 382 #define CONFIG_SF_DEFAULT_MODE          0
 383
 384 /*
 385  * General PCI
 386  * Memory space is mapped 1-1, but I/O space must start from 0.
 387  */
 388
 389 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 390 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 391 #ifdef CONFIG_PHYS_64BIT
 392 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 393 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 394 #else
 395 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 396 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 397 #endif
 398 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 399 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 400 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 401 #ifdef CONFIG_PHYS_64BIT
 402 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 403 #else
 404 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 405 #endif
 406 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 407
 408 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 409 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 410 #ifdef CONFIG_PHYS_64BIT
 411 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 412 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 413 #else
 414 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 415 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 416 #endif
 417 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 418 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 419 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 420 #ifdef CONFIG_PHYS_64BIT
 421 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 422 #else
 423 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 424 #endif
 425 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 426
 427 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 428 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 429 #ifdef CONFIG_PHYS_64BIT
 430 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 431 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 432 #else
 433 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 434 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 435 #endif
 436 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 437 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 438 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 439 #ifdef CONFIG_PHYS_64BIT
 440 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 441 #else
 442 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 443 #endif
 444 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 445
 446 /* controller 4, Base address 203000 */
 447 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 448 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 449 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 450 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 451 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 452 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 453
 454 /* Qman/Bman */
 455 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 456 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 457 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 458 #ifdef CONFIG_PHYS_64BIT
 459 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 460 #else
 461 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 462 #endif
 463 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 464 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 465 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 466 #ifdef CONFIG_PHYS_64BIT
 467 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 468 #else
 469 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 470 #endif
 471 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 472
 473 #define CONFIG_SYS_DPAA_FMAN
 474 #define CONFIG_SYS_DPAA_PME
 475 /* Default address of microcode for the Linux Fman driver */
 476 #if defined(CONFIG_SPIFLASH)
 477 /*
 478  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 479  * env, so we got 0x110000.
 480  */
 481 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 482 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 483 #elif defined(CONFIG_SDCARD)
 484 /*
 485  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 486  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 487  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 488  */
 489 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 490 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 491 #elif defined(CONFIG_NAND)
 492 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 493 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 494 #else
 495 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 496 #define CONFIG_SYS_QE_FMAN_FW_ADDR              0xEF000000
 497 #endif
 498 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 499 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 500
 501 #ifdef CONFIG_SYS_DPAA_FMAN
 502 #define CONFIG_FMAN_ENET
 503 #define CONFIG_PHYLIB_10G
 504 #define CONFIG_PHY_VITESSE
 505 #define CONFIG_PHY_TERANETICS
 506 #endif
 507
 508 #ifdef CONFIG_PCI
 509 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 510 #define CONFIG_E1000
 511
 512 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 513 #define CONFIG_DOS_PARTITION
 514 #endif  /* CONFIG_PCI */
 515
 516 /* SATA */
 517 #ifdef CONFIG_FSL_SATA_V2
 518 #define CONFIG_LIBATA
 519 #define CONFIG_FSL_SATA
 520
 521 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 522 #define CONFIG_SATA1
 523 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 524 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 525 #define CONFIG_SATA2
 526 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 527 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 528
 529 #define CONFIG_LBA48
 530 #define CONFIG_CMD_SATA
 531 #define CONFIG_DOS_PARTITION
 532 #define CONFIG_CMD_EXT2
 533 #endif
 534
 535 #ifdef CONFIG_FMAN_ENET
 536 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 537 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 538 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 539 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 540 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 541
 542 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 543 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 544 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 545 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 546 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 547
 548 #define CONFIG_SYS_TBIPA_VALUE  8
 549 #define CONFIG_MII              /* MII PHY management */
 550 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 551 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 552 #endif
 553
 554 /*
 555  * Environment
 556  */
 557 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 558 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 559
 560 /*
 561  * Command line configuration.
 562  */
 563 #include <config_cmd_default.h>
 564
 565 #define CONFIG_CMD_DHCP
 566 #define CONFIG_CMD_ELF
 567 #define CONFIG_CMD_ERRATA
 568 #define CONFIG_CMD_GREPENV
 569 #define CONFIG_CMD_IRQ
 570 #define CONFIG_CMD_I2C
 571 #define CONFIG_CMD_MII
 572 #define CONFIG_CMD_PING
 573 #define CONFIG_CMD_SETEXPR
 574 #define CONFIG_CMD_REGINFO
 575
 576 #ifdef CONFIG_PCI
 577 #define CONFIG_CMD_PCI
 578 #define CONFIG_CMD_NET
 579 #endif
 580
 581 /*
 582 * USB
 583 */
 584 #define CONFIG_CMD_USB
 585 #define CONFIG_USB_STORAGE
 586 #define CONFIG_USB_EHCI
 587 #define CONFIG_USB_EHCI_FSL
 588 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 589 #define CONFIG_CMD_EXT2
 590 #define CONFIG_HAS_FSL_DR_USB
 591
 592 #ifdef CONFIG_MMC
 593 #define CONFIG_FSL_ESDHC
 594 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 595 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 596 #define CONFIG_CMD_MMC
 597 #define CONFIG_GENERIC_MMC
 598 #define CONFIG_CMD_EXT2
 599 #define CONFIG_CMD_FAT
 600 #define CONFIG_DOS_PARTITION
 601 #endif
 602
 603 /*
 604  * Miscellaneous configurable options
 605  */
 606 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 607 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 608 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 609 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 610 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 611 #ifdef CONFIG_CMD_KGDB
 612 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 613 #else
 614 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 615 #endif
 616 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 617 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 618 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 619 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 620
 621 /*
 622  * For booting Linux, the board info and command line data
 623  * have to be in the first 64 MB of memory, since this is
 624  * the maximum mapped by the Linux kernel during initialization.
 625  */
 626 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 627 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 628
 629 #ifdef CONFIG_CMD_KGDB
 630 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 631 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 632 #endif
 633
 634 /*
 635  * Environment Configuration
 636  */
 637 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 638 #define CONFIG_BOOTFILE         "uImage"
 639 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 640
 641 /* default location for tftp and bootm */
 642 #define CONFIG_LOADADDR         1000000
 643
 644 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 645
 646 #define CONFIG_BAUDRATE 115200
 647
 648 #if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
 649 #define __USB_PHY_TYPE  ulpi
 650 #else
 651 #define __USB_PHY_TYPE  utmi
 652 #endif
 653
 654 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 655         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 656         "bank_intlv=cs0_cs1;"                                   \
 657         "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
 658         "netdev=eth0\0"                                         \
 659         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
 660         "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"                  \
 661         "tftpflash=tftpboot $loadaddr $uboot && "               \
 662         "protect off $ubootaddr +$filesize && "                 \
 663         "erase $ubootaddr +$filesize && "                       \
 664         "cp.b $loadaddr $ubootaddr $filesize && "               \
 665         "protect on $ubootaddr +$filesize && "                  \
 666         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 667         "consoledev=ttyS0\0"                                    \
 668         "ramdiskaddr=2000000\0"                                 \
 669         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 670         "fdtaddr=c00000\0"                                      \
 671         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 672         "bdev=sda3\0"                                           \
 673         "c=ffe\0"
 674
 675 #define CONFIG_HDBOOT                                   \
 676         "setenv bootargs root=/dev/$bdev rw "           \
 677         "console=$consoledev,$baudrate $othbootargs;"   \
 678         "tftp $loadaddr $bootfile;"                     \
 679         "tftp $fdtaddr $fdtfile;"                       \
 680         "bootm $loadaddr - $fdtaddr"
 681
 682 #define CONFIG_NFSBOOTCOMMAND                   \
 683         "setenv bootargs root=/dev/nfs rw "     \
 684         "nfsroot=$serverip:$rootpath "          \
 685         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 686         "console=$consoledev,$baudrate $othbootargs;"   \
 687         "tftp $loadaddr $bootfile;"             \
 688         "tftp $fdtaddr $fdtfile;"               \
 689         "bootm $loadaddr - $fdtaddr"
 690
 691 #define CONFIG_RAMBOOTCOMMAND                           \
 692         "setenv bootargs root=/dev/ram rw "             \
 693         "console=$consoledev,$baudrate $othbootargs;"   \
 694         "tftp $ramdiskaddr $ramdiskfile;"               \
 695         "tftp $loadaddr $bootfile;"                     \
 696         "tftp $fdtaddr $fdtfile;"                       \
 697         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 698
 699 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 700
 701 #ifdef CONFIG_SECURE_BOOT
 702 #include <asm/fsl_secure_boot.h>
 703 #endif
 704
 705 #endif  /* __CONFIG_H */