include/configs/enbw_cmc.h

   1 /*
   2  * (C) Copyright 2011
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * Based on:
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * Based on davinci_dvevm.h. Original Copyrights follow:
   9  *
  10  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * Board
  32  */
  33 #define CONFIG_DRIVER_TI_EMAC
  34 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
  35 #define CONFIG_USE_NAND
  36
  37 /*
  38  * SoC Configuration
  39  */
  40 #define CONFIG_ARM926EJS                /* arm926ejs CPU core */
  41 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
  42 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
  43 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  44 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  45 #define CONFIG_SYS_OSCIN_FREQ           24000000
  46 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  47 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  48 #define CONFIG_SYS_HZ                   1000
  49 #define CONFIG_DA850_LOWLEVEL
  50 #define CONFIG_ARCH_CPU_INIT
  51 #define CONFIG_SYS_DA850_PLL_INIT
  52 #define CONFIG_SYS_DA850_DDR_INIT
  53 #define CONFIG_DA8XX_GPIO
  54 #define CONFIG_HOSTNAME         enbw_cmc
  55
  56 #define MACH_TYPE_ENBW_CMC      3585
  57 #define CONFIG_MACH_TYPE        MACH_TYPE_ENBW_CMC
  58
  59 /*
  60  * Memory Info
  61  */
  62 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  63 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  64 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  65 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  66
  67 /* memtest start addr */
  68 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  69
  70 /* memtest will be run on 16MB */
  71 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  72
  73 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  74 #define CONFIG_STACKSIZE        (256*1024) /* regular stack */
  75
  76 /*
  77  * Serial Driver info
  78  */
  79 #define CONFIG_SYS_NS16550
  80 #define CONFIG_SYS_NS16550_SERIAL
  81 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
  82 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
  83 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
  84 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
  85 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
  86
  87 /*
  88  * I2C Configuration
  89  */
  90 #define CONFIG_HARD_I2C
  91 #define CONFIG_DRIVER_DAVINCI_I2C
  92 #define CONFIG_SYS_I2C_SPEED            80000
  93 #define CONFIG_SYS_I2C_SLAVE            10 /* Bogus, master-only in U-Boot */
  94 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
  95 #define CONFIG_CMD_I2C
  96
  97 #define CONFIG_CMD_DTT
  98 #define CONFIG_DTT_LM75
  99 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 100 #define CONFIG_SYS_DTT_MAX_TEMP 70
 101 #define CONFIG_SYS_DTT_LOW_TEMP -30
 102 #define CONFIG_SYS_DTT_HYSTERESIS       3
 103
 104 /*
 105  * Flash & Environment
 106  */
 107 #ifdef CONFIG_USE_NAND
 108 #define CONFIG_NAND_DAVINCI
 109 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 110 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 111 #define CONFIG_SYS_NAND_PAGE_2K
 112 #define CONFIG_SYS_NAND_CS              3
 113 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 114 #define CONFIG_SYS_CLE_MASK             0x10
 115 #define CONFIG_SYS_ALE_MASK             0x8
 116 #undef CONFIG_SYS_NAND_HW_ECC
 117 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 118
 119 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=davinci_nand.1"
 120 #define MTDPARTS_DEFAULT                        \
 121         "mtdparts="                             \
 122                 "physmap-flash.0:"              \
 123                         "512k(U-Boot),"         \
 124                         "64k(env1),"            \
 125                         "64k(env2),"            \
 126                         "-(rest);"              \
 127                 "davinci_nand.1:"               \
 128                         "128k(dtb),"            \
 129                         "3m(kernel),"           \
 130                         "4m(rootfs),"           \
 131                         "-(userfs)"
 132
 133
 134 #define CONFIG_CMD_MTDPARTS
 135
 136 #endif
 137
 138 /*
 139  * Network & Ethernet Configuration
 140  */
 141 #ifdef CONFIG_DRIVER_TI_EMAC
 142 #define CONFIG_MII
 143 #define CONFIG_BOOTP_DEFAULT
 144 #define CONFIG_BOOTP_DNS
 145 #define CONFIG_BOOTP_DNS2
 146 #define CONFIG_BOOTP_SEND_HOSTNAME
 147 #define CONFIG_NET_RETRY_COUNT  10
 148 #endif
 149
 150 /*
 151  * Flash configuration
 152  */
 153 #define CONFIG_SYS_FLASH_CFI
 154 #define CONFIG_FLASH_CFI_DRIVER
 155 #define CONFIG_FLASH_CFI_MTD
 156 #define CONFIG_SYS_FLASH_BASE           0x60000000
 157 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 159 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 160 #define CONFIG_SYS_MAX_FLASH_SECT       128
 161 #define CONFIG_FLASH_16BIT              /* Flash is 16-bit */
 162
 163 #define CONFIG_CMD_FLASH
 164
 165 #define CONFIG_ENV_IS_IN_FLASH
 166 #define CONFIG_SYS_MONITOR_LEN  0x80000
 167 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + \
 168                                         CONFIG_SYS_MONITOR_LEN)
 169 #define CONFIG_ENV_SECT_SIZE    (64 << 10)
 170 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
 171 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + \
 172                                         CONFIG_ENV_SECT_SIZE)
 173 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 174 #undef CONFIG_ENV_IS_IN_NAND
 175 #define CONFIG_DEFAULT_SETTINGS_ADDR    (CONFIG_ENV_ADDR_REDUND + \
 176                                                 CONFIG_ENV_SECT_SIZE)
 177
 178 #define xstr(s) str(s)
 179 #define str(s)  #s
 180
 181 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 182         "u-boot_addr_r=c0000000\0"                                      \
 183         "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"                 \
 184         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 185         "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
 186                 "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"   \
 187                 "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE)    \
 188                 " ${filesize};"                                         \
 189                 "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
 190         "netdev=eth0\0"                                                 \
 191         "rootpath=/opt/eldk-arm/arm\0"                                  \
 192         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 193                 "nfsroot=${serverip}:${rootpath}\0"                     \
 194         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 195         "addip=setenv bootargs ${bootargs} "                            \
 196                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 197                 ":${hostname}:${netdev}:off panic=1\0"                  \
 198         "kernel_addr_r=c0700000\0"                                      \
 199         "fdt_addr_r=c0600000\0"                                         \
 200         "ramdisk_addr_r=c0b00000\0"                                     \
 201         "fdt_file=" xstr(CONFIG_HOSTNAME) "/"                           \
 202                 xstr(CONFIG_HOSTNAME) ".dtb\0"                          \
 203         "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0"               \
 204         "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0"    \
 205         "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0"      \
 206         "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0"                  \
 207         "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0"            \
 208         "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0"                     \
 209         "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0"     \
 210         "addcon=setenv bootargs ${bootargs} console=ttyS2,"             \
 211                 "${baudrate}n8\0"                                       \
 212         "net_nfs=run load_fdt load_kernel; "                            \
 213                 "run nfsargs addip addcon addmtd addmisc;"              \
 214                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 215         "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
 216                 "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"    \
 217         "bootcmd=run net_nfs\0"                                         \
 218         "machid=e01\0"                                                  \
 219         "key_cmd_0=echo key:   0\0"                                     \
 220         "key_cmd_1=echo key:   1\0"                                     \
 221         "key_cmd_2=echo key:   2\0"                                     \
 222         "key_cmd_3=echo key:   3\0"                                     \
 223         "key_magic_0=0\0"                                               \
 224         "key_magic_1=1\0"                                               \
 225         "key_magic_2=2\0"                                               \
 226         "key_magic_3=3\0"                                               \
 227         "magic_keys=0123\0"                                             \
 228         "hwconfig=switch:lan=on,pwl=off\0"                              \
 229         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 230         "addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0"   \
 231         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 232         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 233         "logversion=2\0"                                                \
 234         "\0"
 235
 236 /*
 237  * U-Boot general configuration
 238  */
 239 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 240 #define CONFIG_SYS_PROMPT       "=> " /* Command Prompt */
 241 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 242 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 243 #define CONFIG_SYS_MAXARGS      16 /* max number of command args */
 244 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 245 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 246 #define CONFIG_VERSION_VARIABLE
 247 #define CONFIG_AUTO_COMPLETE
 248 #define CONFIG_SYS_HUSH_PARSER
 249 #define CONFIG_CMDLINE_EDITING
 250 #define CONFIG_SYS_LONGHELP
 251 #define CONFIG_CRC32_VERIFY
 252 #define CONFIG_MX_CYCLIC
 253 #define CONFIG_BOOTDELAY        3
 254 #define CONFIG_HWCONFIG
 255 #define CONFIG_SHOW_BOOT_PROGRESS
 256 #define CONFIG_BOARD_LATE_INIT
 257
 258 /*
 259  * U-Boot commands
 260  */
 261 #include <config_cmd_default.h>
 262 #define CONFIG_CMD_ENV
 263 #define CONFIG_CMD_ASKENV
 264 #define CONFIG_CMD_DHCP
 265 #define CONFIG_CMD_DIAG
 266 #define CONFIG_CMD_MII
 267 #define CONFIG_CMD_PING
 268 #define CONFIG_CMD_SAVES
 269 #define CONFIG_CMD_MEMORY
 270 #define CONFIG_CMD_CACHE
 271
 272 #ifdef CONFIG_CMD_BDI
 273 #define CONFIG_CLOCKS
 274 #endif
 275
 276 #ifndef CONFIG_DRIVER_TI_EMAC
 277 #undef CONFIG_CMD_NET
 278 #undef CONFIG_CMD_DHCP
 279 #undef CONFIG_CMD_MII
 280 #undef CONFIG_CMD_PING
 281 #endif
 282
 283 #ifdef CONFIG_USE_NAND
 284 #undef CONFIG_CMD_IMLS
 285 #define CONFIG_CMD_NAND
 286
 287 #define CONFIG_CMD_MTDPARTS
 288 #define CONFIG_MTD_DEVICE
 289 #define CONFIG_MTD_PARTITIONS
 290 #define CONFIG_LZO
 291 #define CONFIG_RBTREE
 292 #define CONFIG_CMD_UBI
 293 #define CONFIG_CMD_UBIFS
 294 #endif
 295
 296 #if !defined(CONFIG_USE_NAND) && \
 297         !defined(CONFIG_USE_NOR) && \
 298         !defined(CONFIG_USE_SPIFLASH)
 299 #define CONFIG_ENV_IS_NOWHERE
 300 #define CONFIG_SYS_NO_FLASH
 301 #define CONFIG_ENV_SIZE         (16 << 10)
 302 #undef CONFIG_CMD_IMLS
 303 #undef CONFIG_CMD_ENV
 304 #endif
 305
 306 #define CONFIG_SYS_TEXT_BASE            0x60000000
 307 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 308 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 309 #define CONFIG_SYS_INIT_SP_ADDR         (0x8001ff00)
 310
 311 #define CONFIG_VERSION_VARIABLE
 312 #define CONFIG_ENV_OVERWRITE
 313
 314 #define CONFIG_PREBOOT  "echo;" \
 315         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 316         "echo"
 317 #define CONFIG_MISC_INIT_R
 318
 319 #define CONFIG_CMC_RESET_PIN    0x04000000
 320 #define CONFIG_CMC_RESET_TIMEOUT        3
 321
 322 #define CONFIG_HW_WATCHDOG
 323 #define CONFIG_SYS_WDTTIMERBASE         DAVINCI_TIMER1_BASE
 324 #define CONFIG_SYS_WDT_PERIOD_LOW       0x0c000000
 325 #define CONFIG_SYS_WDT_PERIOD_HIGH      0x0
 326
 327 #define CONFIG_CMD_DATE
 328 #define CONFIG_RTC_DAVINCI
 329
 330 /* SD/MMC */
 331 #define CONFIG_MMC
 332 #define CONFIG_GENERIC_MMC
 333 #define CONFIG_DAVINCI_MMC
 334 #define CONFIG_MMC_MBLOCK
 335 #define CONFIG_DOS_PARTITION
 336 #define CONFIG_CMD_FAT
 337 #define CONFIG_CMD_MMC
 338
 339
 340 /* FDT support */
 341 #define CONFIG_OF_LIBFDT
 342
 343 /* LowLevel Init */
 344 /* PLL */
 345 #define CONFIG_SYS_DV_CLKMODE           0
 346 #define CONFIG_SYS_DA850_PLL0_POSTDIV   0
 347 #define CONFIG_SYS_DA850_PLL0_PLLDIV1   0x8000
 348 #define CONFIG_SYS_DA850_PLL0_PLLDIV2   0x8001
 349 #define CONFIG_SYS_DA850_PLL0_PLLDIV3   0x8002 /* 150MHz */
 350 #define CONFIG_SYS_DA850_PLL0_PLLDIV4   0x8003
 351 #define CONFIG_SYS_DA850_PLL0_PLLDIV5   0x8002
 352 #define CONFIG_SYS_DA850_PLL0_PLLDIV6   CONFIG_SYS_DA850_PLL0_PLLDIV1
 353 #define CONFIG_SYS_DA850_PLL0_PLLDIV7   0x8005
 354
 355 #define CONFIG_SYS_DA850_PLL1_POSTDIV   1
 356 #define CONFIG_SYS_DA850_PLL1_PLLDIV1   0x8000
 357 #define CONFIG_SYS_DA850_PLL1_PLLDIV2   0x8001
 358 #define CONFIG_SYS_DA850_PLL1_PLLDIV3   0x8002
 359
 360 #define CONFIG_SYS_DA850_PLL0_PLLM      18      /* PLL0 -> 456 MHz */
 361 #define CONFIG_SYS_DA850_PLL1_PLLM      24      /* PLL1 -> 300 MHz */
 362
 363 /* DDR RAM */
 364 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
 365                         DV_DDR_PHY_EXT_STRBEN   | \
 366                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 367
 368 #define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
 369                   (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
 370                   (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
 371                   (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
 372                   (0x1 << DV_DDR_SDCR_DDREN_SHIFT)      | \
 373                   (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT)    | \
 374                   (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)  | \
 375                   (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)  | \
 376                   (0x3 << DV_DDR_SDCR_CL_SHIFT)         | \
 377                   (0x2 << DV_DDR_SDCR_IBANK_SHIFT)              | \
 378                   (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 379
 380 #define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
 381
 382 /*
 383  * freq = 150MHz -> t = 7ns
 384  */
 385 #define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
 386                 (0x0d << DV_DDR_SDTMR1_RFC_SHIFT)       | \
 387                 (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
 388                 (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
 389                 (1 << DV_DDR_SDTMR1_WR_SHIFT)           | \
 390                 (5 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
 391                 (7 << DV_DDR_SDTMR1_RC_SHIFT)           | \
 392                 (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
 393                 (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) |  /* Reserved */ \
 394                 ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
 395
 396 /*
 397  * freq = 150MHz -> t=7ns
 398  */
 399 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
 400         (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
 401         (8 << DV_DDR_SDTMR2_RASMAX_SHIFT)               | \
 402         (2 << DV_DDR_SDTMR2_XP_SHIFT)                   | \
 403         (0 << DV_DDR_SDTMR2_ODT_SHIFT)                  | \
 404         (15 << DV_DDR_SDTMR2_XSNR_SHIFT)                | \
 405         (27 << DV_DDR_SDTMR2_XSRD_SHIFT)                | \
 406         (0 << DV_DDR_SDTMR2_RTP_SHIFT)                  | \
 407         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
 408
 409 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x00000407
 410 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x30
 411 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
 412                                         DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
 413                                         DAVINCI_SYSCFG_SUSPSRC_UART2 | \
 414                                         DAVINCI_SYSCFG_SUSPSRC_EMAC |\
 415                                         DAVINCI_SYSCFG_SUSPSRC_I2C)
 416
 417 #define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
 418                                 DAVINCI_ABCR_WSTROBE(6) | \
 419                                 DAVINCI_ABCR_WHOLD(1)   | \
 420                                 DAVINCI_ABCR_RSETUP(2)  | \
 421                                 DAVINCI_ABCR_RSTROBE(6) | \
 422                                 DAVINCI_ABCR_RHOLD(1)   | \
 423                                 DAVINCI_ABCR_ASIZE_16BIT)
 424
 425 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
 426                                 DAVINCI_ABCR_WSTROBE(2) | \
 427                                 DAVINCI_ABCR_WHOLD(1)   | \
 428                                 DAVINCI_ABCR_RSETUP(1)  | \
 429                                 DAVINCI_ABCR_RSTROBE(6) | \
 430                                 DAVINCI_ABCR_RHOLD(1)   | \
 431                                 DAVINCI_ABCR_ASIZE_8BIT)
 432
 433 /*
 434  * NOR Bootconfiguration word:
 435  * Method: Direc boot
 436  * EMIFA access mode: 16 Bit
 437  */
 438 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
 439
 440 #define CONFIG_POST     (CONFIG_SYS_POST_MEMORY)
 441 #define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
 442 #define CONFIG_LOGBUFFER
 443 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 444
 445 #define CONFIG_BOOTCOUNT_LIMIT
 446 #define CONFIG_SYS_BOOTCOUNT_ADDR       DAVINCI_RTC_BASE
 447
 448 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc0080000
 449 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x60004000
 450 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x70000
 451 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 452 #endif /* __CONFIG_H */