include/configs/katmai.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************
  27  * katmai.h - configuration for AMCC Katmai (440SPe)
  28  ***********************************************************************/
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*-----------------------------------------------------------------------
  34  * High Level Configuration Options
  35  *----------------------------------------------------------------------*/
  36 #define CONFIG_KATMAI                   1       /* Board is Katmai      */
  37 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
  38 #define CONFIG_440                      1       /* ... PPC440 family    */
  39 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  40 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  41 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  42 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
  43
  44 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  45
  46 /*
  47  * Enable this board for more than 2GB of SDRAM
  48  */
  49 #define CONFIG_PHYS_64BIT
  50 #define CONFIG_VERY_BIG_RAM
  51
  52 /*
  53  * Include common defines/options for all AMCC eval boards
  54  */
  55 #define CONFIG_HOSTNAME         katmai
  56 #include "amcc-common.h"
  57
  58 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
  59 #undef  CONFIG_SHOW_BOOT_PROGRESS
  60
  61 /*-----------------------------------------------------------------------
  62  * Base addresses -- Note these are effective addresses where the
  63  * actual resources get mapped (not physical addresses)
  64  *----------------------------------------------------------------------*/
  65 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
  66 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  67
  68 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  69 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  70 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  71
  72 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  73 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  74 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  75
  76 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  77 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  78 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  79 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  80 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  81 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  82
  83 /* base address of inbound PCIe window */
  84 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
  85
  86 /* System RAM mapped to PCI space */
  87 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  88 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  89 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  90
  91 #define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
  92
  93 /*-----------------------------------------------------------------------
  94  * Initial RAM & stack pointer (placed in internal SRAM)
  95  *----------------------------------------------------------------------*/
  96 #define CONFIG_SYS_TEMP_STACK_OCM       1
  97 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
  98 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
  99 #define CONFIG_SYS_INIT_RAM_END 0x2000          /* End of used area in RAM */
 100 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 101
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 103 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 104
 105 /*-----------------------------------------------------------------------
 106  * Serial Port
 107  *----------------------------------------------------------------------*/
 108 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 109 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 110
 111 /*-----------------------------------------------------------------------
 112  * DDR SDRAM
 113  *----------------------------------------------------------------------*/
 114 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 115 #define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
 116 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 117 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
 118 #undef  CONFIG_STRESS
 119
 120 /*-----------------------------------------------------------------------
 121  * I2C
 122  *----------------------------------------------------------------------*/
 123 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 124
 125 #define CONFIG_I2C_MULTI_BUS
 126 #define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
 127
 128 #define IIC0_BOOTPROM_ADDR      0x50
 129 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 130
 131 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 132 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
 133 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 135 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 136
 137 /* I2C bootstrap EEPROM */
 138 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 139 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 140 #define CONFIG_4xx_CONFIG_BLOCKSIZE             8
 141
 142 /* I2C RTC */
 143 #define CONFIG_RTC_M41T11       1
 144 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
 145 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 146 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
 147
 148 /* I2C DTT */
 149 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
 150 #define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
 151 /*
 152  * standard dtt sensor configuration - bottom bit will determine local or
 153  * remote sensor of the ADM1021, the rest determines index into
 154  * CONFIG_SYS_DTT_ADM1021 array below.
 155  */
 156 #define CONFIG_DTT_SENSORS      { 0, 1 }
 157
 158 /*
 159  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 160  * there will be one entry in this array for each two (dummy) sensors in
 161  * CONFIG_DTT_SENSORS.
 162  *
 163  * For Katmai board:
 164  * - only one ADM1021
 165  * - i2c addr 0x18
 166  * - conversion rate 0x02 = 0.25 conversions/second
 167  * - ALERT ouput disabled
 168  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 169  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 170  */
 171 #define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 172
 173 /*-----------------------------------------------------------------------
 174  * Environment
 175  *----------------------------------------------------------------------*/
 176 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 177
 178 /*
 179  * Default environment variables
 180  */
 181 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 182         CONFIG_AMCC_DEF_ENV                                             \
 183         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 184         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 185         "kernel_addr=ff000000\0"                                        \
 186         "fdt_addr=ff1e0000\0"                                           \
 187         "ramdisk_addr=ff200000\0"                                       \
 188         "pciconfighost=1\0"                                             \
 189         "pcie_mode=RP:RP:RP\0"                                          \
 190         ""
 191
 192 /*
 193  * Commands additional to the ones defined in amcc-common.h
 194  */
 195 #define CONFIG_CMD_CHIP_CONFIG
 196 #define CONFIG_CMD_DATE
 197 #define CONFIG_CMD_ECCTEST
 198 #define CONFIG_CMD_EXT2
 199 #define CONFIG_CMD_FAT
 200 #define CONFIG_CMD_PCI
 201 #define CONFIG_CMD_SDRAM
 202 #define CONFIG_CMD_SNTP
 203
 204 #define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
 205 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 206 #define CONFIG_HAS_ETH0
 207 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 208 #define CONFIG_PHY_RESET_DELAY  1000
 209 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 210 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 211
 212 /*-----------------------------------------------------------------------
 213  * FLASH related
 214  *----------------------------------------------------------------------*/
 215 #define CONFIG_SYS_FLASH_CFI
 216 #define CONFIG_FLASH_CFI_DRIVER
 217 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 218 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 219
 220 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 221 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
 222 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
 223
 224 #undef  CONFIG_SYS_FLASH_CHECKSUM
 225 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 226 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 227
 228 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 229 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 230 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 231
 232 /* Address and size of Redundant Environment Sector     */
 233 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 234 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 235
 236 /*-----------------------------------------------------------------------
 237  * PCI stuff
 238  *-----------------------------------------------------------------------
 239  */
 240 /* General PCI */
 241 #define CONFIG_PCI                      /* include pci support          */
 242 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 243 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 244 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 245
 246 /* Board-specific PCI */
 247 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 248 #undef  CONFIG_SYS_PCI_MASTER_INIT
 249
 250 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 251 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 252 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 253
 254 /*
 255  *  NETWORK Support (PCI):
 256  */
 257 /* Support for Intel 82557/82559/82559ER chips. */
 258 #define CONFIG_EEPRO100
 259
 260 /*-----------------------------------------------------------------------
 261  * Xilinx System ACE support
 262  *----------------------------------------------------------------------*/
 263 #define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
 264 #define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
 265 #define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
 266 #define CONFIG_DOS_PARTITION    1
 267
 268 /*-----------------------------------------------------------------------
 269  * External Bus Controller (EBC) Setup
 270  *----------------------------------------------------------------------*/
 271
 272 /* Memory Bank 0 (Flash) initialization                                 */
 273 #define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
 274                                  EBC_BXAP_TWT_ENCODE(7)     |           \
 275                                  EBC_BXAP_BCE_DISABLE       |           \
 276                                  EBC_BXAP_BCT_2TRANS        |           \
 277                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 278                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 279                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 280                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 281                                  EBC_BXAP_TH_ENCODE(0)      |           \
 282                                  EBC_BXAP_RE_DISABLED       |           \
 283                                  EBC_BXAP_SOR_DELAYED       |           \
 284                                  EBC_BXAP_BEM_WRITEONLY     |           \
 285                                  EBC_BXAP_PEN_DISABLED)
 286 #define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
 287                                  EBC_BXCR_BS_16MB                    |  \
 288                                  EBC_BXCR_BU_RW                      |  \
 289                                  EBC_BXCR_BW_16BIT)
 290
 291 /* Memory Bank 1 (Xilinx System ACE controller) initialization          */
 292 #define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
 293                                  EBC_BXAP_TWT_ENCODE(4)     |           \
 294                                  EBC_BXAP_BCE_DISABLE       |           \
 295                                  EBC_BXAP_BCT_2TRANS        |           \
 296                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 297                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 298                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 299                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 300                                  EBC_BXAP_TH_ENCODE(0)      |           \
 301                                  EBC_BXAP_RE_DISABLED       |           \
 302                                  EBC_BXAP_SOR_NONDELAYED    |           \
 303                                  EBC_BXAP_BEM_WRITEONLY     |           \
 304                                  EBC_BXAP_PEN_DISABLED)
 305 #define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
 306                                  EBC_BXCR_BS_1MB                    |   \
 307                                  EBC_BXCR_BU_RW                     |   \
 308                                  EBC_BXCR_BW_16BIT)
 309
 310 /*-------------------------------------------------------------------------
 311  * Initialize EBC CONFIG -
 312  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 313  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 314  *-------------------------------------------------------------------------*/
 315 #define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
 316                                  EBC_CFG_PTD_ENABLE   | \
 317                                  EBC_CFG_RTC_16PERCLK | \
 318                                  EBC_CFG_ATC_PREVIOUS | \
 319                                  EBC_CFG_DTC_PREVIOUS | \
 320                                  EBC_CFG_CTC_PREVIOUS | \
 321                                  EBC_CFG_OEO_PREVIOUS | \
 322                                  EBC_CFG_EMC_DEFAULT  | \
 323                                  EBC_CFG_PME_DISABLE  | \
 324                                  EBC_CFG_PR_16)
 325
 326 /*-----------------------------------------------------------------------
 327  * GPIO Setup
 328  *----------------------------------------------------------------------*/
 329 #define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
 330 #define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
 331 #define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
 332 #define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
 333
 334 #define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 335                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 336                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 337                                  GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 338 #define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 339 #define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 340 #define CONFIG_SYS_GPIO_ODR             0
 341
 342 #endif  /* __CONFIG_H */