include/configs/km/km83xx-common.h

   1 /*
   2  * (C) Copyright 2010
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  */
  10
  11 #ifndef __CONFIG_KM83XX_H
  12 #define __CONFIG_KM83XX_H
  13
  14 /* include common defines/options for all Keymile boards */
  15 #include "keymile-common.h"
  16 #include "km-powerpc.h"
  17
  18 #define MTDIDS_DEFAULT          "nor0=boot"
  19 #define MTDPARTS_DEFAULT        "mtdparts="                     \
  20         "boot:"                                                 \
  21                 "768k(u-boot),"                                 \
  22                 "128k(env),"                                    \
  23                 "128k(envred),"                                 \
  24                 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
  25
  26 #define CONFIG_MISC_INIT_R
  27 /*
  28  * System Clock Setup
  29  */
  30 #define CONFIG_83XX_CLKIN               66000000
  31 #define CONFIG_SYS_CLK_FREQ             66000000
  32 #define CONFIG_83XX_PCICLK              66000000
  33
  34 /*
  35  * IMMR new address
  36  */
  37 #define CONFIG_SYS_IMMR         0xE0000000
  38
  39 /*
  40  * Bus Arbitration Configuration Register (ACR)
  41  */
  42 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  43 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  44 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  45 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  46
  47 /*
  48  * DDR Setup
  49  */
  50 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  51 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  52 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  53 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  54                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  55
  56 #define CFG_83XX_DDR_USES_CS0
  57
  58 /*
  59  * Manually set up DDR parameters
  60  */
  61 #define CONFIG_DDR_II
  62 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  63
  64 /*
  65  * The reserved memory
  66  */
  67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  68 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  69
  70 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  71 #define CONFIG_SYS_RAMBOOT
  72 #endif
  73
  74 /* Reserve 768 kB for Mon */
  75 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  76
  77 /*
  78  * Initial RAM Base Address Setup
  79  */
  80 #define CONFIG_SYS_INIT_RAM_LOCK
  81 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  82 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  83 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
  84 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  85                                                 GENERATED_GBL_DATA_SIZE)
  86
  87 /*
  88  * Init Local Bus Memory Controller:
  89  *
  90  * Bank Bus     Machine PortSz  Size  Device
  91  * ---- ---     ------- ------  -----  ------
  92  *  0   Local   GPCM    16 bit  256MB FLASH
  93  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
  94  *
  95  */
  96 /*
  97  * FLASH on the Local Bus
  98  */
  99 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 100 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 101 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 102 #define CONFIG_SYS_FLASH_PROTECTION
 103 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 104
 105 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 106 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 107
 108 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 109                                 BR_PS_16 | /* 16 bit port size */ \
 110                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 111                                 BR_V)
 112
 113 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 114                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 115                                 OR_GPCM_SCY_5 | \
 116                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 117
 118 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 119 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 120 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 121
 122 /*
 123  * PRIO1/PIGGY on the local bus CS1
 124  */
 125 /* Window base at flash base */
 126 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 127 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 128
 129 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 130                                 BR_PS_8 | /* 8 bit port size */ \
 131                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 132                                 BR_V)
 133 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 134                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 135                                 OR_GPCM_SCY_2 | \
 136                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 137
 138 /*
 139  * Serial Port
 140  */
 141 #define CONFIG_CONS_INDEX       1
 142 #define CONFIG_SYS_NS16550
 143 #define CONFIG_SYS_NS16550_SERIAL
 144 #define CONFIG_SYS_NS16550_REG_SIZE     1
 145 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 146
 147 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 148 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 149
 150 /* Pass open firmware flat tree */
 151 #define CONFIG_OF_LIBFDT
 152 #define CONFIG_OF_BOARD_SETUP
 153 #define CONFIG_OF_STDOUT_VIA_ALIAS
 154
 155 /*
 156  * QE UEC ethernet configuration
 157  */
 158 #define CONFIG_UEC_ETH
 159 #define CONFIG_ETHPRIME         "UEC0"
 160
 161 #define CONFIG_UEC_ETH1         /* GETH1 */
 162 #define UEC_VERBOSE_DEBUG       1
 163
 164 #ifdef CONFIG_UEC_ETH1
 165 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 166 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 167 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 168 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 169 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 170 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 171 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 172 #endif
 173
 174 /*
 175  * Environment
 176  */
 177
 178 #ifndef CONFIG_SYS_RAMBOOT
 179 #define CONFIG_ENV_IS_IN_FLASH
 180 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 181                                         CONFIG_SYS_MONITOR_LEN)
 182 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 183 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 184
 185 /* Address and size of Redundant Environment Sector     */
 186 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 187                                                 CONFIG_ENV_SECT_SIZE)
 188 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 189
 190 #else /* CFG_SYS_RAMBOOT */
 191 #define CONFIG_SYS_NO_FLASH             /* Flash is not usable now */
 192 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 193 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 194 #define CONFIG_ENV_SIZE         0x2000
 195 #endif /* CFG_SYS_RAMBOOT */
 196
 197 /* I2C */
 198 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 199 #define CONFIG_FSL_I2C
 200 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 201 #define CONFIG_SYS_I2C_SLAVE    0x7F
 202 #define CONFIG_SYS_I2C_OFFSET   0x3000
 203
 204 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
 205 #define CONFIG_DTT_LM75         /* ON Semi's LM75 */
 206 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses */
 207 #define CONFIG_SYS_DTT_MAX_TEMP 70
 208 #define CONFIG_SYS_DTT_LOW_TEMP -30
 209 #define CONFIG_SYS_DTT_HYSTERESIS       3
 210 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 211
 212 #if defined(CONFIG_CMD_NAND)
 213 #define CONFIG_NAND_KMETER1
 214 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 215 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 216 #endif
 217
 218 #if defined(CONFIG_PCI)
 219 #define CONFIG_CMD_PCI
 220 #endif
 221
 222 /*
 223  * For booting Linux, the board info and command line data
 224  * have to be in the first 8 MB of memory, since this is
 225  * the maximum mapped by the Linux kernel during initialization.
 226  */
 227 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 228
 229 /*
 230  * Core HID Setup
 231  */
 232 #define CONFIG_SYS_HID0_INIT            0x000000000
 233 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 234                                          HID0_ENABLE_INSTRUCTION_CACHE)
 235 #define CONFIG_SYS_HID2                 HID2_HBE
 236
 237 /*
 238  * MMU Setup
 239  */
 240
 241 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 242
 243 /* DDR: cache cacheable */
 244 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 245                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 246 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 247                                         BATU_VS | BATU_VP)
 248 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 249 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 250
 251 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 252 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 253                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 254 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 255                                         | BATU_VP)
 256 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 257 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 258
 259 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 260 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 261                                 BATL_MEMCOHERENCE)
 262 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 263                                 BATU_VS | BATU_VP)
 264 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 265                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 266 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 267
 268 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 269 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 270                                         BATL_MEMCOHERENCE)
 271 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 272                                         BATU_VS | BATU_VP)
 273 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 274                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 275 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 276
 277 /* Stack in dcache: cacheable, no memory coherence */
 278 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 279 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 280                                         BATU_VS | BATU_VP)
 281 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 282 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 283
 284 /*
 285  * Internal Definitions
 286  */
 287 #define BOOTFLASH_START 0xF0000000
 288
 289 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 290
 291 /*
 292  * Environment Configuration
 293  */
 294 #define CONFIG_ENV_OVERWRITE
 295 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 296 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 297 #endif
 298
 299 #ifndef CONFIG_KM_DEF_ARCH
 300 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 301 #endif
 302
 303 #define CONFIG_EXTRA_ENV_SETTINGS \
 304         CONFIG_KM_DEF_ENV                                               \
 305         CONFIG_KM_DEF_ARCH                                              \
 306         "dtt_bus=pca9547:70:a\0"                                        \
 307         "EEprom_ivm=pca9547:70:9\0"                                     \
 308         "newenv="                                                       \
 309                 "prot off 0xF00C0000 +0x40000 && "                      \
 310                 "era 0xF00C0000 +0x40000\0"                             \
 311         "unlock=yes\0"                                                  \
 312         ""
 313
 314 #if defined(CONFIG_UEC_ETH)
 315 #define CONFIG_HAS_ETH0
 316 #endif
 317
 318 #endif /* __CONFIG_KM83XX_H */