include/configs/km/kmp204x-common.h

   1 /*
   2  * (C) Copyright 2013 Keymile AG
   3  * Valentin Longchamp <valentin.longchamp@keymile.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _CONFIG_KMP204X_H
   9 #define _CONFIG_KMP204X_H
  10
  11 #define CONFIG_PHYS_64BIT
  12 #define CONFIG_PPC_P2041
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  15
  16 #define CONFIG_KM_DEF_NETDEV    "netdev=eth0\0"
  17
  18 #define CONFIG_NAND_ECC_BCH
  19
  20 /* common KM defines */
  21 #include "keymile-common.h"
  22
  23 #define CONFIG_SYS_RAMBOOT
  24 #define CONFIG_RAMBOOT_PBL
  25 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  26 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  27 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
  28 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE
  32 #define CONFIG_E500                     /* BOOKE e500 family */
  33 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  34 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  35 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  36 #define CONFIG_MP                       /* support multiple processors */
  37
  38 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  39 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  40 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  41 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  42 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  43 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  44 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  45 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  46
  47 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  48
  49 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  50
  51 /* Environment in SPI Flash */
  52 #define CONFIG_SYS_EXTRA_ENV_RELOC
  53 #define CONFIG_ENV_IS_IN_SPI_FLASH
  54 #define CONFIG_ENV_SPI_BUS              0
  55 #define CONFIG_ENV_SPI_CS               0
  56 #define CONFIG_ENV_SPI_MAX_HZ           20000000
  57 #define CONFIG_ENV_SPI_MODE             0
  58 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB for u-boot */
  59 #define CONFIG_ENV_SIZE                 0x004000        /* 16K env */
  60 #define CONFIG_ENV_SECT_SIZE            0x010000
  61 #define CONFIG_ENV_OFFSET_REDUND        0x110000
  62 #define CONFIG_ENV_TOTAL_SIZE           0x020000
  63
  64 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  65
  66 #ifndef __ASSEMBLY__
  67 unsigned long get_board_sys_clk(unsigned long dummy);
  68 #endif
  69 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  70
  71 /*
  72  * These can be toggled for performance analysis, otherwise use default.
  73  */
  74 #define CONFIG_SYS_CACHE_STASHING
  75 #define CONFIG_BACKSIDE_L2_CACHE
  76 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  77 #define CONFIG_BTB                      /* toggle branch predition */
  78
  79 #define CONFIG_ENABLE_36BIT_PHYS
  80
  81 #define CONFIG_ADDR_MAP
  82 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  83
  84 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  85 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
  86 #define CONFIG_SYS_MEMTEST_END          0x00800000
  87 #define CONFIG_SYS_ALT_MEMTEST
  88 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  89
  90 /*
  91  *  Config the L3 Cache as L3 SRAM
  92  */
  93 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  94 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  95                 CONFIG_RAMBOOT_TEXT_BASE)
  96 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  97 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  98
  99 #define CONFIG_SYS_DCSRBAR              0xf0000000
 100 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 101
 102 /*
 103  * DDR Setup
 104  */
 105 #define CONFIG_VERY_BIG_RAM
 106 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 107 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 108
 109 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 110 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 111
 112 #define CONFIG_DDR_SPD
 113 #define CONFIG_SYS_FSL_DDR3
 114 #define CONFIG_FSL_DDR_INTERACTIVE
 115
 116 #define CONFIG_SYS_SPD_BUS_NUM  0
 117 #define SPD_EEPROM_ADDRESS      0x54
 118 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 119
 120 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 122
 123 /******************************************************************************
 124  * (PRAM usage)
 125  * ... -------------------------------------------------------
 126  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 127  * ... |<------------------- pram -------------------------->|
 128  * ... -------------------------------------------------------
 129  * @END_OF_RAM:
 130  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 131  * @CONFIG_KM_PHRAM: address for /var
 132  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 133  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
 134  */
 135
 136 /* size of rootfs in RAM */
 137 #define CONFIG_KM_ROOTFSSIZE    0x0
 138 /* pseudo-non volatile RAM [hex] */
 139 #define CONFIG_KM_PNVRAM        0x80000
 140 /* physical RAM MTD size [hex] */
 141 #define CONFIG_KM_PHRAM         0x100000
 142 /* resereved pram area at the end of memroy [hex] */
 143 #define CONFIG_KM_RESERVED_PRAM 0x0
 144 /* enable protected RAM */
 145 #define CONFIG_PRAM             0
 146
 147 #define CONFIG_KM_CRAMFS_ADDR   0x2000000
 148 #define CONFIG_KM_KERNEL_ADDR   0x1000000       /* max kernel size 15.5Mbytes */
 149 #define CONFIG_KM_FDT_ADDR      0x1F80000       /* max dtb    size  0.5Mbytes */
 150
 151 /*
 152  * Local Bus Definitions
 153  */
 154
 155 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
 156 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_8 | LCRR_EADC_2)
 157
 158 /* Nand Flash */
 159 #define CONFIG_NAND_FSL_ELBC
 160 #define CONFIG_SYS_NAND_BASE            0xffa00000
 161 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 162
 163 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 164 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 165 #define CONFIG_MTD_NAND_VERIFY_WRITE
 166 #define CONFIG_CMD_NAND
 167 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 168
 169 #define CONFIG_BCH
 170
 171 /* NAND flash config */
 172 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 173                                | BR_PS_8               /* Port Size = 8 bit */ \
 174                                | BR_MS_FCM             /* MSEL = FCM */ \
 175                                | BR_V)                 /* valid */
 176
 177 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB       /* length 256K */ \
 178                                | OR_FCM_BCTLD   /* LBCTL not ass */     \
 179                                | OR_FCM_SCY_1   /* 1 clk wait cycle */  \
 180                                | OR_FCM_RST     /* 1 clk read setup */  \
 181                                | OR_FCM_PGS     /* Large page size */   \
 182                                | OR_FCM_CST)    /* 0.25 command setup */
 183
 184 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 185 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 186
 187 /* QRIO FPGA */
 188 #define CONFIG_SYS_QRIO_BASE            0xfb000000
 189 #define CONFIG_SYS_QRIO_BASE_PHYS       0xffb000000ull
 190
 191 #define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
 192                                 | BR_PS_8       /* Port Size 8 bits */ \
 193                                 | BR_DECC_OFF   /* no error corr */ \
 194                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 195                                 | BR_V)         /* valid */
 196
 197 #define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB  /* length 64K */ \
 198                                 | OR_GPCM_BCTLD /* no LCTL assert */ \
 199                                 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
 200                                 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 201                                 | OR_GPCM_TRLX /* relaxed tmgs */ \
 202                                 | OR_GPCM_EAD) /* extra bus clk cycles */
 203
 204 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
 205 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
 206
 207 /* bootcounter in QRIO */
 208 #define CONFIG_BOOTCOUNT_LIMIT
 209 #define CONFIG_SYS_BOOTCOUNT_ADDR       (CONFIG_SYS_QRIO_BASE + 0x20)
 210
 211 #define CONFIG_BOARD_EARLY_INIT_F
 212 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 213 #define CONFIG_MISC_INIT_F
 214 #define CONFIG_MISC_INIT_R
 215 #define CONFIG_LAST_STAGE_INIT
 216
 217 #define CONFIG_HWCONFIG
 218
 219 /* define to use L1 as initial stack */
 220 #define CONFIG_L1_INIT_RAM
 221 #define CONFIG_SYS_INIT_RAM_LOCK
 222 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 225 /* The assembler doesn't like typecast */
 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 227         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 228           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 229 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 230
 231 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 232                                         GENERATED_GBL_DATA_SIZE)
 233 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 234
 235 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 236 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 237 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 238
 239 /* Serial Port - controlled on board with jumper J8
 240  * open - index 2
 241  * shorted - index 1
 242  */
 243 #define CONFIG_CONS_INDEX       1
 244 #define CONFIG_SYS_NS16550
 245 #define CONFIG_SYS_NS16550_SERIAL
 246 #define CONFIG_SYS_NS16550_REG_SIZE     1
 247 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 248
 249 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 250 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 251 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 252 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 253
 254 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 255
 256 /* Use the HUSH parser */
 257 #define CONFIG_SYS_HUSH_PARSER
 258
 259 /* pass open firmware flat tree */
 260 #define CONFIG_OF_LIBFDT
 261 #define CONFIG_OF_BOARD_SETUP
 262 #define CONFIG_OF_STDOUT_VIA_ALIAS
 263
 264 /* new uImage format support */
 265 #define CONFIG_FIT
 266 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 267
 268 /* I2C */
 269
 270 #define CONFIG_SYS_I2C
 271 #define CONFIG_SYS_I2C_INIT_BOARD
 272 #define CONFIG_SYS_I2C_SPEED            100000 /* deblocking */
 273 #define CONFIG_SYS_NUM_I2C_BUSES        3
 274 #define CONFIG_SYS_I2C_MAX_HOPS         1
 275 #define CONFIG_SYS_I2C_FSL              /* Use FSL I2C driver */
 276 #define CONFIG_I2C_MULTI_BUS
 277 #define CONFIG_I2C_CMD_TREE
 278 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 279 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 280 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 281 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 282                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 283                                         {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
 284                                 }
 285 #ifndef __ASSEMBLY__
 286 void set_sda(int state);
 287 void set_scl(int state);
 288 int get_sda(void);
 289 int get_scl(void);
 290 #endif
 291
 292 #define CONFIG_KM_IVM_BUS               1       /* I2C1 (Mux-Port 1)*/
 293
 294 /*
 295  * eSPI - Enhanced SPI
 296  */
 297 #define CONFIG_FSL_ESPI
 298 #define CONFIG_SPI_FLASH
 299 #define CONFIG_SPI_FLASH_BAR    /* 4 byte-addressing */
 300 #define CONFIG_SPI_FLASH_STMICRO
 301 #define CONFIG_CMD_SF
 302 #define CONFIG_SF_DEFAULT_SPEED         20000000
 303 #define CONFIG_SF_DEFAULT_MODE          0
 304
 305 /*
 306  * General PCI
 307  * Memory space is mapped 1-1, but I/O space must start from 0.
 308  */
 309
 310 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 311 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 312 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 313 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 314 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 315 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 316 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 317 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 318 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 319
 320 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 321 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 322 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 323 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 324 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 325 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8010000
 326 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 327 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8010000ull
 328 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 329
 330 /* Qman/Bman */
 331 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 332 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 333 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 334 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 335 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 336 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 337 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 338 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 339 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 340
 341 #define CONFIG_SYS_DPAA_FMAN
 342 #define CONFIG_SYS_DPAA_PME
 343 /* Default address of microcode for the Linux Fman driver
 344  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
 345  * ucode is stored after env, so we got 0x120000.
 346  */
 347 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 348 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x120000
 349 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 350 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 351
 352 #define CONFIG_FMAN_ENET
 353 #define CONFIG_PHYLIB_10G
 354 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
 355
 356 #define CONFIG_PCI_INDIRECT_BRIDGE
 357 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 358 #define CONFIG_E1000
 359
 360 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 361 #define CONFIG_DOS_PARTITION
 362
 363 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
 364 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x11
 365 #define CONFIG_SYS_TBIPA_VALUE  8
 366 #define CONFIG_PHYLIB           /* recommended PHY management */
 367 #define CONFIG_ETHPRIME         "FM1@DTSEC5"
 368 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 369
 370 /*
 371  * Environment
 372  */
 373 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 374 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 375
 376 /*
 377  * additionnal command line configuration.
 378  */
 379 #define CONFIG_CMD_PCI
 380 #define CONFIG_CMD_NET
 381
 382 /* we don't need flash support */
 383 #define CONFIG_SYS_NO_FLASH
 384 #undef CONFIG_CMD_IMLS
 385 #undef CONFIG_CMD_FLASH
 386 #undef CONFIG_FLASH_CFI_MTD
 387 #undef CONFIG_JFFS2_CMDLINE
 388
 389 /*
 390  * For booting Linux, the board info and command line data
 391  * have to be in the first 64 MB of memory, since this is
 392  * the maximum mapped by the Linux kernel during initialization.
 393  */
 394 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 395 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 396
 397 #ifdef CONFIG_CMD_KGDB
 398 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 399 #endif
 400
 401 #define __USB_PHY_TYPE  utmi
 402
 403 /*
 404  * Environment Configuration
 405  */
 406 #define CONFIG_ENV_OVERWRITE
 407 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 408 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 409 #endif
 410
 411 #ifndef MTDIDS_DEFAULT
 412 # define MTDIDS_DEFAULT         "nand0=fsl_elbc_nand"
 413 #endif /* MTDIDS_DEFAULT */
 414
 415 #ifndef MTDPARTS_DEFAULT
 416 # define MTDPARTS_DEFAULT       "mtdparts="                     \
 417         "fsl_elbc_nand:"                                                \
 418                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
 419 #endif /* MTDPARTS_DEFAULT */
 420
 421 /* architecture specific default bootargs */
 422 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 423
 424 /* FIXME: FDT_ADDR is unspecified */
 425 #define CONFIG_KM_DEF_ENV_CPU                                           \
 426         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 427         "cramfsloadfdt="                                                \
 428                 "cramfsload ${fdt_addr_r} "                             \
 429                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 430         "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"              \
 431         "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0"           \
 432         "update="                                                       \
 433                 "sf probe 0;sf erase 0 +${filesize};"                   \
 434                 "sf write ${load_addr_r} 0 ${filesize};\0"              \
 435         ""
 436
 437 #define CONFIG_HW_ENV_SETTINGS                                          \
 438         "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"                       \
 439         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 440         "usb_dr_mode=host\0"
 441
 442 #define CONFIG_KM_NEW_ENV                                               \
 443         "newenv=sf probe 0;"                                            \
 444                 "sf erase " __stringify(CONFIG_ENV_OFFSET) " "          \
 445                 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
 446
 447 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
 448 #ifndef CONFIG_KM_DEF_ARCH
 449 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 450 #endif
 451
 452 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 453         CONFIG_KM_DEF_ENV                                               \
 454         CONFIG_KM_DEF_ARCH                                              \
 455         CONFIG_KM_NEW_ENV                                               \
 456         CONFIG_HW_ENV_SETTINGS                                          \
 457         "EEprom_ivm=pca9547:70:9\0"                                     \
 458         ""
 459
 460 #endif /* _CONFIG_KMP204X_H */