2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <config_cmd_default.h>
13 #define CONFIG_SYS_GENERIC_BOARD
15 #define CONFIG_DISPLAY_CPUINFO
16 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_SKIP_LOWLEVEL_INIT
19 #define CONFIG_BOARD_EARLY_INIT_F
22 * Size of malloc() pool
24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
27 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
30 * Generic Timer Definitions
32 #define GENERIC_TIMER_CLK 12500000
34 #define CONFIG_SYS_CLK_FREQ 100000000
35 #define CONFIG_DDR_CLK_FREQ 100000000
37 #ifdef CONFIG_RAMBOOT_PBL
38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
42 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
43 #define CONFIG_SPL_FRAMEWORK
44 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
45 #define CONFIG_SPL_LIBCOMMON_SUPPORT
46 #define CONFIG_SPL_LIBGENERIC_SUPPORT
47 #define CONFIG_SPL_ENV_SUPPORT
48 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
49 #define CONFIG_SPL_I2C_SUPPORT
50 #define CONFIG_SPL_WATCHDOG_SUPPORT
51 #define CONFIG_SPL_SERIAL_SUPPORT
52 #define CONFIG_SPL_MMC_SUPPORT
53 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
54 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
56 #define CONFIG_SPL_TEXT_BASE 0x10000000
57 #define CONFIG_SPL_MAX_SIZE 0x1a000
58 #define CONFIG_SPL_STACK 0x1001d000
59 #define CONFIG_SPL_PAD_TO 0x1c000
60 #define CONFIG_SYS_TEXT_BASE 0x82000000
62 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
63 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
64 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
65 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
66 #define CONFIG_SYS_MONITOR_LEN 0x80000
69 #ifdef CONFIG_QSPI_BOOT
70 #define CONFIG_SYS_TEXT_BASE 0x40010000
71 #define CONFIG_SYS_NO_FLASH
74 #ifndef CONFIG_SYS_TEXT_BASE
75 #define CONFIG_SYS_TEXT_BASE 0x67f80000
78 #define CONFIG_NR_DRAM_BANKS 1
79 #define PHYS_SDRAM 0x80000000
80 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
82 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
83 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
85 #define CONFIG_SYS_HAS_SERDES
87 #define CONFIG_FSL_CAAM /* Enable CAAM */
89 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
90 !defined(CONFIG_QSPI_BOOT)
97 #ifndef CONFIG_QSPI_BOOT
98 #define CONFIG_FSL_IFC
99 #define CONFIG_SYS_FLASH_BASE 0x60000000
100 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
102 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
103 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
104 CSPR_PORT_SIZE_16 | \
107 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
109 /* NOR Flash Timing Params */
110 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
112 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
113 FTIM0_NOR_TEADC(0x5) | \
114 FTIM0_NOR_TAVDS(0x0) | \
115 FTIM0_NOR_TEAHC(0x5))
116 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
117 FTIM1_NOR_TRAD_NOR(0x1A) | \
118 FTIM1_NOR_TSEQRAD_NOR(0x13))
119 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
120 FTIM2_NOR_TCH(0x4) | \
121 FTIM2_NOR_TWP(0x1c) | \
122 FTIM2_NOR_TWPH(0x0e))
123 #define CONFIG_SYS_NOR_FTIM3 0
125 #define CONFIG_FLASH_CFI_DRIVER
126 #define CONFIG_SYS_FLASH_CFI
127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
128 #define CONFIG_SYS_FLASH_QUIET_TEST
129 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
132 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
133 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
134 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
136 #define CONFIG_SYS_FLASH_EMPTY_INFO
137 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
139 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
140 #define CONFIG_SYS_WRITE_SWAPPED_DATA
145 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
146 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
148 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
149 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
153 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
154 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
155 CSOR_NOR_NOR_MODE_AVD_NOR | \
158 /* CPLD Timing parameters for IFC GPCM */
159 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
160 FTIM0_GPCM_TEADC(0xf) | \
161 FTIM0_GPCM_TEAHC(0xf))
162 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
163 FTIM1_GPCM_TRAD(0x3f))
164 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
165 FTIM2_GPCM_TCH(0xf) | \
166 FTIM2_GPCM_TWP(0xff))
167 #define CONFIG_SYS_FPGA_FTIM3 0x0
168 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
169 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
170 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
171 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
172 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
173 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
174 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
175 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
176 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
177 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
178 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
179 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
180 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
181 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
182 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
183 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
189 #define CONFIG_FSL_LPUART
190 #define CONFIG_LPUART_32B_REG
192 #define CONFIG_CONS_INDEX 1
193 #define CONFIG_SYS_NS16550
194 #define CONFIG_SYS_NS16550_SERIAL
195 #define CONFIG_SYS_NS16550_REG_SIZE 1
196 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
199 #define CONFIG_BAUDRATE 115200
204 #define CONFIG_CMD_I2C
205 #define CONFIG_SYS_I2C
206 #define CONFIG_SYS_I2C_MXC
209 #ifndef CONFIG_SD_BOOT
210 #define CONFIG_ID_EEPROM
211 #define CONFIG_SYS_I2C_EEPROM_NXID
212 #define CONFIG_SYS_EEPROM_BUS_NUM 1
213 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
223 #define CONFIG_CMD_MMC
224 #define CONFIG_FSL_ESDHC
225 #define CONFIG_GENERIC_MMC
227 #define CONFIG_CMD_FAT
228 #define CONFIG_DOS_PARTITION
231 #ifdef CONFIG_QSPI_BOOT
232 #define CONFIG_FSL_QSPI
233 #define QSPI0_AMBA_BASE 0x40000000
234 #define FSL_QSPI_FLASH_SIZE (1 << 24)
235 #define FSL_QSPI_FLASH_NUM 2
237 #define CONFIG_CMD_SF
238 #define CONFIG_SPI_FLASH
239 #define CONFIG_SPI_FLASH_STMICRO
245 #define CONFIG_FSL_DCU_FB
247 #ifdef CONFIG_FSL_DCU_FB
249 #define CONFIG_CMD_BMP
250 #define CONFIG_CFB_CONSOLE
251 #define CONFIG_VGA_AS_SINGLE_DEVICE
252 #define CONFIG_VIDEO_LOGO
253 #define CONFIG_VIDEO_BMP_LOGO
255 #define CONFIG_FSL_DCU_SII9022A
256 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
257 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
263 #define CONFIG_TSEC_ENET
265 #ifdef CONFIG_TSEC_ENET
267 #define CONFIG_MII_DEFAULT_TSEC 1
268 #define CONFIG_TSEC1 1
269 #define CONFIG_TSEC1_NAME "eTSEC1"
270 #define CONFIG_TSEC2 1
271 #define CONFIG_TSEC2_NAME "eTSEC2"
272 #define CONFIG_TSEC3 1
273 #define CONFIG_TSEC3_NAME "eTSEC3"
275 #define TSEC1_PHY_ADDR 2
276 #define TSEC2_PHY_ADDR 0
277 #define TSEC3_PHY_ADDR 1
279 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
280 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
281 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
283 #define TSEC1_PHYIDX 0
284 #define TSEC2_PHYIDX 0
285 #define TSEC3_PHYIDX 0
287 #define CONFIG_ETHPRIME "eTSEC1"
289 #define CONFIG_PHY_GIGE
290 #define CONFIG_PHYLIB
291 #define CONFIG_PHY_ATHEROS
293 #define CONFIG_HAS_ETH0
294 #define CONFIG_HAS_ETH1
295 #define CONFIG_HAS_ETH2
299 #define CONFIG_PCI /* Enable PCI/PCIE */
300 #define CONFIG_PCIE1 /* PCIE controler 1 */
301 #define CONFIG_PCIE2 /* PCIE controler 2 */
302 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
303 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
305 #define CONFIG_CMD_PING
306 #define CONFIG_CMD_DHCP
307 #define CONFIG_CMD_MII
308 #define CONFIG_CMD_NET
310 #define CONFIG_CMDLINE_TAG
311 #define CONFIG_CMDLINE_EDITING
313 #ifdef CONFIG_QSPI_BOOT
314 #undef CONFIG_CMD_IMLS
316 #define CONFIG_CMD_IMLS
319 #define CONFIG_ARMV7_NONSEC
320 #define CONFIG_ARMV7_VIRT
321 #define CONFIG_PEN_ADDR_BIG_ENDIAN
322 #define CONFIG_LS102XA_NS_ACCESS
323 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
324 #define CONFIG_TIMER_CLK_FREQ 12500000
325 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
327 #define CONFIG_HWCONFIG
328 #define HWCONFIG_BUFFER_SIZE 128
330 #define CONFIG_BOOTDELAY 3
333 #define CONFIG_EXTRA_ENV_SETTINGS \
334 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
335 "initrd_high=0xcfffffff\0" \
336 "fdt_high=0xcfffffff\0"
338 #define CONFIG_EXTRA_ENV_SETTINGS \
339 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
340 "initrd_high=0xcfffffff\0" \
341 "fdt_high=0xcfffffff\0"
345 * Miscellaneous configurable options
347 #define CONFIG_SYS_LONGHELP /* undef to save memory */
348 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
349 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
350 #define CONFIG_AUTO_COMPLETE
351 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
352 #define CONFIG_SYS_PBSIZE \
353 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
354 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
355 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
357 #define CONFIG_CMD_ENV_EXISTS
358 #define CONFIG_CMD_GREPENV
359 #define CONFIG_CMD_MEMINFO
360 #define CONFIG_CMD_MEMTEST
361 #define CONFIG_SYS_MEMTEST_START 0x80000000
362 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
364 #define CONFIG_SYS_LOAD_ADDR 0x82000000
366 #define CONFIG_LS102XA_STREAM_ID
370 * The stack sizes are set up in start.S using the settings below
372 #define CONFIG_STACKSIZE (30 * 1024)
374 #define CONFIG_SYS_INIT_SP_OFFSET \
375 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
376 #define CONFIG_SYS_INIT_SP_ADDR \
377 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
379 #ifdef CONFIG_SPL_BUILD
380 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
382 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
385 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
390 #define CONFIG_ENV_OVERWRITE
392 #if defined(CONFIG_SD_BOOT)
393 #define CONFIG_ENV_OFFSET 0x100000
394 #define CONFIG_ENV_IS_IN_MMC
395 #define CONFIG_SYS_MMC_ENV_DEV 0
396 #define CONFIG_ENV_SIZE 0x20000
397 #elif defined(CONFIG_QSPI_BOOT)
398 #define CONFIG_ENV_IS_IN_SPI_FLASH
399 #define CONFIG_ENV_SIZE 0x2000
400 #define CONFIG_ENV_OFFSET 0x100000
401 #define CONFIG_ENV_SECT_SIZE 0x10000
403 #define CONFIG_ENV_IS_IN_FLASH
404 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
405 #define CONFIG_ENV_SIZE 0x20000
406 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
409 #define CONFIG_OF_LIBFDT
410 #define CONFIG_OF_BOARD_SETUP
411 #define CONFIG_CMD_BOOTZ
413 #define CONFIG_MISC_INIT_R
415 /* Hash command with SHA acceleration supported in hardware */
416 #define CONFIG_CMD_HASH
417 #define CONFIG_SHA_HW_ACCEL
419 #ifdef CONFIG_SECURE_BOOT
420 #define CONFIG_CMD_BLOB