include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <config_cmd_default.h>
  11
  12
  13 #define CONFIG_SYS_GENERIC_BOARD
  14
  15 #define CONFIG_DISPLAY_CPUINFO
  16 #define CONFIG_DISPLAY_BOARDINFO
  17
  18 #define CONFIG_SKIP_LOWLEVEL_INIT
  19 #define CONFIG_BOARD_EARLY_INIT_F
  20
  21 /*
  22  * Size of malloc() pool
  23  */
  24 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  25
  26 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  27 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  28
  29 /*
  30  * Generic Timer Definitions
  31  */
  32 #define GENERIC_TIMER_CLK               12500000
  33
  34 #define CONFIG_SYS_CLK_FREQ             100000000
  35 #define CONFIG_DDR_CLK_FREQ             100000000
  36
  37 #define DDR_SDRAM_CFG                   0x470c0008
  38 #define DDR_CS0_BNDS                    0x008000bf
  39 #define DDR_CS0_CONFIG                  0x80014302
  40 #define DDR_TIMING_CFG_0                0x50550004
  41 #define DDR_TIMING_CFG_1                0xbcb38c56
  42 #define DDR_TIMING_CFG_2                0x0040d120
  43 #define DDR_TIMING_CFG_3                0x010e1000
  44 #define DDR_TIMING_CFG_4                0x00000001
  45 #define DDR_TIMING_CFG_5                0x03401400
  46 #define DDR_SDRAM_CFG_2                 0x00401010
  47 #define DDR_SDRAM_MODE                  0x00061c60
  48 #define DDR_SDRAM_MODE_2                0x00180000
  49 #define DDR_SDRAM_INTERVAL              0x18600618
  50 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  51 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  52 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  53 #define DDR_DDR_CDR1                    0x80040000
  54 #define DDR_DDR_CDR2                    0x00000001
  55 #define DDR_SDRAM_CLK_CNTL              0x02000000
  56 #define DDR_DDR_ZQ_CNTL                 0x89080600
  57 #define DDR_CS0_CONFIG_2                0
  58 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  59
  60 #ifdef CONFIG_RAMBOOT_PBL
  61 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  62 #endif
  63
  64 #ifdef CONFIG_SD_BOOT
  65 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
  66 #define CONFIG_SPL_FRAMEWORK
  67 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  68 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  69 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  70 #define CONFIG_SPL_ENV_SUPPORT
  71 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  72 #define CONFIG_SPL_I2C_SUPPORT
  73 #define CONFIG_SPL_WATCHDOG_SUPPORT
  74 #define CONFIG_SPL_SERIAL_SUPPORT
  75 #define CONFIG_SPL_MMC_SUPPORT
  76 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
  77 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
  78
  79 #define CONFIG_SPL_TEXT_BASE            0x10000000
  80 #define CONFIG_SPL_MAX_SIZE             0x1a000
  81 #define CONFIG_SPL_STACK                0x1001d000
  82 #define CONFIG_SPL_PAD_TO               0x1c000
  83 #define CONFIG_SYS_TEXT_BASE            0x82000000
  84
  85 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  86 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  87 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  88 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  89 #define CONFIG_SYS_MONITOR_LEN          0x80000
  90 #endif
  91
  92 #ifdef CONFIG_QSPI_BOOT
  93 #define CONFIG_SYS_TEXT_BASE            0x40010000
  94 #define CONFIG_SYS_NO_FLASH
  95 #endif
  96
  97 #ifndef CONFIG_SYS_TEXT_BASE
  98 #define CONFIG_SYS_TEXT_BASE            0x60100000
  99 #endif
 100
 101 #define CONFIG_NR_DRAM_BANKS            1
 102 #define PHYS_SDRAM                      0x80000000
 103 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 104
 105 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 106 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 107
 108 #define CONFIG_SYS_HAS_SERDES
 109
 110 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 111
 112 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 113         !defined(CONFIG_QSPI_BOOT)
 114 #define CONFIG_U_QE
 115 #endif
 116
 117 /*
 118  * IFC Definitions
 119  */
 120 #ifndef CONFIG_QSPI_BOOT
 121 #define CONFIG_FSL_IFC
 122 #define CONFIG_SYS_FLASH_BASE           0x60000000
 123 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 124
 125 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 126 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 127                                 CSPR_PORT_SIZE_16 | \
 128                                 CSPR_MSEL_NOR | \
 129                                 CSPR_V)
 130 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 131
 132 /* NOR Flash Timing Params */
 133 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 134                                         CSOR_NOR_TRHZ_80)
 135 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 136                                         FTIM0_NOR_TEADC(0x5) | \
 137                                         FTIM0_NOR_TAVDS(0x0) | \
 138                                         FTIM0_NOR_TEAHC(0x5))
 139 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 140                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 141                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 142 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 143                                         FTIM2_NOR_TCH(0x4) | \
 144                                         FTIM2_NOR_TWP(0x1c) | \
 145                                         FTIM2_NOR_TWPH(0x0e))
 146 #define CONFIG_SYS_NOR_FTIM3            0
 147
 148 #define CONFIG_FLASH_CFI_DRIVER
 149 #define CONFIG_SYS_FLASH_CFI
 150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 151 #define CONFIG_SYS_FLASH_QUIET_TEST
 152 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 153
 154 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 155 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 156 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 157 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 158
 159 #define CONFIG_SYS_FLASH_EMPTY_INFO
 160 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 161
 162 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 163 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 164 #endif
 165
 166 /* CPLD */
 167
 168 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 169 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 170
 171 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 172 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 173                                         CSPR_PORT_SIZE_8 | \
 174                                         CSPR_MSEL_GPCM | \
 175                                         CSPR_V)
 176 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 177 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 178                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 179                                         CSOR_NOR_TRHZ_80)
 180
 181 /* CPLD Timing parameters for IFC GPCM */
 182 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 183                                         FTIM0_GPCM_TEADC(0xf) | \
 184                                         FTIM0_GPCM_TEAHC(0xf))
 185 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 186                                         FTIM1_GPCM_TRAD(0x3f))
 187 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 188                                         FTIM2_GPCM_TCH(0xf) | \
 189                                         FTIM2_GPCM_TWP(0xff))
 190 #define CONFIG_SYS_FPGA_FTIM3           0x0
 191 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 192 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 193 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 194 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 195 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 196 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 197 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 198 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 199 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 200 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 201 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 202 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 203 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 204 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 205 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 206 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 207
 208 /*
 209  * Serial Port
 210  */
 211 #ifdef CONFIG_LPUART
 212 #define CONFIG_FSL_LPUART
 213 #define CONFIG_LPUART_32B_REG
 214 #else
 215 #define CONFIG_CONS_INDEX               1
 216 #define CONFIG_SYS_NS16550
 217 #define CONFIG_SYS_NS16550_SERIAL
 218 #define CONFIG_SYS_NS16550_REG_SIZE     1
 219 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 220 #endif
 221
 222 #define CONFIG_BAUDRATE                 115200
 223
 224 /*
 225  * I2C
 226  */
 227 #define CONFIG_CMD_I2C
 228 #define CONFIG_SYS_I2C
 229 #define CONFIG_SYS_I2C_MXC
 230 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 231
 232 /* EEPROM */
 233 #ifndef CONFIG_SD_BOOT
 234 #define CONFIG_ID_EEPROM
 235 #define CONFIG_SYS_I2C_EEPROM_NXID
 236 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 237 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 241 #endif
 242
 243 /*
 244  * MMC
 245  */
 246 #define CONFIG_MMC
 247 #define CONFIG_CMD_MMC
 248 #define CONFIG_FSL_ESDHC
 249 #define CONFIG_GENERIC_MMC
 250
 251 #define CONFIG_CMD_FAT
 252 #define CONFIG_DOS_PARTITION
 253
 254 /* QSPI */
 255 #ifdef CONFIG_QSPI_BOOT
 256 #define CONFIG_FSL_QSPI
 257 #define QSPI0_AMBA_BASE                 0x40000000
 258 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 259 #define FSL_QSPI_FLASH_NUM              2
 260
 261 #define CONFIG_CMD_SF
 262 #define CONFIG_SPI_FLASH_STMICRO
 263 #endif
 264
 265 /*
 266  * Video
 267  */
 268 #define CONFIG_FSL_DCU_FB
 269
 270 #ifdef CONFIG_FSL_DCU_FB
 271 #define CONFIG_VIDEO
 272 #define CONFIG_CMD_BMP
 273 #define CONFIG_CFB_CONSOLE
 274 #define CONFIG_VGA_AS_SINGLE_DEVICE
 275 #define CONFIG_VIDEO_LOGO
 276 #define CONFIG_VIDEO_BMP_LOGO
 277
 278 #define CONFIG_FSL_DCU_SII9022A
 279 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 280 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 281 #endif
 282
 283 /*
 284  * eTSEC
 285  */
 286 #define CONFIG_TSEC_ENET
 287
 288 #ifdef CONFIG_TSEC_ENET
 289 #define CONFIG_MII
 290 #define CONFIG_MII_DEFAULT_TSEC         1
 291 #define CONFIG_TSEC1                    1
 292 #define CONFIG_TSEC1_NAME               "eTSEC1"
 293 #define CONFIG_TSEC2                    1
 294 #define CONFIG_TSEC2_NAME               "eTSEC2"
 295 #define CONFIG_TSEC3                    1
 296 #define CONFIG_TSEC3_NAME               "eTSEC3"
 297
 298 #define TSEC1_PHY_ADDR                  2
 299 #define TSEC2_PHY_ADDR                  0
 300 #define TSEC3_PHY_ADDR                  1
 301
 302 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 303 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 304 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 305
 306 #define TSEC1_PHYIDX                    0
 307 #define TSEC2_PHYIDX                    0
 308 #define TSEC3_PHYIDX                    0
 309
 310 #define CONFIG_ETHPRIME                 "eTSEC1"
 311
 312 #define CONFIG_PHY_GIGE
 313 #define CONFIG_PHYLIB
 314 #define CONFIG_PHY_ATHEROS
 315
 316 #define CONFIG_HAS_ETH0
 317 #define CONFIG_HAS_ETH1
 318 #define CONFIG_HAS_ETH2
 319 #endif
 320
 321 /* PCIe */
 322 #define CONFIG_PCI              /* Enable PCI/PCIE */
 323 #define CONFIG_PCIE1            /* PCIE controler 1 */
 324 #define CONFIG_PCIE2            /* PCIE controler 2 */
 325 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 326 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 327
 328 #define CONFIG_SYS_PCI_64BIT
 329
 330 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 331 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 332 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 333 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 334
 335 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 336 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 337 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 338
 339 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 340 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 341 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 342
 343 #ifdef CONFIG_PCI
 344 #define CONFIG_PCI_PNP
 345 #define CONFIG_E1000
 346 #define CONFIG_PCI_SCAN_SHOW
 347 #define CONFIG_CMD_PCI
 348 #endif
 349
 350 #define CONFIG_CMD_PING
 351 #define CONFIG_CMD_DHCP
 352 #define CONFIG_CMD_MII
 353
 354 #define CONFIG_CMDLINE_TAG
 355 #define CONFIG_CMDLINE_EDITING
 356
 357 #ifdef CONFIG_QSPI_BOOT
 358 #undef CONFIG_CMD_IMLS
 359 #else
 360 #define CONFIG_CMD_IMLS
 361 #endif
 362
 363 #define CONFIG_ARMV7_NONSEC
 364 #define CONFIG_ARMV7_VIRT
 365 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 366 #define CONFIG_LS102XA_NS_ACCESS
 367 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 368 #define CONFIG_TIMER_CLK_FREQ           12500000
 369 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
 370
 371 #define CONFIG_HWCONFIG
 372 #define HWCONFIG_BUFFER_SIZE            128
 373
 374 #define CONFIG_BOOTDELAY                3
 375
 376 #ifdef CONFIG_LPUART
 377 #define CONFIG_EXTRA_ENV_SETTINGS       \
 378         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 379         "initrd_high=0xcfffffff\0"      \
 380         "fdt_high=0xcfffffff\0"
 381 #else
 382 #define CONFIG_EXTRA_ENV_SETTINGS       \
 383         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 384         "initrd_high=0xcfffffff\0"      \
 385         "fdt_high=0xcfffffff\0"
 386 #endif
 387
 388 /*
 389  * Miscellaneous configurable options
 390  */
 391 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 392 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 393 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 394 #define CONFIG_AUTO_COMPLETE
 395 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 396 #define CONFIG_SYS_PBSIZE               \
 397                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 398 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 399 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 400
 401 #define CONFIG_CMD_ENV_EXISTS
 402 #define CONFIG_CMD_GREPENV
 403 #define CONFIG_CMD_MEMINFO
 404 #define CONFIG_CMD_MEMTEST
 405 #define CONFIG_SYS_MEMTEST_START        0x80000000
 406 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 407
 408 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 409
 410 #define CONFIG_LS102XA_STREAM_ID
 411
 412 /*
 413  * Stack sizes
 414  * The stack sizes are set up in start.S using the settings below
 415  */
 416 #define CONFIG_STACKSIZE                (30 * 1024)
 417
 418 #define CONFIG_SYS_INIT_SP_OFFSET \
 419         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 420 #define CONFIG_SYS_INIT_SP_ADDR \
 421         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 422
 423 #ifdef CONFIG_SPL_BUILD
 424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 425 #else
 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 427 #endif
 428
 429 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
 430
 431 /*
 432  * Environment
 433  */
 434 #define CONFIG_ENV_OVERWRITE
 435
 436 #if defined(CONFIG_SD_BOOT)
 437 #define CONFIG_ENV_OFFSET               0x100000
 438 #define CONFIG_ENV_IS_IN_MMC
 439 #define CONFIG_SYS_MMC_ENV_DEV          0
 440 #define CONFIG_ENV_SIZE                 0x20000
 441 #elif defined(CONFIG_QSPI_BOOT)
 442 #define CONFIG_ENV_IS_IN_SPI_FLASH
 443 #define CONFIG_ENV_SIZE                 0x2000
 444 #define CONFIG_ENV_OFFSET               0x100000
 445 #define CONFIG_ENV_SECT_SIZE            0x10000
 446 #else
 447 #define CONFIG_ENV_IS_IN_FLASH
 448 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 449 #define CONFIG_ENV_SIZE                 0x20000
 450 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 451 #endif
 452
 453 #define CONFIG_OF_LIBFDT
 454 #define CONFIG_OF_BOARD_SETUP
 455 #define CONFIG_CMD_BOOTZ
 456
 457 #define CONFIG_MISC_INIT_R
 458
 459 /* Hash command with SHA acceleration supported in hardware */
 460 #define CONFIG_CMD_HASH
 461 #define CONFIG_SHA_HW_ACCEL
 462
 463 #ifdef CONFIG_SECURE_BOOT
 464 #define CONFIG_CMD_BLOB
 465 #endif
 466
 467 #endif