include/configs/mpc5121ads.h

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * MPC5121ADS board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_MPC5121ADS 1
  31 /*
  32  * Memory map for the MPC5121ADS board:
  33  *
  34  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  35  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  36  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  37  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  38  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  39  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  40  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  41  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  42  */
  43
  44 /*
  45  * High Level Configuration Options
  46  */
  47 #define CONFIG_E300             1       /* E300 Family */
  48 #define CONFIG_MPC512X          1       /* MPC512X family */
  49
  50 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  51
  52 /* video */
  53 #ifdef CONFIG_FSL_DIU_FB
  54 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_IMMR + 0x2100)
  55 #define CONFIG_VIDEO
  56 #define CONFIG_CMD_BMP
  57 #define CONFIG_CFB_CONSOLE
  58 #define CONFIG_VIDEO_SW_CURSOR
  59 #define CONFIG_VGA_AS_SINGLE_DEVICE
  60 #define CONFIG_VIDEO_LOGO
  61 #define CONFIG_VIDEO_BMP_LOGO
  62 #endif
  63
  64 /* CONFIG_PCI is defined at config time */
  65
  66 #ifdef CONFIG_MPC5121ADS_REV2
  67 #define CONFIG_SYS_MPC512X_CLKIN        66000000        /* in Hz */
  68 #else
  69 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  70 #define CONFIG_PCI
  71 #endif
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  74 #define CONFIG_MISC_INIT_R
  75
  76 #define CONFIG_SYS_IMMR         0x80000000
  77
  78 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  79 #define CONFIG_SYS_MEMTEST_END          0x00400000
  80
  81 /*
  82  * DDR Setup - manually set all parameters as there's no SPD etc.
  83  */
  84 #ifdef CONFIG_MPC5121ADS_REV2
  85 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  86 #else
  87 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  88 #endif
  89 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  90 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  91 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  92
  93 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
  94
  95 /* DDR Controller Configuration
  96  *
  97  * SYS_CFG:
  98  *      [31:31] MDDRC Soft Reset:       Diabled
  99  *      [30:30] DRAM CKE pin:           Enabled
 100  *      [29:29] DRAM CLK:               Enabled
 101  *      [28:28] Command Mode:           Enabled (For initialization only)
 102  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
 103  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
 104  *      [20:19] Read Test:              DON'T USE
 105  *      [18:18] Self Refresh:           Enabled
 106  *      [17:17] 16bit Mode:             Disabled
 107  *      [16:13] Ready Delay:            2
 108  *      [12:12] Half DQS Delay:         Disabled
 109  *      [11:11] Quarter DQS Delay:      Disabled
 110  *      [10:08] Write Delay:            2
 111  *      [07:07] Early ODT:              Disabled
 112  *      [06:06] On DIE Termination:     Disabled
 113  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 114  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 115  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 116  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 117  *      [01:01] FIFO Overlfow Enabled:  Enabled
 118  *      [00:00] FIFO Underflow Enabled: Enabled
 119  * TIME_CFG0
 120  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 121  *      [15:8]  DRAM Command Time:      0 CSB clocks
 122  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 123  * TIME_CFG1
 124  *      [31:26] DRAM tRFC:
 125  *      [25:21] DRAM tWR1:
 126  *      [20:17] DRAM tWRT1:
 127  *      [16:11] DRAM tDRR:
 128  *      [10:05] DRAM tRC:
 129  *      [04:00] DRAM tRAS:
 130  * TIME_CFG2
 131  *      [31:28] DRAM tRCD:
 132  *      [27:23] DRAM tFAW:
 133  *      [22:19] DRAM tRTW1:
 134  *      [18:15] DRAM tCCD:
 135  *      [14:10] DRAM tRTP:
 136  *      [09:05] DRAM tRP:
 137  *      [04:00] DRAM tRPA
 138  */
 139 #ifdef CONFIG_MPC5121ADS_REV2
 140 #define CONFIG_SYS_MDDRC_SYS_CFG        0xE8604A00
 141 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x54EC1168
 142 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x35210864
 143 #else
 144 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A00
 145 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 146 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 147 #endif
 148 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x06183D2E
 149
 150 #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA         0xEA802B00
 151 #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA       0x690e1189
 152 #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA       0x35310864
 153
 154 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 155 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 156 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
 157 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
 158 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
 159 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 160
 161 #define DDRCMD_EMR_OCD(pr, ohm) ( \
 162         (1 << 24)          | /* MDDRC Command Request   */ \
 163         (1 << 16)          | /* MODE Reg BA[2:0]        */ \
 164         (0 << 12)          | /* Outputs 0=Enabled       */ \
 165         (0 << 11)          | /* RDQS                    */ \
 166         (1 << 10)          | /* DQS#                    */ \
 167         (pr <<  7)         | /* OCD prog 7=deflt,0=exit */ \
 168                     /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
 169         ((ohm & 0x2) <<  5)| /* Rtt1                    */ \
 170         (0 <<  3)          | /* additive posted CAS#    */ \
 171         ((ohm & 0x1) <<  2)| /* Rtt0                    */ \
 172         (0 <<  0)          | /* Output Drive Strength   */ \
 173         (0 <<  0))           /* DLL Enable 0=Normal     */
 174
 175 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   DDRCMD_EMR_OCD(7, 0)
 176 #define CONFIG_SYS_ELPIDA_OCD_EXIT      DDRCMD_EMR_OCD(0, 0)
 177
 178 #define DDRCMD_MODE_REG(cas, wr) ( \
 179         (1 << 24)    | /* MDDRC Command Request                 */ \
 180         (0 << 16)    | /* MODE Reg BA[2:0]                      */ \
 181         ((wr-1) << 9)| /* Write Recovery                        */ \
 182         (cas << 4)   | /* CAS                                   */ \
 183         (0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved */ \
 184         (2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8       */
 185
 186 #define CONFIG_SYS_MICRON_INIT_DEV_OP   DDRCMD_MODE_REG(3, 3)
 187 #define CONFIG_SYS_ELPIDA_INIT_DEV_OP   DDRCMD_MODE_REG(4, 4)
 188 #define CONFIG_SYS_ELPIDA_RES_DLL       (DDRCMD_MODE_REG(4, 4) | (1 << 8))
 189
 190 /* DDR Priority Manager Configuration */
 191 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 192 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 193 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 194 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 195 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 196 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 197 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 198 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 199 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 200 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 201 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 202 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 203 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 204 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 205 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 206 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 207 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 208 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 209 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 210 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 211 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 212 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 213 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 214
 215 /*
 216  * NOR FLASH on the Local Bus
 217  */
 218 #undef CONFIG_BKUP_FLASH
 219 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 220 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 221 #ifdef CONFIG_BKUP_FLASH
 222 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 223 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* max flash size in bytes */
 224 #else
 225 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH   */
 226 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size in bytes */
 227 #endif
 228 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 229 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 230 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 231 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 232
 233 #undef CONFIG_SYS_FLASH_CHECKSUM
 234
 235 /*
 236  * NAND FLASH
 237  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
 238  */
 239 #define CONFIG_CMD_NAND                                 /* enable NAND support */
 240 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
 241 #define CONFIG_NAND_MPC5121_NFC
 242 #define CONFIG_SYS_NAND_BASE            0x40000000
 243
 244 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 245 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 246
 247 /*
 248  * Configuration parameters for MPC5121 NAND driver
 249  */
 250 #define CONFIG_FSL_NFC_WIDTH 1
 251 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 252 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 253 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 254
 255 /*
 256  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 257  * window is 64KB
 258  */
 259 #define CONFIG_SYS_CPLD_BASE            0x82000000
 260 #define CONFIG_SYS_CPLD_SIZE            0x00010000      /* 64 KB */
 261 #define CONFIG_SYS_CS2_START            CONFIG_SYS_CPLD_BASE
 262 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_CPLD_SIZE
 263
 264 #define CONFIG_SYS_SRAM_BASE            0x30000000
 265 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 266
 267 #define CONFIG_SYS_CS0_CFG              0x05059310      /* ALE active low, data size 4bytes */
 268 #define CONFIG_SYS_CS2_CFG              0x05059010      /* ALE active low, data size 1byte */
 269 #define CONFIG_SYS_CS_ALETIMING 0x00000005      /* Use alternative CS timing for CS0 and CS2 */
 270
 271 /* Use SRAM for initial stack */
 272 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE            /* Initial RAM address */
 273 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_SRAM_SIZE            /* Size of used area in RAM */
 274
 275 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 276 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 277
 278 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE            /* Start of monitor */
 279 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)            /* Reserve 512 kB for Mon */
 280 #ifdef  CONFIG_FSL_DIU_FB
 281 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 282 #else
 283 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 284 #endif
 285
 286 /*
 287  * Serial Port
 288  */
 289 #define CONFIG_CONS_INDEX     1
 290
 291 /*
 292  * Serial console configuration
 293  */
 294 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 295 #define CONFIG_SYS_PSC3
 296 #if CONFIG_PSC_CONSOLE != 3
 297 #error CONFIG_PSC_CONSOLE must be 3
 298 #endif
 299 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 300 #define CONFIG_SYS_BAUDRATE_TABLE  \
 301         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 302
 303 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 304 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 305 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 306 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 307
 308 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 309 /* Use the HUSH parser */
 310 #define CONFIG_SYS_HUSH_PARSER
 311 #ifdef  CONFIG_SYS_HUSH_PARSER
 312 #endif
 313
 314 /*
 315  * Clocks in use
 316  */
 317 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 318                          CLOCK_SCCR1_DDR_EN |                           \
 319                          CLOCK_SCCR1_FEC_EN |                           \
 320                          CLOCK_SCCR1_LPC_EN |                           \
 321                          CLOCK_SCCR1_NFC_EN |                           \
 322                          CLOCK_SCCR1_PATA_EN |                          \
 323                          CLOCK_SCCR1_PCI_EN |                           \
 324                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 325                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 326                          CLOCK_SCCR1_TPR_EN)
 327
 328 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN |           \
 329                          CLOCK_SCCR2_I2C_EN |           \
 330                          CLOCK_SCCR2_MEM_EN |           \
 331                          CLOCK_SCCR2_SPDIF_EN |         \
 332                          CLOCK_SCCR2_USB1_EN |          \
 333                          CLOCK_SCCR2_USB2_EN)
 334
 335 /*
 336  * PCI
 337  */
 338 #ifdef CONFIG_PCI
 339 #define CONFIG_PCI_INDIRECT_BRIDGE
 340
 341 /*
 342  * General PCI
 343  */
 344 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
 345 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 346 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000      /* 256M */
 347 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
 348 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 349 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 350 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 351 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 352 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 353
 354
 355 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 356
 357 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 358
 359 #endif
 360
 361 /* I2C */
 362 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 363 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 364 #define CONFIG_I2C_MULTI_BUS
 365 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 366 #define CONFIG_SYS_I2C_SLAVE            0x7F
 367 #if 0
 368 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 369 #endif
 370
 371 /*
 372  * IIM - IC Identification Module
 373  */
 374 #undef CONFIG_FSL_IIM
 375
 376 /*
 377  * EEPROM configuration
 378  */
 379 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM address */
 380 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 381 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 382 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32-Byte Page Write Mode */
 383
 384 /*
 385  * Ethernet configuration
 386  */
 387 #define CONFIG_MPC512x_FEC      1
 388 #define CONFIG_PHY_ADDR         0x1
 389 #define CONFIG_MII              1       /* MII PHY management           */
 390 #define CONFIG_FEC_AN_TIMEOUT   1
 391 #define CONFIG_HAS_ETH0
 392
 393 /*
 394  * Configure on-board RTC
 395  */
 396 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
 397 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 398
 399 /*
 400  * USB  Support
 401  */
 402 #define CONFIG_CMD_USB
 403
 404 #if defined(CONFIG_CMD_USB)
 405 #define CONFIG_USB_EHCI                         /* Enable EHCI Support  */
 406 #define CONFIG_USB_EHCI_FSL                     /* On a FSL platform    */
 407 #define CONFIG_EHCI_MMIO_BIG_ENDIAN             /* With big-endian regs */
 408 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 409 #define CONFIG_EHCI_IS_TDI
 410 #define CONFIG_USB_STORAGE
 411 #endif
 412
 413 /*
 414  * Environment
 415  */
 416 #define CONFIG_ENV_IS_IN_FLASH  1
 417 /* This has to be a multiple of the Flash sector size */
 418 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 419 #define CONFIG_ENV_SIZE         0x2000
 420 #ifdef CONFIG_BKUP_FLASH
 421 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (256K) for env */
 422 #else
 423 #define CONFIG_ENV_SECT_SIZE    0x40000 /* one sector (256K) for env */
 424 #endif
 425
 426 /* Address and size of Redundant Environment Sector     */
 427 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 428 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 429
 430 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 431 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 432
 433 #include <config_cmd_default.h>
 434
 435 #define CONFIG_CMD_ASKENV
 436 #define CONFIG_CMD_DATE
 437 #define CONFIG_CMD_DHCP
 438 #define CONFIG_CMD_EEPROM
 439 #define CONFIG_CMD_EXT2
 440 #define CONFIG_CMD_I2C
 441 #define CONFIG_CMD_IDE
 442 #define CONFIG_CMD_JFFS2
 443 #define CONFIG_CMD_MII
 444 #define CONFIG_CMD_NFS
 445 #define CONFIG_CMD_PING
 446 #define CONFIG_CMD_REGINFO
 447
 448 #undef CONFIG_CMD_FUSE
 449
 450 #if defined(CONFIG_PCI)
 451 #define CONFIG_CMD_PCI
 452 #endif
 453
 454 /*
 455  * Dynamic MTD partition support
 456  */
 457 #define CONFIG_CMD_MTDPARTS
 458 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 459 #define CONFIG_FLASH_CFI_MTD
 460 #define MTDIDS_DEFAULT          "nor0=fc000000.flash,nand0=mpc5121.nand"
 461
 462 /*
 463  * NOR flash layout:
 464  *
 465  * FC000000 - FEABFFFF 42.75 MiB        User Data
 466  * FEAC0000 - FFABFFFF  16 MiB          Root File System
 467  * FFAC0000 - FFEBFFFF   4 MiB          Linux Kernel
 468  * FFEC0000 - FFEFFFFF 256 KiB          Device Tree
 469  * FFF00000 - FFFFFFFF   1 MiB          U-Boot (up to 512 KiB) and 2 x * env
 470  *
 471  * NAND flash layout: one big partition
 472  */
 473 #define MTDPARTS_DEFAULT        "mtdparts=fc000000.flash:43776k(user)," \
 474                                                 "16m(rootfs),"          \
 475                                                 "4m(kernel),"           \
 476                                                 "256k(dtb),"            \
 477                                                 "1m(u-boot);"           \
 478                                         "mpc5121.nand:-(data)"
 479
 480
 481 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
 482
 483 #define CONFIG_DOS_PARTITION
 484 #define CONFIG_MAC_PARTITION
 485 #define CONFIG_ISO_PARTITION
 486
 487 #define CONFIG_CMD_FAT
 488 #define CONFIG_SUPPORT_VFAT
 489
 490 #endif /* defined(CONFIG_CMD_IDE) */
 491
 492 /*
 493  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 494  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 495  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 496  * to chapter 36 of the MPC5121e Reference Manual.
 497  */
 498 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 499 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 500
 501  /*
 502  * Miscellaneous configurable options
 503  */
 504 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 505 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 506 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 507
 508 #ifdef CONFIG_CMD_KGDB
 509         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 510 #else
 511         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 512 #endif
 513
 514
 515 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 516 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 517 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 518 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 519
 520 /*
 521  * For booting Linux, the board info and command line data
 522  * have to be in the first 256 MB of memory, since this is
 523  * the maximum mapped by the Linux kernel during initialization.
 524  */
 525 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 526
 527 /* Cache Configuration */
 528 #define CONFIG_SYS_DCACHE_SIZE          32768
 529 #define CONFIG_SYS_CACHELINE_SIZE       32
 530 #ifdef CONFIG_CMD_KGDB
 531 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 532 #endif
 533
 534 #define CONFIG_SYS_HID0_INIT    0x000000000
 535 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 536 #define CONFIG_SYS_HID2 HID2_HBE
 537
 538 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 539
 540 #ifdef CONFIG_CMD_KGDB
 541 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 542 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 543 #endif
 544
 545 /*
 546  * Environment Configuration
 547  */
 548 #define CONFIG_TIMESTAMP
 549
 550 #define CONFIG_HOSTNAME         mpc5121ads
 551 #define CONFIG_BOOTFILE         "mpc5121ads/uImage"
 552 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 553
 554 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 555
 556 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 557 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 558
 559 #define CONFIG_BAUDRATE         115200
 560
 561 #define CONFIG_PREBOOT  "echo;" \
 562         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 563         "echo"
 564
 565 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 566         "u-boot_addr_r=200000\0"                                        \
 567         "kernel_addr_r=600000\0"                                        \
 568         "fdt_addr_r=880000\0"                                           \
 569         "ramdisk_addr_r=900000\0"                                       \
 570         "u-boot_addr=FFF00000\0"                                        \
 571         "kernel_addr=FFAC0000\0"                                        \
 572         "fdt_addr=FFEC0000\0"                                           \
 573         "ramdisk_addr=FEAC0000\0"                                       \
 574         "ramdiskfile=mpc5121ads/uRamdisk\0"                             \
 575         "u-boot=mpc5121ads/u-boot.bin\0"                                \
 576         "bootfile=mpc5121ads/uImage\0"                                  \
 577         "fdtfile=mpc5121ads/mpc5121ads.dtb\0"                           \
 578         "rootpath=/opt/eldk/ppc_6xx\n"                                  \
 579         "netdev=eth0\0"                                                 \
 580         "consdev=ttyPSC0\0"                                             \
 581         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 582                 "nfsroot=${serverip}:${rootpath}\0"                     \
 583         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 584         "addip=setenv bootargs ${bootargs} "                            \
 585                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 586                 ":${hostname}:${netdev}:off panic=1\0"                  \
 587         "addtty=setenv bootargs ${bootargs} "                           \
 588                 "console=${consdev},${baudrate}\0"                      \
 589         "flash_nfs=run nfsargs addip addtty;"                           \
 590                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 591         "flash_self=run ramargs addip addtty;"                          \
 592                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 593         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 594                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 595                 "run nfsargs addip addtty;"                             \
 596                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 597         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 598                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 599                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 600                 "run ramargs addip addtty;"                             \
 601                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 602         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 603         "update=protect off ${u-boot_addr} +${filesize};"               \
 604                 "era ${u-boot_addr} +${filesize};"                      \
 605                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 606         "upd=run load update\0"                                         \
 607         ""
 608
 609 #define CONFIG_BOOTCOMMAND      "run flash_self"
 610
 611 #define CONFIG_OF_LIBFDT        1
 612 #define CONFIG_OF_BOARD_SETUP   1
 613 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 614
 615 #define OF_CPU                  "PowerPC,5121@0"
 616 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 617 #define OF_TBCLK                (bd->bi_busfreq / 4)
 618 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 619
 620 /*-----------------------------------------------------------------------
 621  * IDE/ATA stuff
 622  *-----------------------------------------------------------------------
 623  */
 624
 625 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 626 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 627 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 628
 629 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 630 #define CONFIG_IDE_PREINIT
 631
 632 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 633 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 634
 635 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 636 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 637
 638 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 639 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 640
 641 /* Offset for normal register accesses  */
 642 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 643
 644 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 645 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 646
 647 /* Interval between registers   */
 648 #define CONFIG_SYS_ATA_STRIDE           4
 649
 650 #define ATA_BASE_ADDR                   get_pata_base()
 651
 652 /*
 653  * Control register bit definitions
 654  */
 655 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 656 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 657 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 658 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 659 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 660 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 661 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 662 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 663
 664 #endif  /* __CONFIG_H */